[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
#include "radeon.h"

#include <drm/drm_fb_helper.h>

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a radeon fb
   the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct list_head fbdev_list;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
	.fb_debug_enter = drm_fb_helper_debug_enter,
	.fb_debug_leave = drm_fb_helper_debug_leave,
};


int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 bpp, depth;

	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
						  fb_tiled) * ((bpp + 1) / 8);

	if (rdev->family >= CHIP_R600)
		height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       false, true,
				       &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gem_to_radeon_bo(gobj);

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitches[0]);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	/* Only 27 bit offset for legacy CRTC */
	ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
				       ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
				       NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper;
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	rbo = gem_to_radeon_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = framebuffer_alloc(0, device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	info->par = rfbdev;

	ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out_unref;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;
	rfbdev->helper.fbdev = info;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures = alloc_apertures(1);
	if (!info->apertures) {
		ret = -ENOMEM;
		goto out_unref;
	}
	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = rdev->mc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}

	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	if (ret) {
		ret = -ENOMEM;
		goto out_unref;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

void radeon_fb_output_poll_changed(struct radeon_device *rdev)
{
	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = &rfbdev->rfb;

	if (rfbdev->helper.fbdev) {
		info = rfbdev->helper.fbdev;

		unregister_framebuffer(info);
		if (info->cmap.len)
			fb_dealloc_cmap(&info->cmap);
		framebuffer_release(info);
	}

	if (rfb->obj) {
		radeonfb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_unregister_private(&rfb->base);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
	.fb_probe = radeonfb_create,
};

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;

	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
				 rdev->num_crtc,
				 RADEONFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);

	/* disable all the possible outputs/crtcs before entering KMS mode */
	drm_helper_disable_unused_functions(rdev->ddev);

	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
}

int radeon_fbdev_total_size(struct radeon_device *rdev)
{
	struct radeon_bo *robj;
	int size = 0;

	robj = gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj);
	size += radeon_bo_size(robj);
	return size;
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
		return true;
	return false;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
5a0e3ad6	27	#include <linux/slab.h>
771fe6b9	28	#include <linux/fb.h>
771fe6b9	29
760285e7 DH	30	#include <drm/drmP.h>
	31	#include <drm/drm_crtc.h>
	32	#include <drm/drm_crtc_helper.h>
	33	#include <drm/radeon_drm.h>
771fe6b9 JG	34	#include "radeon.h"
771fe6b9 JG	35
760285e7	36	#include <drm/drm_fb_helper.h>
785b93ef	37
6a9ee8af DA	38	#include <linux/vga_switcheroo.h>
6a9ee8af DA	39
38651674 DA	40	/* object hierarchy -
	41	this contains a helper + a radeon fb
	42	the helper contains a pointer to radeon framebuffer baseclass.
	43	*/
8be48d92	44	struct radeon_fbdev {
785b93ef	45	struct drm_fb_helper helper;
38651674 DA	46	struct radeon_framebuffer rfb;
	47	struct list_head fbdev_list;
	48	struct radeon_device *rdev;
771fe6b9 JG	49	};
771fe6b9 JG	50
771fe6b9 JG	51	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	52	.owner = THIS_MODULE,
c88f9f0c	53	.fb_check_var = drm_fb_helper_check_var,
785b93ef	54	.fb_set_par = drm_fb_helper_set_par,
771fe6b9 JG	55	.fb_fillrect = cfb_fillrect,
	56	.fb_copyarea = cfb_copyarea,
	57	.fb_imageblit = cfb_imageblit,
785b93ef DA	58	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	59	.fb_blank = drm_fb_helper_blank,
068143d3	60	.fb_setcmap = drm_fb_helper_setcmap,
4dd19b0d CB	61	.fb_debug_enter = drm_fb_helper_debug_enter,
4dd19b0d CB	62	.fb_debug_leave = drm_fb_helper_debug_leave,
771fe6b9 JG	63	};
771fe6b9 JG	64
771fe6b9	65
ff72145b	66	int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	67	{
771fe6b9 JG	68	int aligned = width;
e024e110	69	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	70	int pitch_mask = 0;
	71
	72	switch (bpp / 8) {
	73	case 1:
	74	pitch_mask = align_large ? 255 : 127;
	75	break;
	76	case 2:
	77	pitch_mask = align_large ? 127 : 31;
	78	break;
	79	case 3:
	80	case 4:
	81	pitch_mask = align_large ? 63 : 15;
	82	break;
	83	}
	84
	85	aligned += pitch_mask;
	86	aligned &= ~pitch_mask;
	87	return aligned;
	88	}
	89
8be48d92	90	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	91	{
7e4d15d9	92	struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
8be48d92 DA	93	int ret;
	94
	95	ret = radeon_bo_reserve(rbo, false);
	96	if (likely(ret == 0)) {
	97	radeon_bo_kunmap(rbo);
29d08b3e	98	radeon_bo_unpin(rbo);
8be48d92 DA	99	radeon_bo_unreserve(rbo);
	100	}
	101	drm_gem_object_unreference_unlocked(gobj);
	102	}
785b93ef	103
8be48d92	104	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
308e5bcb	105	struct drm_mode_fb_cmd2 *mode_cmd,
8be48d92	106	struct drm_gem_object **gobj_p)
771fe6b9	107	{
8be48d92	108	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	109	struct drm_gem_object *gobj = NULL;
4c788679	110	struct radeon_bo *rbo = NULL;
e024e110	111	bool fb_tiled = false; /* useful for testing */
c88f9f0c	112	u32 tiling_flags = 0;
8be48d92 DA	113	int ret;
8be48d92 DA	114	int aligned_size, size;
e40b6fc8	115	int height = mode_cmd->height;
308e5bcb JB	116	u32 bpp, depth;
308e5bcb JB	117
248dbc23	118	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
771fe6b9	119
771fe6b9	120	/* need to align pitch with crtc limits */
308e5bcb JB	121	mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
308e5bcb JB	122	fb_tiled) * ((bpp + 1) / 8);
771fe6b9	123
e40b6fc8 DA	124	if (rdev->family >= CHIP_R600)
e40b6fc8 DA	125	height = ALIGN(mode_cmd->height, 8);
308e5bcb	126	size = mode_cmd->pitches[0] * height;
771fe6b9	127	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	128	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92	129	RADEON_GEM_DOMAIN_VRAM,
4dfe947e	130	false, true,
8be48d92	131	&gobj);
771fe6b9	132	if (ret) {
8be48d92 DA	133	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	134	aligned_size);
	135	return -ENOMEM;
771fe6b9	136	}
7e4d15d9	137	rbo = gem_to_radeon_bo(gobj);
771fe6b9	138
e024e110	139	if (fb_tiled)
c88f9f0c MD	140	tiling_flags = RADEON_TILING_MACRO;
	141
	142	#ifdef __BIG_ENDIAN
435ddd92	143	switch (bpp) {
c88f9f0c MD	144	case 32:
	145	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	146	break;
	147	case 16:
	148	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	149	default:
	150	break;
	151	}
	152	#endif
	153
4c788679 JG	154	if (tiling_flags) {
4c788679 JG	155	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92	156	tiling_flags \| RADEON_TILING_SURFACE,
308e5bcb	157	mode_cmd->pitches[0]);
4c788679 JG	158	if (ret)
	159	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	160	}
8be48d92	161
38651674	162
4c788679 JG	163	ret = radeon_bo_reserve(rbo, false);
	164	if (unlikely(ret != 0))
	165	goto out_unref;
0349af70 MD	166	/* Only 27 bit offset for legacy CRTC */
	167	ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
	168	ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
	169	NULL);
4c788679 JG	170	if (ret) {
	171	radeon_bo_unreserve(rbo);
	172	goto out_unref;
	173	}
	174	if (fb_tiled)
	175	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	176	ret = radeon_bo_kmap(rbo, NULL);
4c788679	177	radeon_bo_unreserve(rbo);
f92e93eb	178	if (ret) {
f92e93eb JG	179	goto out_unref;
f92e93eb JG	180	}
771fe6b9	181
8be48d92 DA	182	*gobj_p = gobj;
	183	return 0;
	184	out_unref:
	185	radeonfb_destroy_pinned_object(gobj);
	186	*gobj_p = NULL;
	187	return ret;
	188	}
	189
cd5428a5	190	static int radeonfb_create(struct drm_fb_helper *helper,
8be48d92 DA	191	struct drm_fb_helper_surface_size *sizes)
8be48d92 DA	192	{
cd5428a5	193	struct radeon_fbdev rfbdev = (struct radeon_fbdev )helper;
8be48d92 DA	194	struct radeon_device *rdev = rfbdev->rdev;
	195	struct fb_info *info;
	196	struct drm_framebuffer *fb = NULL;
308e5bcb	197	struct drm_mode_fb_cmd2 mode_cmd;
8be48d92 DA	198	struct drm_gem_object *gobj = NULL;
	199	struct radeon_bo *rbo = NULL;
	200	struct device *device = &rdev->pdev->dev;
	201	int ret;
	202	unsigned long tmp;
	203
	204	mode_cmd.width = sizes->surface_width;
	205	mode_cmd.height = sizes->surface_height;
	206
	207	/* avivo can't scanout real 24bpp */
	208	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	209	sizes->surface_bpp = 32;
	210
308e5bcb JB	211	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
308e5bcb JB	212	sizes->surface_depth);
771fe6b9	213
8be48d92	214	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
aaefcd42 DA	215	if (ret) {
	216	DRM_ERROR("failed to create fbcon object %d\n", ret);
	217	return ret;
	218	}
	219
7e4d15d9	220	rbo = gem_to_radeon_bo(gobj);
771fe6b9	221
8be48d92 DA	222	/* okay we have an object now allocate the framebuffer */
8be48d92 DA	223	info = framebuffer_alloc(0, device);
771fe6b9 JG	224	if (info == NULL) {
	225	ret = -ENOMEM;
	226	goto out_unref;
	227	}
785b93ef	228
8be48d92	229	info->par = rfbdev;
771fe6b9	230
aaefcd42 DA	231	ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
aaefcd42 DA	232	if (ret) {
8b513d0c	233	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
aaefcd42 DA	234	goto out_unref;
aaefcd42 DA	235	}
8be48d92	236
38651674 DA	237	fb = &rfbdev->rfb.base;
	238
	239	/* setup helper */
	240	rfbdev->helper.fb = fb;
	241	rfbdev->helper.fbdev = info;
38651674	242
8be48d92	243	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	244
771fe6b9	245	strcpy(info->fix.id, "radeondrmfb");
785b93ef	246
01f2c773	247	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
3632ef89	248
8fd4bd22	249	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
771fe6b9	250	info->fbops = &radeonfb_ops;
785b93ef	251
8be48d92	252	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	253	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	254	info->fix.smem_len = radeon_bo_size(rbo);
	255	info->screen_base = rbo->kptr;
	256	info->screen_size = radeon_bo_size(rbo);
785b93ef	257
38651674	258	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	259
ed8f0d9e DA	260	/* setup aperture base/size for vesafb takeover */
1471ca9a MS	261	info->apertures = alloc_apertures(1);
	262	if (!info->apertures) {
	263	ret = -ENOMEM;
	264	goto out_unref;
	265	}
	266	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
68d30596	267	info->apertures->ranges[0].size = rdev->mc.aper_size;
ed8f0d9e	268
fb2a99e1	269	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
4abe3520	270
771fe6b9 JG	271	if (info->screen_base == NULL) {
	272	ret = -ENOSPC;
	273	goto out_unref;
	274	}
4abe3520 DA	275
	276	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	277	if (ret) {
	278	ret = -ENOMEM;
	279	goto out_unref;
	280	}
	281
771fe6b9 JG	282	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
771fe6b9 JG	283	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	284	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9	285	DRM_INFO("fb depth is %d\n", fb->depth);
01f2c773	286	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
771fe6b9	287
6a9ee8af	288	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	289	return 0;
	290
	291	out_unref:
4c788679	292	if (rbo) {
8be48d92	293
771fe6b9	294	}
f92e93eb	295	if (fb && ret) {
771fe6b9	296	drm_gem_object_unreference(gobj);
36206361	297	drm_framebuffer_unregister_private(fb);
771fe6b9 JG	298	drm_framebuffer_cleanup(fb);
	299	kfree(fb);
	300	}
771fe6b9 JG	301	return ret;
	302	}
	303
eb1f8e4f	304	void radeon_fb_output_poll_changed(struct radeon_device *rdev)
771fe6b9	305	{
eb1f8e4f	306	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
771fe6b9	307	}
771fe6b9	308
8be48d92	309	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9 JG	310	{
771fe6b9 JG	311	struct fb_info *info;
38651674	312	struct radeon_framebuffer *rfb = &rfbdev->rfb;
771fe6b9	313
8be48d92 DA	314	if (rfbdev->helper.fbdev) {
8be48d92 DA	315	info = rfbdev->helper.fbdev;
4abe3520	316
8be48d92	317	unregister_framebuffer(info);
4abe3520 DA	318	if (info->cmap.len)
4abe3520 DA	319	fb_dealloc_cmap(&info->cmap);
8be48d92	320	framebuffer_release(info);
771fe6b9	321	}
771fe6b9	322
8be48d92	323	if (rfb->obj) {
29d08b3e DA	324	radeonfb_destroy_pinned_object(rfb->obj);
29d08b3e DA	325	rfb->obj = NULL;
771fe6b9	326	}
4abe3520	327	drm_fb_helper_fini(&rfbdev->helper);
36206361	328	drm_framebuffer_unregister_private(&rfb->base);
38651674	329	drm_framebuffer_cleanup(&rfb->base);
771fe6b9	330
771fe6b9 JG	331	return 0;
771fe6b9 JG	332	}
785b93ef	333
4abe3520 DA	334	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	335	.gamma_set = radeon_crtc_fb_gamma_set,
	336	.gamma_get = radeon_crtc_fb_gamma_get,
cd5428a5	337	.fb_probe = radeonfb_create,
4abe3520	338	};
38651674 DA	339
	340	int radeon_fbdev_init(struct radeon_device *rdev)
	341	{
8be48d92	342	struct radeon_fbdev *rfbdev;
4abe3520	343	int bpp_sel = 32;
5a79395b	344	int ret;
4abe3520 DA	345
	346	/* select 8 bpp console on RN50 or 16MB cards */
	347	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	348	bpp_sel = 8;
8be48d92 DA	349
	350	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	351	if (!rfbdev)
	352	return -ENOMEM;
	353
	354	rfbdev->rdev = rdev;
	355	rdev->mode_info.rfbdev = rfbdev;
4abe3520	356	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
8be48d92	357
5a79395b CW	358	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
	359	rdev->num_crtc,
	360	RADEONFB_CONN_LIMIT);
	361	if (ret) {
	362	kfree(rfbdev);
	363	return ret;
	364	}
	365
0b4c0f3f	366	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
76a39dbf DV	367
	368	/* disable all the possible outputs/crtcs before entering KMS mode */
	369	drm_helper_disable_unused_functions(rdev->ddev);
	370
4abe3520	371	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
771fe6b9	372	return 0;
38651674 DA	373	}
	374
	375	void radeon_fbdev_fini(struct radeon_device *rdev)
	376	{
8be48d92 DA	377	if (!rdev->mode_info.rfbdev)
	378	return;
	379
38651674	380	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	381	kfree(rdev->mode_info.rfbdev);
38651674 DA	382	rdev->mode_info.rfbdev = NULL;
	383	}
	384
	385	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	386	{
	387	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
	388	}
	389
	390	int radeon_fbdev_total_size(struct radeon_device *rdev)
	391	{
	392	struct radeon_bo *robj;
	393	int size = 0;
	394
7e4d15d9	395	robj = gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj);
38651674 DA	396	size += radeon_bo_size(robj);
	397	return size;
	398	}
	399
	400	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
	401	{
7e4d15d9	402	if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
38651674 DA	403	return true;
38651674 DA	404	return false;
771fe6b9	405	}