[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_fence.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Dave Airlie
 */
#include <linux/seq_file.h>
#include <linux/atomic.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <linux/kref.h>
#include <linux/slab.h>
#include "drmP.h"
#include "drm.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_trace.h"

static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
{
	u32 scratch_index;

	if (rdev->wb.enabled) {
		if (rdev->wb.use_event)
			scratch_index = R600_WB_EVENT_OFFSET +
				rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
		else
			scratch_index = RADEON_WB_SCRATCH_OFFSET +
				rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
		rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);
	} else
		WREG32(rdev->fence_drv[ring].scratch_reg, seq);
}

static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
{
	u32 seq = 0;
	u32 scratch_index;

	if (rdev->wb.enabled) {
		if (rdev->wb.use_event)
			scratch_index = R600_WB_EVENT_OFFSET +
				rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
		else
			scratch_index = RADEON_WB_SCRATCH_OFFSET +
				rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
		seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
	} else
		seq = RREG32(rdev->fence_drv[ring].scratch_reg);
	return seq;
}

int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
{
	unsigned long irq_flags;

	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	if (fence->emitted) {
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
		return 0;
	}
	fence->seq = atomic_add_return(1, &rdev->fence_drv[fence->ring].seq);
	if (!rdev->cp.ready)
		/* FIXME: cp is not running assume everythings is done right
		 * away
		 */
		radeon_fence_write(rdev, fence->seq, fence->ring);
	else
		radeon_fence_ring_emit(rdev, fence);

	trace_radeon_fence_emit(rdev->ddev, fence->seq);
	fence->emitted = true;
	list_move_tail(&fence->list, &rdev->fence_drv[fence->ring].emitted);
	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	return 0;
}

static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
{
	struct radeon_fence *fence;
	struct list_head *i, *n;
	uint32_t seq;
	bool wake = false;
	unsigned long cjiffies;

	seq = radeon_fence_read(rdev, ring);
	if (seq != rdev->fence_drv[ring].last_seq) {
		rdev->fence_drv[ring].last_seq = seq;
		rdev->fence_drv[ring].last_jiffies = jiffies;
		rdev->fence_drv[ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
	} else {
		cjiffies = jiffies;
		if (time_after(cjiffies, rdev->fence_drv[ring].last_jiffies)) {
			cjiffies -= rdev->fence_drv[ring].last_jiffies;
			if (time_after(rdev->fence_drv[ring].last_timeout, cjiffies)) {
				/* update the timeout */
				rdev->fence_drv[ring].last_timeout -= cjiffies;
			} else {
				/* the 500ms timeout is elapsed we should test
				 * for GPU lockup
				 */
				rdev->fence_drv[ring].last_timeout = 1;
			}
		} else {
			/* wrap around update last jiffies, we will just wait
			 * a little longer
			 */
			rdev->fence_drv[ring].last_jiffies = cjiffies;
		}
		return false;
	}
	n = NULL;
	list_for_each(i, &rdev->fence_drv[ring].emitted) {
		fence = list_entry(i, struct radeon_fence, list);
		if (fence->seq == seq) {
			n = i;
			break;
		}
	}
	/* all fence previous to this one are considered as signaled */
	if (n) {
		i = n;
		do {
			n = i->prev;
			list_move_tail(i, &rdev->fence_drv[ring].signaled);
			fence = list_entry(i, struct radeon_fence, list);
			fence->signaled = true;
			i = n;
		} while (i != &rdev->fence_drv[ring].emitted);
		wake = true;
	}
	return wake;
}

static void radeon_fence_destroy(struct kref *kref)
{
	unsigned long irq_flags;
        struct radeon_fence *fence;

	fence = container_of(kref, struct radeon_fence, kref);
	write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
	list_del(&fence->list);
	fence->emitted = false;
	write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
	kfree(fence);
}

int radeon_fence_create(struct radeon_device *rdev,
			struct radeon_fence **fence,
			int ring)
{
	unsigned long irq_flags;

	*fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
	if ((*fence) == NULL) {
		return -ENOMEM;
	}
	kref_init(&((*fence)->kref));
	(*fence)->rdev = rdev;
	(*fence)->emitted = false;
	(*fence)->signaled = false;
	(*fence)->seq = 0;
	(*fence)->ring = ring;
	INIT_LIST_HEAD(&(*fence)->list);

	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	list_add_tail(&(*fence)->list, &rdev->fence_drv[ring].created);
	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	return 0;
}

bool radeon_fence_signaled(struct radeon_fence *fence)
{
	unsigned long irq_flags;
	bool signaled = false;

	if (!fence)
		return true;

	if (fence->rdev->gpu_lockup)
		return true;

	write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
	signaled = fence->signaled;
	/* if we are shuting down report all fence as signaled */
	if (fence->rdev->shutdown) {
		signaled = true;
	}
	if (!fence->emitted) {
		WARN(1, "Querying an unemitted fence : %p !\n", fence);
		signaled = true;
	}
	if (!signaled) {
		radeon_fence_poll_locked(fence->rdev, fence->ring);
		signaled = fence->signaled;
	}
	write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
	return signaled;
}

int radeon_fence_wait(struct radeon_fence *fence, bool intr)
{
	struct radeon_device *rdev;
	unsigned long irq_flags, timeout;
	u32 seq;
	int r;

	if (fence == NULL) {
		WARN(1, "Querying an invalid fence : %p !\n", fence);
		return 0;
	}
	rdev = fence->rdev;
	if (radeon_fence_signaled(fence)) {
		return 0;
	}
	timeout = rdev->fence_drv[fence->ring].last_timeout;
retry:
	/* save current sequence used to check for GPU lockup */
	seq = rdev->fence_drv[fence->ring].last_seq;
	trace_radeon_fence_wait_begin(rdev->ddev, seq);
	if (intr) {
		radeon_irq_kms_sw_irq_get(rdev);
		r = wait_event_interruptible_timeout(rdev->fence_drv[fence->ring].queue,
				radeon_fence_signaled(fence), timeout);
		radeon_irq_kms_sw_irq_put(rdev);
		if (unlikely(r < 0)) {
			return r;
		}
	} else {
		radeon_irq_kms_sw_irq_get(rdev);
		r = wait_event_timeout(rdev->fence_drv[fence->ring].queue,
			 radeon_fence_signaled(fence), timeout);
		radeon_irq_kms_sw_irq_put(rdev);
	}
	trace_radeon_fence_wait_end(rdev->ddev, seq);
	if (unlikely(!radeon_fence_signaled(fence))) {
		/* we were interrupted for some reason and fence isn't
		 * isn't signaled yet, resume wait
		 */
		if (r) {
			timeout = r;
			goto retry;
		}
		/* don't protect read access to rdev->fence_drv[t].last_seq
		 * if we experiencing a lockup the value doesn't change
		 */
		if (seq == rdev->fence_drv[fence->ring].last_seq &&
		    radeon_gpu_is_lockup(rdev)) {
			/* good news we believe it's a lockup */
			printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
			     fence->seq, seq);
			/* FIXME: what should we do ? marking everyone
			 * as signaled for now
			 */
			rdev->gpu_lockup = true;
			r = radeon_gpu_reset(rdev);
			if (r)
				return r;
			radeon_fence_write(rdev, fence->seq, fence->ring);
			rdev->gpu_lockup = false;
		}
		timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
		write_lock_irqsave(&rdev->fence_lock, irq_flags);
		rdev->fence_drv[fence->ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
		rdev->fence_drv[fence->ring].last_jiffies = jiffies;
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
		goto retry;
	}
	return 0;
}

int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
{
	unsigned long irq_flags;
	struct radeon_fence *fence;
	int r;

	if (rdev->gpu_lockup) {
		return 0;
	}
	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	if (list_empty(&rdev->fence_drv[ring].emitted)) {
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
		return 0;
	}
	fence = list_entry(rdev->fence_drv[ring].emitted.next,
			   struct radeon_fence, list);
	radeon_fence_ref(fence);
	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	r = radeon_fence_wait(fence, false);
	radeon_fence_unref(&fence);
	return r;
}

int radeon_fence_wait_last(struct radeon_device *rdev, int ring)
{
	unsigned long irq_flags;
	struct radeon_fence *fence;
	int r;

	if (rdev->gpu_lockup) {
		return 0;
	}
	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	if (list_empty(&rdev->fence_drv[ring].emitted)) {
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
		return 0;
	}
	fence = list_entry(rdev->fence_drv[ring].emitted.prev,
			   struct radeon_fence, list);
	radeon_fence_ref(fence);
	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	r = radeon_fence_wait(fence, false);
	radeon_fence_unref(&fence);
	return r;
}

struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
{
	kref_get(&fence->kref);
	return fence;
}

void radeon_fence_unref(struct radeon_fence **fence)
{
	struct radeon_fence *tmp = *fence;

	*fence = NULL;
	if (tmp) {
		kref_put(&tmp->kref, radeon_fence_destroy);
	}
}

void radeon_fence_process(struct radeon_device *rdev, int ring)
{
	unsigned long irq_flags;
	bool wake;

	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	wake = radeon_fence_poll_locked(rdev, ring);
	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	if (wake) {
		wake_up_all(&rdev->fence_drv[ring].queue);
	}
}

int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings)
{
	unsigned long irq_flags;
	int r, ring;

	for (ring = 0; ring < num_rings; ring++) {
		write_lock_irqsave(&rdev->fence_lock, irq_flags);
		r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
		if (r) {
			dev_err(rdev->dev, "fence failed to get scratch register\n");
			write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
			return r;
		}
		radeon_fence_write(rdev, 0, ring);
		atomic_set(&rdev->fence_drv[ring].seq, 0);
		INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
		INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
		INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
		init_waitqueue_head(&rdev->fence_drv[ring].queue);
		rdev->fence_drv[ring].initialized = true;
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	}
	for (ring = num_rings; ring < RADEON_NUM_RINGS; ring++) {
		write_lock_irqsave(&rdev->fence_lock, irq_flags);
		INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
		INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
		INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
		rdev->fence_drv[ring].initialized = false;
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	}
	if (radeon_debugfs_fence_init(rdev)) {
		dev_err(rdev->dev, "fence debugfs file creation failed\n");
	}
	return 0;
}

void radeon_fence_driver_fini(struct radeon_device *rdev)
{
	unsigned long irq_flags;
	int ring;

	for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
		if (!rdev->fence_drv[ring].initialized)
			continue;
		wake_up_all(&rdev->fence_drv[ring].queue);
		write_lock_irqsave(&rdev->fence_lock, irq_flags);
		radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
		write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
		rdev->fence_drv[ring].initialized = false;
	}
}


/*
 * Fence debugfs
 */
#if defined(CONFIG_DEBUG_FS)
static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_fence *fence;
	int i;

	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		if (!rdev->fence_drv[i].initialized)
			continue;

		seq_printf(m, "--- ring %d ---\n", i);
		seq_printf(m, "Last signaled fence 0x%08X\n",
			   radeon_fence_read(rdev, i));
		if (!list_empty(&rdev->fence_drv[i].emitted)) {
			fence = list_entry(rdev->fence_drv[i].emitted.prev,
					   struct radeon_fence, list);
			seq_printf(m, "Last emitted fence %p with 0x%08X\n",
				   fence,  fence->seq);
		}
	}
	return 0;
}

static struct drm_info_list radeon_debugfs_fence_list[] = {
	{"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
};
#endif

int radeon_debugfs_fence_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
#else
	return 0;
#endif
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Dave Airlie
	30	*/
	31	#include <linux/seq_file.h>
60063497	32	#include <linux/atomic.h>
771fe6b9 JG	33	#include <linux/wait.h>
	34	#include <linux/list.h>
	35	#include <linux/kref.h>
5a0e3ad6	36	#include <linux/slab.h>
771fe6b9 JG	37	#include "drmP.h"
	38	#include "drm.h"
	39	#include "radeon_reg.h"
	40	#include "radeon.h"
99ee7fac	41	#include "radeon_trace.h"
771fe6b9	42
7465280c	43	static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
b81157d0	44	{
7465280c AD	45	u32 scratch_index;
7465280c AD	46
b81157d0	47	if (rdev->wb.enabled) {
b81157d0	48	if (rdev->wb.use_event)
7465280c AD	49	scratch_index = R600_WB_EVENT_OFFSET +
7465280c AD	50	rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
b81157d0	51	else
7465280c AD	52	scratch_index = RADEON_WB_SCRATCH_OFFSET +
7465280c AD	53	rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
69932487	54	rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);
b81157d0	55	} else
7465280c	56	WREG32(rdev->fence_drv[ring].scratch_reg, seq);
b81157d0 AD	57	}
b81157d0 AD	58
7465280c	59	static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
b81157d0	60	{
7465280c AD	61	u32 seq = 0;
7465280c AD	62	u32 scratch_index;
b81157d0 AD	63
b81157d0 AD	64	if (rdev->wb.enabled) {
b81157d0	65	if (rdev->wb.use_event)
7465280c AD	66	scratch_index = R600_WB_EVENT_OFFSET +
7465280c AD	67	rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
b81157d0	68	else
7465280c AD	69	scratch_index = RADEON_WB_SCRATCH_OFFSET +
7465280c AD	70	rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
b81157d0 AD	71	seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
b81157d0 AD	72	} else
7465280c	73	seq = RREG32(rdev->fence_drv[ring].scratch_reg);
b81157d0 AD	74	return seq;
	75	}
	76
771fe6b9 JG	77	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence fence)
	78	{
	79	unsigned long irq_flags;
	80
7465280c	81	write_lock_irqsave(&rdev->fence_lock, irq_flags);
851a6bd9	82	if (fence->emitted) {
7465280c	83	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	84	return 0;
771fe6b9 JG	85	}
7465280c	86	fence->seq = atomic_add_return(1, &rdev->fence_drv[fence->ring].seq);
b81157d0	87	if (!rdev->cp.ready)
771fe6b9 JG	88	/* FIXME: cp is not running assume everythings is done right
	89	* away
	90	*/
7465280c	91	radeon_fence_write(rdev, fence->seq, fence->ring);
b81157d0	92	else
771fe6b9	93	radeon_fence_ring_emit(rdev, fence);
3ce0a23d	94
99ee7fac	95	trace_radeon_fence_emit(rdev->ddev, fence->seq);
851a6bd9	96	fence->emitted = true;
7465280c AD	97	list_move_tail(&fence->list, &rdev->fence_drv[fence->ring].emitted);
7465280c AD	98	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	99	return 0;
	100	}
	101
7465280c	102	static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
771fe6b9 JG	103	{
	104	struct radeon_fence *fence;
	105	struct list_head i, n;
	106	uint32_t seq;
	107	bool wake = false;
225758d8	108	unsigned long cjiffies;
771fe6b9	109
7465280c AD	110	seq = radeon_fence_read(rdev, ring);
	111	if (seq != rdev->fence_drv[ring].last_seq) {
	112	rdev->fence_drv[ring].last_seq = seq;
	113	rdev->fence_drv[ring].last_jiffies = jiffies;
	114	rdev->fence_drv[ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
225758d8 JG	115	} else {
225758d8 JG	116	cjiffies = jiffies;
7465280c AD	117	if (time_after(cjiffies, rdev->fence_drv[ring].last_jiffies)) {
	118	cjiffies -= rdev->fence_drv[ring].last_jiffies;
	119	if (time_after(rdev->fence_drv[ring].last_timeout, cjiffies)) {
225758d8	120	/* update the timeout */
7465280c	121	rdev->fence_drv[ring].last_timeout -= cjiffies;
225758d8 JG	122	} else {
	123	/* the 500ms timeout is elapsed we should test
	124	* for GPU lockup
	125	*/
7465280c	126	rdev->fence_drv[ring].last_timeout = 1;
225758d8 JG	127	}
	128	} else {
	129	/* wrap around update last jiffies, we will just wait
	130	* a little longer
	131	*/
7465280c	132	rdev->fence_drv[ring].last_jiffies = cjiffies;
225758d8 JG	133	}
	134	return false;
	135	}
771fe6b9	136	n = NULL;
7465280c	137	list_for_each(i, &rdev->fence_drv[ring].emitted) {
771fe6b9 JG	138	fence = list_entry(i, struct radeon_fence, list);
	139	if (fence->seq == seq) {
	140	n = i;
	141	break;
	142	}
	143	}
	144	/* all fence previous to this one are considered as signaled */
	145	if (n) {
	146	i = n;
	147	do {
	148	n = i->prev;
7465280c	149	list_move_tail(i, &rdev->fence_drv[ring].signaled);
771fe6b9 JG	150	fence = list_entry(i, struct radeon_fence, list);
	151	fence->signaled = true;
	152	i = n;
7465280c	153	} while (i != &rdev->fence_drv[ring].emitted);
771fe6b9 JG	154	wake = true;
	155	}
	156	return wake;
	157	}
	158
	159	static void radeon_fence_destroy(struct kref *kref)
	160	{
	161	unsigned long irq_flags;
	162	struct radeon_fence *fence;
	163
	164	fence = container_of(kref, struct radeon_fence, kref);
7465280c	165	write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
771fe6b9	166	list_del(&fence->list);
851a6bd9	167	fence->emitted = false;
7465280c	168	write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
771fe6b9 JG	169	kfree(fence);
	170	}
	171
7465280c AD	172	int radeon_fence_create(struct radeon_device *rdev,
	173	struct radeon_fence **fence,
	174	int ring)
771fe6b9 JG	175	{
	176	unsigned long irq_flags;
	177
	178	*fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
	179	if ((*fence) == NULL) {
	180	return -ENOMEM;
	181	}
	182	kref_init(&((*fence)->kref));
	183	(*fence)->rdev = rdev;
851a6bd9	184	(*fence)->emitted = false;
771fe6b9 JG	185	(*fence)->signaled = false;
771fe6b9 JG	186	(*fence)->seq = 0;
7465280c	187	(*fence)->ring = ring;
771fe6b9 JG	188	INIT_LIST_HEAD(&(*fence)->list);
771fe6b9 JG	189
7465280c AD	190	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	191	list_add_tail(&(*fence)->list, &rdev->fence_drv[ring].created);
	192	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	193	return 0;
	194	}
	195
771fe6b9 JG	196	bool radeon_fence_signaled(struct radeon_fence *fence)
771fe6b9 JG	197	{
771fe6b9 JG	198	unsigned long irq_flags;
	199	bool signaled = false;
	200
3655d54a	201	if (!fence)
771fe6b9	202	return true;
3655d54a DJ	203
3655d54a DJ	204	if (fence->rdev->gpu_lockup)
771fe6b9	205	return true;
3655d54a	206
7465280c	207	write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
771fe6b9 JG	208	signaled = fence->signaled;
	209	/* if we are shuting down report all fence as signaled */
	210	if (fence->rdev->shutdown) {
	211	signaled = true;
	212	}
851a6bd9 CK	213	if (!fence->emitted) {
851a6bd9 CK	214	WARN(1, "Querying an unemitted fence : %p !\n", fence);
771fe6b9 JG	215	signaled = true;
	216	}
	217	if (!signaled) {
7465280c	218	radeon_fence_poll_locked(fence->rdev, fence->ring);
771fe6b9 JG	219	signaled = fence->signaled;
771fe6b9 JG	220	}
7465280c	221	write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
771fe6b9 JG	222	return signaled;
	223	}
	224
3ce0a23d	225	int radeon_fence_wait(struct radeon_fence *fence, bool intr)
771fe6b9 JG	226	{
771fe6b9 JG	227	struct radeon_device *rdev;
225758d8 JG	228	unsigned long irq_flags, timeout;
225758d8 JG	229	u32 seq;
771fe6b9 JG	230	int r;
771fe6b9 JG	231
771fe6b9 JG	232	if (fence == NULL) {
	233	WARN(1, "Querying an invalid fence : %p !\n", fence);
	234	return 0;
	235	}
	236	rdev = fence->rdev;
	237	if (radeon_fence_signaled(fence)) {
	238	return 0;
	239	}
7465280c	240	timeout = rdev->fence_drv[fence->ring].last_timeout;
771fe6b9	241	retry:
225758d8	242	/* save current sequence used to check for GPU lockup */
7465280c	243	seq = rdev->fence_drv[fence->ring].last_seq;
99ee7fac	244	trace_radeon_fence_wait_begin(rdev->ddev, seq);
3ce0a23d	245	if (intr) {
1614f8b1	246	radeon_irq_kms_sw_irq_get(rdev);
7465280c	247	r = wait_event_interruptible_timeout(rdev->fence_drv[fence->ring].queue,
771fe6b9	248	radeon_fence_signaled(fence), timeout);
1614f8b1	249	radeon_irq_kms_sw_irq_put(rdev);
90aca4d2	250	if (unlikely(r < 0)) {
5cc6fbab	251	return r;
90aca4d2	252	}
771fe6b9	253	} else {
1614f8b1	254	radeon_irq_kms_sw_irq_get(rdev);
7465280c	255	r = wait_event_timeout(rdev->fence_drv[fence->ring].queue,
771fe6b9	256	radeon_fence_signaled(fence), timeout);
1614f8b1	257	radeon_irq_kms_sw_irq_put(rdev);
771fe6b9	258	}
99ee7fac	259	trace_radeon_fence_wait_end(rdev->ddev, seq);
771fe6b9	260	if (unlikely(!radeon_fence_signaled(fence))) {
225758d8 JG	261	/* we were interrupted for some reason and fence isn't
	262	* isn't signaled yet, resume wait
	263	*/
	264	if (r) {
	265	timeout = r;
	266	goto retry;
771fe6b9	267	}
7465280c	268	/* don't protect read access to rdev->fence_drv[t].last_seq
225758d8 JG	269	* if we experiencing a lockup the value doesn't change
225758d8 JG	270	*/
7465280c AD	271	if (seq == rdev->fence_drv[fence->ring].last_seq &&
7465280c AD	272	radeon_gpu_is_lockup(rdev)) {
225758d8	273	/* good news we believe it's a lockup */
19703058	274	printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
fce7d61b	275	fence->seq, seq);
225758d8 JG	276	/* FIXME: what should we do ? marking everyone
	277	* as signaled for now
	278	*/
90aca4d2	279	rdev->gpu_lockup = true;
90aca4d2 JG	280	r = radeon_gpu_reset(rdev);
	281	if (r)
	282	return r;
7465280c	283	radeon_fence_write(rdev, fence->seq, fence->ring);
90aca4d2	284	rdev->gpu_lockup = false;
771fe6b9	285	}
225758d8	286	timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
7465280c AD	287	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	288	rdev->fence_drv[fence->ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
	289	rdev->fence_drv[fence->ring].last_jiffies = jiffies;
	290	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	291	goto retry;
771fe6b9 JG	292	}
771fe6b9 JG	293	return 0;
	294	}
	295
7465280c	296	int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
771fe6b9 JG	297	{
	298	unsigned long irq_flags;
	299	struct radeon_fence *fence;
	300	int r;
	301
	302	if (rdev->gpu_lockup) {
	303	return 0;
	304	}
7465280c AD	305	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	306	if (list_empty(&rdev->fence_drv[ring].emitted)) {
	307	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	308	return 0;
771fe6b9 JG	309	}
7465280c	310	fence = list_entry(rdev->fence_drv[ring].emitted.next,
771fe6b9 JG	311	struct radeon_fence, list);
771fe6b9 JG	312	radeon_fence_ref(fence);
7465280c	313	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	314	r = radeon_fence_wait(fence, false);
	315	radeon_fence_unref(&fence);
	316	return r;
	317	}
	318
7465280c	319	int radeon_fence_wait_last(struct radeon_device *rdev, int ring)
771fe6b9 JG	320	{
	321	unsigned long irq_flags;
	322	struct radeon_fence *fence;
	323	int r;
	324
	325	if (rdev->gpu_lockup) {
	326	return 0;
	327	}
7465280c AD	328	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	329	if (list_empty(&rdev->fence_drv[ring].emitted)) {
	330	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	331	return 0;
771fe6b9 JG	332	}
7465280c	333	fence = list_entry(rdev->fence_drv[ring].emitted.prev,
771fe6b9 JG	334	struct radeon_fence, list);
771fe6b9 JG	335	radeon_fence_ref(fence);
7465280c	336	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9 JG	337	r = radeon_fence_wait(fence, false);
	338	radeon_fence_unref(&fence);
	339	return r;
	340	}
	341
	342	struct radeon_fence radeon_fence_ref(struct radeon_fence fence)
	343	{
	344	kref_get(&fence->kref);
	345	return fence;
	346	}
	347
	348	void radeon_fence_unref(struct radeon_fence **fence)
	349	{
	350	struct radeon_fence tmp = fence;
	351
	352	*fence = NULL;
	353	if (tmp) {
cdb650a4	354	kref_put(&tmp->kref, radeon_fence_destroy);
771fe6b9 JG	355	}
	356	}
	357
7465280c	358	void radeon_fence_process(struct radeon_device *rdev, int ring)
771fe6b9 JG	359	{
	360	unsigned long irq_flags;
	361	bool wake;
	362
7465280c AD	363	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	364	wake = radeon_fence_poll_locked(rdev, ring);
	365	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9	366	if (wake) {
7465280c	367	wake_up_all(&rdev->fence_drv[ring].queue);
771fe6b9 JG	368	}
	369	}
	370
7465280c	371	int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings)
771fe6b9 JG	372	{
771fe6b9 JG	373	unsigned long irq_flags;
7465280c	374	int r, ring;
771fe6b9	375
7465280c AD	376	for (ring = 0; ring < num_rings; ring++) {
	377	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	378	r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
	379	if (r) {
	380	dev_err(rdev->dev, "fence failed to get scratch register\n");
	381	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	382	return r;
	383	}
	384	radeon_fence_write(rdev, 0, ring);
	385	atomic_set(&rdev->fence_drv[ring].seq, 0);
	386	INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
	387	INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
	388	INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
	389	init_waitqueue_head(&rdev->fence_drv[ring].queue);
	390	rdev->fence_drv[ring].initialized = true;
	391	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	392	}
	393	for (ring = num_rings; ring < RADEON_NUM_RINGS; ring++) {
	394	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	395	INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
	396	INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
	397	INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
	398	rdev->fence_drv[ring].initialized = false;
	399	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
771fe6b9	400	}
771fe6b9	401	if (radeon_debugfs_fence_init(rdev)) {
0a0c7596	402	dev_err(rdev->dev, "fence debugfs file creation failed\n");
771fe6b9 JG	403	}
	404	return 0;
	405	}
	406
	407	void radeon_fence_driver_fini(struct radeon_device *rdev)
	408	{
	409	unsigned long irq_flags;
7465280c AD	410	int ring;
	411
	412	for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
	413	if (!rdev->fence_drv[ring].initialized)
	414	continue;
	415	wake_up_all(&rdev->fence_drv[ring].queue);
	416	write_lock_irqsave(&rdev->fence_lock, irq_flags);
	417	radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
	418	write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
	419	rdev->fence_drv[ring].initialized = false;
	420	}
771fe6b9 JG	421	}
	422
	423
	424	/*
	425	* Fence debugfs
	426	*/
	427	#if defined(CONFIG_DEBUG_FS)
	428	static int radeon_debugfs_fence_info(struct seq_file m, void data)
	429	{
	430	struct drm_info_node node = (struct drm_info_node )m->private;
	431	struct drm_device *dev = node->minor->dev;
	432	struct radeon_device *rdev = dev->dev_private;
	433	struct radeon_fence *fence;
7465280c AD	434	int i;
	435
	436	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
	437	if (!rdev->fence_drv[i].initialized)
	438	continue;
	439
	440	seq_printf(m, "--- ring %d ---\n", i);
	441	seq_printf(m, "Last signaled fence 0x%08X\n",
	442	radeon_fence_read(rdev, i));
	443	if (!list_empty(&rdev->fence_drv[i].emitted)) {
	444	fence = list_entry(rdev->fence_drv[i].emitted.prev,
	445	struct radeon_fence, list);
	446	seq_printf(m, "Last emitted fence %p with 0x%08X\n",
	447	fence, fence->seq);
	448	}
771fe6b9 JG	449	}
	450	return 0;
	451	}
	452
	453	static struct drm_info_list radeon_debugfs_fence_list[] = {
	454	{"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
	455	};
	456	#endif
	457
	458	int radeon_debugfs_fence_init(struct radeon_device *rdev)
	459	{
	460	#if defined(CONFIG_DEBUG_FS)
	461	return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
	462	#else
	463	return 0;
	464	#endif
	465	}