[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */
/**
 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Allocate system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 * Returns 0 for success, -ENOMEM for failure.
 */
int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
{
	void *ptr;

	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
				   &rdev->gart.table_addr);
	if (ptr == NULL) {
		return -ENOMEM;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_uc((unsigned long)ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	rdev->gart.ptr = ptr;
	memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
	return 0;
}

/**
 * radeon_gart_table_ram_free - free system ram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Free system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 */
void radeon_gart_table_ram_free(struct radeon_device *rdev)
{
	if (rdev->gart.ptr == NULL) {
		return;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_wb((unsigned long)rdev->gart.ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
			    (void *)rdev->gart.ptr,
			    rdev->gart.table_addr);
	rdev->gart.ptr = NULL;
	rdev->gart.table_addr = 0;
}

/**
 * radeon_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @rdev: radeon_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.robj == NULL) {
		r = radeon_bo_create(rdev, rdev->gart.table_size,
				     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
				     0, NULL, NULL, &rdev->gart.robj);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * radeon_gart_table_vram_pin - pin gart page table in vram
 *
 * @rdev: radeon_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int radeon_gart_table_vram_pin(struct radeon_device *rdev)
{
	uint64_t gpu_addr;
	int r;

	r = radeon_bo_reserve(rdev->gart.robj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->gart.robj,
				RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->gart.robj);
		return r;
	}
	r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
	if (r)
		radeon_bo_unpin(rdev->gart.robj);
	radeon_bo_unreserve(rdev->gart.robj);
	rdev->gart.table_addr = gpu_addr;

	if (!r) {
		int i;

		/* We might have dropped some GART table updates while it wasn't
		 * mapped, restore all entries
		 */
		for (i = 0; i < rdev->gart.num_gpu_pages; i++)
			radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
		mb();
		radeon_gart_tlb_flush(rdev);
	}

	return r;
}

/**
 * radeon_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @rdev: radeon_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.robj == NULL) {
		return;
	}
	r = radeon_bo_reserve(rdev->gart.robj, false);
	if (likely(r == 0)) {
		radeon_bo_kunmap(rdev->gart.robj);
		radeon_bo_unpin(rdev->gart.robj);
		radeon_bo_unreserve(rdev->gart.robj);
		rdev->gart.ptr = NULL;
	}
}

/**
 * radeon_gart_table_vram_free - free gart page table vram
 *
 * @rdev: radeon_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void radeon_gart_table_vram_free(struct radeon_device *rdev)
{
	if (rdev->gart.robj == NULL) {
		return;
	}
	radeon_bo_unref(&rdev->gart.robj);
}

/*
 * Common gart functions.
 */
/**
 * radeon_gart_unbind - unbind pages from the gart page table
 *
 * @rdev: radeon_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 */
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
	for (i = 0; i < pages; i++, p++) {
		if (rdev->gart.pages[p]) {
			rdev->gart.pages[p] = NULL;
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
				rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
				if (rdev->gart.ptr) {
					radeon_gart_set_page(rdev, t,
							     rdev->dummy_page.entry);
				}
			}
		}
	}
	if (rdev->gart.ptr) {
		mb();
		radeon_gart_tlb_flush(rdev);
	}
}

/**
 * radeon_gart_bind - bind pages into the gart page table
 *
 * @rdev: radeon_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @pagelist: pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: RADEON_GART_PAGE_* flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
		     uint32_t flags)
{
	unsigned t;
	unsigned p;
	uint64_t page_base, page_entry;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);

	for (i = 0; i < pages; i++, p++) {
		rdev->gart.pages[p] = pagelist[i];
		page_base = dma_addr[i];
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
			page_entry = radeon_gart_get_page_entry(page_base, flags);
			rdev->gart.pages_entry[t] = page_entry;
			if (rdev->gart.ptr) {
				radeon_gart_set_page(rdev, t, page_entry);
			}
			page_base += RADEON_GPU_PAGE_SIZE;
		}
	}
	if (rdev->gart.ptr) {
		mb();
		radeon_gart_tlb_flush(rdev);
	}
	return 0;
}

/**
 * radeon_gart_init - init the driver info for managing the gart
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int radeon_gart_init(struct radeon_device *rdev)
{
	int r, i;

	if (rdev->gart.pages) {
		return 0;
	}
	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = radeon_dummy_page_init(rdev);
	if (r)
		return r;
	/* Compute table size */
	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	/* Allocate pages table */
	rdev->gart.pages = vzalloc(sizeof(void *) * rdev->gart.num_cpu_pages);
	if (rdev->gart.pages == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	rdev->gart.pages_entry = vmalloc(sizeof(uint64_t) *
					 rdev->gart.num_gpu_pages);
	if (rdev->gart.pages_entry == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	/* set GART entry to point to the dummy page by default */
	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
		rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
	return 0;
}

/**
 * radeon_gart_fini - tear down the driver info for managing the gart
 *
 * @rdev: radeon_device pointer
 *
 * Tear down the gart driver info and free the dummy page (all asics).
 */
void radeon_gart_fini(struct radeon_device *rdev)
{
	if (rdev->gart.ready) {
		/* unbind pages */
		radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	}
	rdev->gart.ready = false;
	vfree(rdev->gart.pages);
	vfree(rdev->gart.pages_entry);
	rdev->gart.pages = NULL;
	rdev->gart.pages_entry = NULL;

	radeon_dummy_page_fini(rdev);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
760285e7 DH	28	#include <drm/drmP.h>
760285e7 DH	29	#include <drm/radeon_drm.h>
771fe6b9	30	#include "radeon.h"
771fe6b9	31
03eec93b AD	32	/*
	33	* GART
	34	* The GART (Graphics Aperture Remapping Table) is an aperture
	35	* in the GPU's address space. System pages can be mapped into
	36	* the aperture and look like contiguous pages from the GPU's
	37	* perspective. A page table maps the pages in the aperture
	38	* to the actual backing pages in system memory.
	39	*
	40	* Radeon GPUs support both an internal GART, as described above,
	41	* and AGP. AGP works similarly, but the GART table is configured
	42	* and maintained by the northbridge rather than the driver.
	43	* Radeon hw has a separate AGP aperture that is programmed to
	44	* point to the AGP aperture provided by the northbridge and the
	45	* requests are passed through to the northbridge aperture.
	46	* Both AGP and internal GART can be used at the same time, however
	47	* that is not currently supported by the driver.
	48	*
	49	* This file handles the common internal GART management.
	50	*/
	51
771fe6b9 JG	52	/*
	53	* Common GART table functions.
	54	*/
03eec93b AD	55	/**
	56	* radeon_gart_table_ram_alloc - allocate system ram for gart page table
	57	*
	58	* @rdev: radeon_device pointer
	59	*
	60	* Allocate system memory for GART page table
	61	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	62	* gart table to be in system memory.
	63	* Returns 0 for success, -ENOMEM for failure.
	64	*/
771fe6b9 JG	65	int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
	66	{
	67	void *ptr;
	68
	69	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
	70	&rdev->gart.table_addr);
	71	if (ptr == NULL) {
	72	return -ENOMEM;
	73	}
	74	#ifdef CONFIG_X86
	75	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	76	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
	77	set_memory_uc((unsigned long)ptr,
	78	rdev->gart.table_size >> PAGE_SHIFT);
	79	}
	80	#endif
c9a1be96 JG	81	rdev->gart.ptr = ptr;
c9a1be96 JG	82	memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
771fe6b9 JG	83	return 0;
	84	}
	85
03eec93b AD	86	/**
	87	* radeon_gart_table_ram_free - free system ram for gart page table
	88	*
	89	* @rdev: radeon_device pointer
	90	*
	91	* Free system memory for GART page table
	92	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	93	* gart table to be in system memory.
	94	*/
771fe6b9 JG	95	void radeon_gart_table_ram_free(struct radeon_device *rdev)
771fe6b9 JG	96	{
c9a1be96	97	if (rdev->gart.ptr == NULL) {
771fe6b9 JG	98	return;
	99	}
	100	#ifdef CONFIG_X86
	101	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	102	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
c9a1be96	103	set_memory_wb((unsigned long)rdev->gart.ptr,
771fe6b9 JG	104	rdev->gart.table_size >> PAGE_SHIFT);
	105	}
	106	#endif
	107	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
c9a1be96	108	(void *)rdev->gart.ptr,
771fe6b9	109	rdev->gart.table_addr);
c9a1be96	110	rdev->gart.ptr = NULL;
771fe6b9 JG	111	rdev->gart.table_addr = 0;
	112	}
	113
03eec93b AD	114	/**
	115	* radeon_gart_table_vram_alloc - allocate vram for gart page table
	116	*
	117	* @rdev: radeon_device pointer
	118	*
	119	* Allocate video memory for GART page table
	120	* (pcie r4xx, r5xx+). These asics require the
	121	* gart table to be in video memory.
	122	* Returns 0 for success, error for failure.
	123	*/
771fe6b9 JG	124	int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
771fe6b9 JG	125	{
771fe6b9 JG	126	int r;
771fe6b9 JG	127
c9a1be96	128	if (rdev->gart.robj == NULL) {
441921d5	129	r = radeon_bo_create(rdev, rdev->gart.table_size,
268b2510	130	PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
831b6966	131	0, NULL, NULL, &rdev->gart.robj);
771fe6b9 JG	132	if (r) {
	133	return r;
	134	}
	135	}
4aac0473 JG	136	return 0;
	137	}
	138
03eec93b AD	139	/**
	140	* radeon_gart_table_vram_pin - pin gart page table in vram
	141	*
	142	* @rdev: radeon_device pointer
	143	*
	144	* Pin the GART page table in vram so it will not be moved
	145	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	146	* gart table to be in video memory.
	147	* Returns 0 for success, error for failure.
	148	*/
4aac0473 JG	149	int radeon_gart_table_vram_pin(struct radeon_device *rdev)
	150	{
	151	uint64_t gpu_addr;
	152	int r;
	153
c9a1be96	154	r = radeon_bo_reserve(rdev->gart.robj, false);
4c788679	155	if (unlikely(r != 0))
771fe6b9	156	return r;
c9a1be96	157	r = radeon_bo_pin(rdev->gart.robj,
4c788679	158	RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
771fe6b9	159	if (r) {
c9a1be96	160	radeon_bo_unreserve(rdev->gart.robj);
771fe6b9 JG	161	return r;
771fe6b9 JG	162	}
c9a1be96	163	r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
4c788679	164	if (r)
c9a1be96 JG	165	radeon_bo_unpin(rdev->gart.robj);
c9a1be96 JG	166	radeon_bo_unreserve(rdev->gart.robj);
771fe6b9	167	rdev->gart.table_addr = gpu_addr;
5636d2f8 MD	168
	169	if (!r) {
	170	int i;
	171
	172	/* We might have dropped some GART table updates while it wasn't
	173	* mapped, restore all entries
	174	*/
	175	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
	176	radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
	177	mb();
	178	radeon_gart_tlb_flush(rdev);
	179	}
	180
4c788679	181	return r;
771fe6b9 JG	182	}
771fe6b9 JG	183
03eec93b AD	184	/**
	185	* radeon_gart_table_vram_unpin - unpin gart page table in vram
	186	*
	187	* @rdev: radeon_device pointer
	188	*
	189	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	190	* These asics require the gart table to be in video memory.
	191	*/
c9a1be96	192	void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
771fe6b9	193	{
4c788679 JG	194	int r;
4c788679 JG	195
c9a1be96	196	if (rdev->gart.robj == NULL) {
771fe6b9 JG	197	return;
771fe6b9 JG	198	}
c9a1be96	199	r = radeon_bo_reserve(rdev->gart.robj, false);
4c788679	200	if (likely(r == 0)) {
c9a1be96 JG	201	radeon_bo_kunmap(rdev->gart.robj);
	202	radeon_bo_unpin(rdev->gart.robj);
	203	radeon_bo_unreserve(rdev->gart.robj);
	204	rdev->gart.ptr = NULL;
	205	}
	206	}
	207
03eec93b AD	208	/**
	209	* radeon_gart_table_vram_free - free gart page table vram
	210	*
	211	* @rdev: radeon_device pointer
	212	*
	213	* Free the video memory used for the GART page table
	214	* (pcie r4xx, r5xx+). These asics require the gart table to
	215	* be in video memory.
	216	*/
c9a1be96 JG	217	void radeon_gart_table_vram_free(struct radeon_device *rdev)
	218	{
	219	if (rdev->gart.robj == NULL) {
	220	return;
4c788679	221	}
c9a1be96	222	radeon_bo_unref(&rdev->gart.robj);
771fe6b9 JG	223	}
771fe6b9 JG	224
771fe6b9 JG	225	/*
	226	* Common gart functions.
	227	*/
03eec93b AD	228	/**
	229	* radeon_gart_unbind - unbind pages from the gart page table
	230	*
	231	* @rdev: radeon_device pointer
	232	* @offset: offset into the GPU's gart aperture
	233	* @pages: number of pages to unbind
	234	*
	235	* Unbinds the requested pages from the gart page table and
	236	* replaces them with the dummy page (all asics).
	237	*/
771fe6b9 JG	238	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
	239	int pages)
	240	{
	241	unsigned t;
	242	unsigned p;
	243	int i, j;
	244
	245	if (!rdev->gart.ready) {
fcf4de5a	246	WARN(1, "trying to unbind memory from uninitialized GART !\n");
771fe6b9 JG	247	return;
771fe6b9 JG	248	}
a77f1718 MT	249	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	250	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	251	for (i = 0; i < pages; i++, p++) {
771fe6b9 JG	252	if (rdev->gart.pages[p]) {
771fe6b9	253	rdev->gart.pages[p] = NULL;
a77f1718	254	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
cb658906	255	rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
c9a1be96	256	if (rdev->gart.ptr) {
cb658906 MD	257	radeon_gart_set_page(rdev, t,
cb658906 MD	258	rdev->dummy_page.entry);
c9a1be96	259	}
771fe6b9 JG	260	}
	261	}
	262	}
233709d2 MD	263	if (rdev->gart.ptr) {
	264	mb();
	265	radeon_gart_tlb_flush(rdev);
	266	}
771fe6b9 JG	267	}
771fe6b9 JG	268
03eec93b AD	269	/**
	270	* radeon_gart_bind - bind pages into the gart page table
	271	*
	272	* @rdev: radeon_device pointer
	273	* @offset: offset into the GPU's gart aperture
	274	* @pages: number of pages to bind
	275	* @pagelist: pages to bind
	276	* @dma_addr: DMA addresses of pages
77497f27	277	* @flags: RADEON_GART_PAGE_* flags
03eec93b AD	278	*
	279	* Binds the requested pages to the gart page table
	280	* (all asics).
	281	* Returns 0 for success, -EINVAL for failure.
	282	*/
771fe6b9	283	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
77497f27 MD	284	int pages, struct page *pagelist, dma_addr_t dma_addr,
77497f27 MD	285	uint32_t flags)
771fe6b9 JG	286	{
	287	unsigned t;
	288	unsigned p;
cb658906	289	uint64_t page_base, page_entry;
771fe6b9 JG	290	int i, j;
	291
	292	if (!rdev->gart.ready) {
fcf4de5a	293	WARN(1, "trying to bind memory to uninitialized GART !\n");
771fe6b9 JG	294	return -EINVAL;
771fe6b9 JG	295	}
a77f1718 MT	296	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	297	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	298
771fe6b9 JG	299	for (i = 0; i < pages; i++, p++) {
771fe6b9	300	rdev->gart.pages[p] = pagelist[i];
cb658906 MD	301	page_base = dma_addr[i];
	302	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
	303	page_entry = radeon_gart_get_page_entry(page_base, flags);
	304	rdev->gart.pages_entry[t] = page_entry;
	305	if (rdev->gart.ptr) {
	306	radeon_gart_set_page(rdev, t, page_entry);
c9a1be96	307	}
cb658906	308	page_base += RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	309	}
771fe6b9 JG	310	}
233709d2 MD	311	if (rdev->gart.ptr) {
	312	mb();
	313	radeon_gart_tlb_flush(rdev);
	314	}
771fe6b9 JG	315	return 0;
	316	}
	317
03eec93b AD	318	/**
	319	* radeon_gart_init - init the driver info for managing the gart
	320	*
	321	* @rdev: radeon_device pointer
	322	*
	323	* Allocate the dummy page and init the gart driver info (all asics).
	324	* Returns 0 for success, error for failure.
	325	*/
771fe6b9 JG	326	int radeon_gart_init(struct radeon_device *rdev)
771fe6b9 JG	327	{
82568565 DA	328	int r, i;
82568565 DA	329
771fe6b9 JG	330	if (rdev->gart.pages) {
	331	return 0;
	332	}
a77f1718 MT	333	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
a77f1718 MT	334	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
771fe6b9 JG	335	DRM_ERROR("Page size is smaller than GPU page size!\n");
	336	return -EINVAL;
	337	}
82568565 DA	338	r = radeon_dummy_page_init(rdev);
	339	if (r)
	340	return r;
771fe6b9 JG	341	/* Compute table size */
771fe6b9 JG	342	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
a77f1718	343	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	344	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
	345	rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	346	/* Allocate pages table */
59240ee3	347	rdev->gart.pages = vzalloc(sizeof(void ) rdev->gart.num_cpu_pages);
771fe6b9 JG	348	if (rdev->gart.pages == NULL) {
	349	radeon_gart_fini(rdev);
	350	return -ENOMEM;
	351	}
cb658906 MD	352	rdev->gart.pages_entry = vmalloc(sizeof(uint64_t) *
	353	rdev->gart.num_gpu_pages);
	354	if (rdev->gart.pages_entry == NULL) {
	355	radeon_gart_fini(rdev);
	356	return -ENOMEM;
	357	}
82568565	358	/* set GART entry to point to the dummy page by default */
cb658906 MD	359	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
cb658906 MD	360	rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
771fe6b9 JG	361	return 0;
	362	}
	363
03eec93b AD	364	/**
	365	* radeon_gart_fini - tear down the driver info for managing the gart
	366	*
	367	* @rdev: radeon_device pointer
	368	*
	369	* Tear down the gart driver info and free the dummy page (all asics).
	370	*/
771fe6b9 JG	371	void radeon_gart_fini(struct radeon_device *rdev)
771fe6b9 JG	372	{
cb658906	373	if (rdev->gart.ready) {
771fe6b9 JG	374	/* unbind pages */
	375	radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	376	}
	377	rdev->gart.ready = false;
59240ee3	378	vfree(rdev->gart.pages);
cb658906	379	vfree(rdev->gart.pages_entry);
771fe6b9	380	rdev->gart.pages = NULL;
cb658906	381	rdev->gart.pages_entry = NULL;
92656d70 AD	382
92656d70 AD	383	radeon_dummy_page_fini(rdev);
771fe6b9	384	}