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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "radeon_drm.h" | |
30 | #include "radeon.h" | |
31 | #include "radeon_reg.h" | |
32 | ||
33 | /* | |
34 | * Common GART table functions. | |
35 | */ | |
36 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev) | |
37 | { | |
38 | void *ptr; | |
39 | ||
40 | ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, | |
41 | &rdev->gart.table_addr); | |
42 | if (ptr == NULL) { | |
43 | return -ENOMEM; | |
44 | } | |
45 | #ifdef CONFIG_X86 | |
46 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || | |
47 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
48 | set_memory_uc((unsigned long)ptr, | |
49 | rdev->gart.table_size >> PAGE_SHIFT); | |
50 | } | |
51 | #endif | |
52 | rdev->gart.table.ram.ptr = ptr; | |
53 | memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size); | |
54 | return 0; | |
55 | } | |
56 | ||
57 | void radeon_gart_table_ram_free(struct radeon_device *rdev) | |
58 | { | |
59 | if (rdev->gart.table.ram.ptr == NULL) { | |
60 | return; | |
61 | } | |
62 | #ifdef CONFIG_X86 | |
63 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || | |
64 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
65 | set_memory_wb((unsigned long)rdev->gart.table.ram.ptr, | |
66 | rdev->gart.table_size >> PAGE_SHIFT); | |
67 | } | |
68 | #endif | |
69 | pci_free_consistent(rdev->pdev, rdev->gart.table_size, | |
70 | (void *)rdev->gart.table.ram.ptr, | |
71 | rdev->gart.table_addr); | |
72 | rdev->gart.table.ram.ptr = NULL; | |
73 | rdev->gart.table_addr = 0; | |
74 | } | |
75 | ||
76 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev) | |
77 | { | |
771fe6b9 JG |
78 | int r; |
79 | ||
80 | if (rdev->gart.table.vram.robj == NULL) { | |
4c788679 JG |
81 | r = radeon_bo_create(rdev, NULL, rdev->gart.table_size, |
82 | true, RADEON_GEM_DOMAIN_VRAM, | |
83 | &rdev->gart.table.vram.robj); | |
771fe6b9 JG |
84 | if (r) { |
85 | return r; | |
86 | } | |
87 | } | |
4aac0473 JG |
88 | return 0; |
89 | } | |
90 | ||
91 | int radeon_gart_table_vram_pin(struct radeon_device *rdev) | |
92 | { | |
93 | uint64_t gpu_addr; | |
94 | int r; | |
95 | ||
4c788679 JG |
96 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
97 | if (unlikely(r != 0)) | |
771fe6b9 | 98 | return r; |
4c788679 JG |
99 | r = radeon_bo_pin(rdev->gart.table.vram.robj, |
100 | RADEON_GEM_DOMAIN_VRAM, &gpu_addr); | |
771fe6b9 | 101 | if (r) { |
4c788679 | 102 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
771fe6b9 JG |
103 | return r; |
104 | } | |
4c788679 JG |
105 | r = radeon_bo_kmap(rdev->gart.table.vram.robj, |
106 | (void **)&rdev->gart.table.vram.ptr); | |
107 | if (r) | |
108 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
109 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
771fe6b9 | 110 | rdev->gart.table_addr = gpu_addr; |
4c788679 | 111 | return r; |
771fe6b9 JG |
112 | } |
113 | ||
114 | void radeon_gart_table_vram_free(struct radeon_device *rdev) | |
115 | { | |
4c788679 JG |
116 | int r; |
117 | ||
771fe6b9 JG |
118 | if (rdev->gart.table.vram.robj == NULL) { |
119 | return; | |
120 | } | |
4c788679 JG |
121 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
122 | if (likely(r == 0)) { | |
123 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
124 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
125 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
126 | } | |
127 | radeon_bo_unref(&rdev->gart.table.vram.robj); | |
771fe6b9 JG |
128 | } |
129 | ||
130 | ||
131 | ||
132 | ||
133 | /* | |
134 | * Common gart functions. | |
135 | */ | |
136 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
137 | int pages) | |
138 | { | |
139 | unsigned t; | |
140 | unsigned p; | |
141 | int i, j; | |
142 | ||
143 | if (!rdev->gart.ready) { | |
144 | WARN(1, "trying to unbind memory to unitialized GART !\n"); | |
145 | return; | |
146 | } | |
a77f1718 MT |
147 | t = offset / RADEON_GPU_PAGE_SIZE; |
148 | p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); | |
771fe6b9 JG |
149 | for (i = 0; i < pages; i++, p++) { |
150 | if (rdev->gart.pages[p]) { | |
151 | pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], | |
152 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
153 | rdev->gart.pages[p] = NULL; | |
154 | rdev->gart.pages_addr[p] = 0; | |
a77f1718 | 155 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
771fe6b9 JG |
156 | radeon_gart_set_page(rdev, t, 0); |
157 | } | |
158 | } | |
159 | } | |
160 | mb(); | |
161 | radeon_gart_tlb_flush(rdev); | |
162 | } | |
163 | ||
164 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
165 | int pages, struct page **pagelist) | |
166 | { | |
167 | unsigned t; | |
168 | unsigned p; | |
169 | uint64_t page_base; | |
170 | int i, j; | |
171 | ||
172 | if (!rdev->gart.ready) { | |
173 | DRM_ERROR("trying to bind memory to unitialized GART !\n"); | |
174 | return -EINVAL; | |
175 | } | |
a77f1718 MT |
176 | t = offset / RADEON_GPU_PAGE_SIZE; |
177 | p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); | |
771fe6b9 JG |
178 | |
179 | for (i = 0; i < pages; i++, p++) { | |
180 | /* we need to support large memory configurations */ | |
181 | /* assume that unbind have already been call on the range */ | |
182 | rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i], | |
183 | 0, PAGE_SIZE, | |
184 | PCI_DMA_BIDIRECTIONAL); | |
185 | if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) { | |
186 | /* FIXME: failed to map page (return -ENOMEM?) */ | |
187 | radeon_gart_unbind(rdev, offset, pages); | |
188 | return -ENOMEM; | |
189 | } | |
190 | rdev->gart.pages[p] = pagelist[i]; | |
ed10f95d | 191 | page_base = rdev->gart.pages_addr[p]; |
a77f1718 | 192 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
771fe6b9 | 193 | radeon_gart_set_page(rdev, t, page_base); |
a77f1718 | 194 | page_base += RADEON_GPU_PAGE_SIZE; |
771fe6b9 JG |
195 | } |
196 | } | |
197 | mb(); | |
198 | radeon_gart_tlb_flush(rdev); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | int radeon_gart_init(struct radeon_device *rdev) | |
203 | { | |
204 | if (rdev->gart.pages) { | |
205 | return 0; | |
206 | } | |
a77f1718 MT |
207 | /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ |
208 | if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { | |
771fe6b9 JG |
209 | DRM_ERROR("Page size is smaller than GPU page size!\n"); |
210 | return -EINVAL; | |
211 | } | |
212 | /* Compute table size */ | |
213 | rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; | |
a77f1718 | 214 | rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; |
771fe6b9 JG |
215 | DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", |
216 | rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); | |
217 | /* Allocate pages table */ | |
218 | rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages, | |
219 | GFP_KERNEL); | |
220 | if (rdev->gart.pages == NULL) { | |
221 | radeon_gart_fini(rdev); | |
222 | return -ENOMEM; | |
223 | } | |
224 | rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) * | |
225 | rdev->gart.num_cpu_pages, GFP_KERNEL); | |
226 | if (rdev->gart.pages_addr == NULL) { | |
227 | radeon_gart_fini(rdev); | |
228 | return -ENOMEM; | |
229 | } | |
230 | return 0; | |
231 | } | |
232 | ||
233 | void radeon_gart_fini(struct radeon_device *rdev) | |
234 | { | |
235 | if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { | |
236 | /* unbind pages */ | |
237 | radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); | |
238 | } | |
239 | rdev->gart.ready = false; | |
240 | kfree(rdev->gart.pages); | |
241 | kfree(rdev->gart.pages_addr); | |
242 | rdev->gart.pages = NULL; | |
243 | rdev->gart.pages_addr = NULL; | |
244 | } |