[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_gem.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"

void radeon_gem_object_free(struct drm_gem_object *gobj)
{
	struct radeon_bo *robj = gem_to_radeon_bo(gobj);

	if (robj) {
		if (robj->gem_base.import_attach)
			drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
		radeon_bo_unref(&robj);
	}
}

int radeon_gem_object_create(struct radeon_device *rdev, int size,
				int alignment, int initial_domain,
				bool discardable, bool kernel,
				struct drm_gem_object **obj)
{
	struct radeon_bo *robj;
	unsigned long max_size;
	int r;

	*obj = NULL;
	/* At least align on page size */
	if (alignment < PAGE_SIZE) {
		alignment = PAGE_SIZE;
	}

	/* maximun bo size is the minimun btw visible vram and gtt size */
	max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
	if (size > max_size) {
		printk(KERN_WARNING "%s:%d alloc size %dMb bigger than %ldMb limit\n",
		       __func__, __LINE__, size >> 20, max_size >> 20);
		return -ENOMEM;
	}

retry:
	r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, NULL, &robj);
	if (r) {
		if (r != -ERESTARTSYS) {
			if (initial_domain == RADEON_GEM_DOMAIN_VRAM) {
				initial_domain |= RADEON_GEM_DOMAIN_GTT;
				goto retry;
			}
			DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n",
				  size, initial_domain, alignment, r);
		}
		return r;
	}
	*obj = &robj->gem_base;
	robj->pid = task_pid_nr(current);

	mutex_lock(&rdev->gem.mutex);
	list_add_tail(&robj->list, &rdev->gem.objects);
	mutex_unlock(&rdev->gem.mutex);

	return 0;
}

static int radeon_gem_set_domain(struct drm_gem_object *gobj,
			  uint32_t rdomain, uint32_t wdomain)
{
	struct radeon_bo *robj;
	uint32_t domain;
	int r;

	/* FIXME: reeimplement */
	robj = gem_to_radeon_bo(gobj);
	/* work out where to validate the buffer to */
	domain = wdomain;
	if (!domain) {
		domain = rdomain;
	}
	if (!domain) {
		/* Do nothings */
		printk(KERN_WARNING "Set domain without domain !\n");
		return 0;
	}
	if (domain == RADEON_GEM_DOMAIN_CPU) {
		/* Asking for cpu access wait for object idle */
		r = radeon_bo_wait(robj, NULL, false);
		if (r) {
			printk(KERN_ERR "Failed to wait for object !\n");
			return r;
		}
	}
	return 0;
}

int radeon_gem_init(struct radeon_device *rdev)
{
	INIT_LIST_HEAD(&rdev->gem.objects);
	return 0;
}

void radeon_gem_fini(struct radeon_device *rdev)
{
	radeon_bo_force_delete(rdev);
}

/*
 * Call from drm_gem_handle_create which appear in both new and open ioctl
 * case.
 */
int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
{
	struct radeon_bo *rbo = gem_to_radeon_bo(obj);
	struct radeon_device *rdev = rbo->rdev;
	struct radeon_fpriv *fpriv = file_priv->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	struct radeon_bo_va *bo_va;
	int r;

	if (rdev->family < CHIP_CAYMAN) {
		return 0;
	}

	r = radeon_bo_reserve(rbo, false);
	if (r) {
		return r;
	}

	bo_va = radeon_vm_bo_find(vm, rbo);
	if (!bo_va) {
		bo_va = radeon_vm_bo_add(rdev, vm, rbo);
	} else {
		++bo_va->ref_count;
	}
	radeon_bo_unreserve(rbo);

	return 0;
}

void radeon_gem_object_close(struct drm_gem_object *obj,
			     struct drm_file *file_priv)
{
	struct radeon_bo *rbo = gem_to_radeon_bo(obj);
	struct radeon_device *rdev = rbo->rdev;
	struct radeon_fpriv *fpriv = file_priv->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	struct radeon_bo_va *bo_va;
	int r;

	if (rdev->family < CHIP_CAYMAN) {
		return;
	}

	r = radeon_bo_reserve(rbo, true);
	if (r) {
		dev_err(rdev->dev, "leaking bo va because "
			"we fail to reserve bo (%d)\n", r);
		return;
	}
	bo_va = radeon_vm_bo_find(vm, rbo);
	if (bo_va) {
		if (--bo_va->ref_count == 0) {
			radeon_vm_bo_rmv(rdev, bo_va);
		}
	}
	radeon_bo_unreserve(rbo);
}

static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r)
{
	if (r == -EDEADLK) {
		r = radeon_gpu_reset(rdev);
		if (!r)
			r = -EAGAIN;
	}
	return r;
}

/*
 * GEM ioctls.
 */
int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_gem_info *args = data;
	struct ttm_mem_type_manager *man;
	unsigned i;

	man = &rdev->mman.bdev.man[TTM_PL_VRAM];

	args->vram_size = rdev->mc.real_vram_size;
	args->vram_visible = (u64)man->size << PAGE_SHIFT;
	if (rdev->stollen_vga_memory)
		args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory);
	args->vram_visible -= radeon_fbdev_total_size(rdev);
	args->gart_size = rdev->mc.gtt_size - 4096 - RADEON_IB_POOL_SIZE*64*1024;
	for(i = 0; i < RADEON_NUM_RINGS; ++i)
		args->gart_size -= rdev->ring[i].ring_size;
	return 0;
}

int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *filp)
{
	/* TODO: implement */
	DRM_ERROR("unimplemented %s\n", __func__);
	return -ENOSYS;
}

int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *filp)
{
	/* TODO: implement */
	DRM_ERROR("unimplemented %s\n", __func__);
	return -ENOSYS;
}

int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_gem_create *args = data;
	struct drm_gem_object *gobj;
	uint32_t handle;
	int r;

	down_read(&rdev->exclusive_lock);
	/* create a gem object to contain this object in */
	args->size = roundup(args->size, PAGE_SIZE);
	r = radeon_gem_object_create(rdev, args->size, args->alignment,
					args->initial_domain, false,
					false, &gobj);
	if (r) {
		up_read(&rdev->exclusive_lock);
		r = radeon_gem_handle_lockup(rdev, r);
		return r;
	}
	r = drm_gem_handle_create(filp, gobj, &handle);
	/* drop reference from allocate - handle holds it now */
	drm_gem_object_unreference_unlocked(gobj);
	if (r) {
		up_read(&rdev->exclusive_lock);
		r = radeon_gem_handle_lockup(rdev, r);
		return r;
	}
	args->handle = handle;
	up_read(&rdev->exclusive_lock);
	return 0;
}

int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp)
{
	/* transition the BO to a domain -
	 * just validate the BO into a certain domain */
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_gem_set_domain *args = data;
	struct drm_gem_object *gobj;
	struct radeon_bo *robj;
	int r;

	/* for now if someone requests domain CPU -
	 * just make sure the buffer is finished with */
	down_read(&rdev->exclusive_lock);

	/* just do a BO wait for now */
	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL) {
		up_read(&rdev->exclusive_lock);
		return -ENOENT;
	}
	robj = gem_to_radeon_bo(gobj);

	r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);

	drm_gem_object_unreference_unlocked(gobj);
	up_read(&rdev->exclusive_lock);
	r = radeon_gem_handle_lockup(robj->rdev, r);
	return r;
}

int radeon_mode_dumb_mmap(struct drm_file *filp,
			  struct drm_device *dev,
			  uint32_t handle, uint64_t *offset_p)
{
	struct drm_gem_object *gobj;
	struct radeon_bo *robj;

	gobj = drm_gem_object_lookup(dev, filp, handle);
	if (gobj == NULL) {
		return -ENOENT;
	}
	robj = gem_to_radeon_bo(gobj);
	*offset_p = radeon_bo_mmap_offset(robj);
	drm_gem_object_unreference_unlocked(gobj);
	return 0;
}

int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp)
{
	struct drm_radeon_gem_mmap *args = data;

	return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
}

int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_gem_busy *args = data;
	struct drm_gem_object *gobj;
	struct radeon_bo *robj;
	int r;
	uint32_t cur_placement = 0;

	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL) {
		return -ENOENT;
	}
	robj = gem_to_radeon_bo(gobj);
	r = radeon_bo_wait(robj, &cur_placement, true);
	switch (cur_placement) {
	case TTM_PL_VRAM:
		args->domain = RADEON_GEM_DOMAIN_VRAM;
		break;
	case TTM_PL_TT:
		args->domain = RADEON_GEM_DOMAIN_GTT;
		break;
	case TTM_PL_SYSTEM:
		args->domain = RADEON_GEM_DOMAIN_CPU;
	default:
		break;
	}
	drm_gem_object_unreference_unlocked(gobj);
	r = radeon_gem_handle_lockup(rdev, r);
	return r;
}

int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_radeon_gem_wait_idle *args = data;
	struct drm_gem_object *gobj;
	struct radeon_bo *robj;
	int r;

	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL) {
		return -ENOENT;
	}
	robj = gem_to_radeon_bo(gobj);
	r = radeon_bo_wait(robj, NULL, false);
	/* callback hw specific functions if any */
	if (rdev->asic->ioctl_wait_idle)
		robj->rdev->asic->ioctl_wait_idle(rdev, robj);
	drm_gem_object_unreference_unlocked(gobj);
	r = radeon_gem_handle_lockup(rdev, r);
	return r;
}

int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp)
{
	struct drm_radeon_gem_set_tiling *args = data;
	struct drm_gem_object *gobj;
	struct radeon_bo *robj;
	int r = 0;

	DRM_DEBUG("%d \n", args->handle);
	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL)
		return -ENOENT;
	robj = gem_to_radeon_bo(gobj);
	r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
	drm_gem_object_unreference_unlocked(gobj);
	return r;
}

int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp)
{
	struct drm_radeon_gem_get_tiling *args = data;
	struct drm_gem_object *gobj;
	struct radeon_bo *rbo;
	int r = 0;

	DRM_DEBUG("\n");
	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL)
		return -ENOENT;
	rbo = gem_to_radeon_bo(gobj);
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		goto out;
	radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
	radeon_bo_unreserve(rbo);
out:
	drm_gem_object_unreference_unlocked(gobj);
	return r;
}

int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp)
{
	struct drm_radeon_gem_va *args = data;
	struct drm_gem_object *gobj;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_fpriv *fpriv = filp->driver_priv;
	struct radeon_bo *rbo;
	struct radeon_bo_va *bo_va;
	u32 invalid_flags;
	int r = 0;

	if (!rdev->vm_manager.enabled) {
		args->operation = RADEON_VA_RESULT_ERROR;
		return -ENOTTY;
	}

	/* !! DONT REMOVE !!
	 * We don't support vm_id yet, to be sure we don't have have broken
	 * userspace, reject anyone trying to use non 0 value thus moving
	 * forward we can use those fields without breaking existant userspace
	 */
	if (args->vm_id) {
		args->operation = RADEON_VA_RESULT_ERROR;
		return -EINVAL;
	}

	if (args->offset < RADEON_VA_RESERVED_SIZE) {
		dev_err(&dev->pdev->dev,
			"offset 0x%lX is in reserved area 0x%X\n",
			(unsigned long)args->offset,
			RADEON_VA_RESERVED_SIZE);
		args->operation = RADEON_VA_RESULT_ERROR;
		return -EINVAL;
	}

	/* don't remove, we need to enforce userspace to set the snooped flag
	 * otherwise we will endup with broken userspace and we won't be able
	 * to enable this feature without adding new interface
	 */
	invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM;
	if ((args->flags & invalid_flags)) {
		dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
			args->flags, invalid_flags);
		args->operation = RADEON_VA_RESULT_ERROR;
		return -EINVAL;
	}
	if (!(args->flags & RADEON_VM_PAGE_SNOOPED)) {
		dev_err(&dev->pdev->dev, "only supported snooped mapping for now\n");
		args->operation = RADEON_VA_RESULT_ERROR;
		return -EINVAL;
	}

	switch (args->operation) {
	case RADEON_VA_MAP:
	case RADEON_VA_UNMAP:
		break;
	default:
		dev_err(&dev->pdev->dev, "unsupported operation %d\n",
			args->operation);
		args->operation = RADEON_VA_RESULT_ERROR;
		return -EINVAL;
	}

	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	if (gobj == NULL) {
		args->operation = RADEON_VA_RESULT_ERROR;
		return -ENOENT;
	}
	rbo = gem_to_radeon_bo(gobj);
	r = radeon_bo_reserve(rbo, false);
	if (r) {
		args->operation = RADEON_VA_RESULT_ERROR;
		drm_gem_object_unreference_unlocked(gobj);
		return r;
	}
	bo_va = radeon_vm_bo_find(&fpriv->vm, rbo);
	if (!bo_va) {
		args->operation = RADEON_VA_RESULT_ERROR;
		drm_gem_object_unreference_unlocked(gobj);
		return -ENOENT;
	}

	switch (args->operation) {
	case RADEON_VA_MAP:
		if (bo_va->soffset) {
			args->operation = RADEON_VA_RESULT_VA_EXIST;
			args->offset = bo_va->soffset;
			goto out;
		}
		r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags);
		break;
	case RADEON_VA_UNMAP:
		r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0);
		break;
	default:
		break;
	}
	args->operation = RADEON_VA_RESULT_OK;
	if (r) {
		args->operation = RADEON_VA_RESULT_ERROR;
	}
out:
	radeon_bo_unreserve(rbo);
	drm_gem_object_unreference_unlocked(gobj);
	return r;
}

int radeon_mode_dumb_create(struct drm_file *file_priv,
			    struct drm_device *dev,
			    struct drm_mode_create_dumb *args)
{
	struct radeon_device *rdev = dev->dev_private;
	struct drm_gem_object *gobj;
	uint32_t handle;
	int r;

	args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
	args->size = args->pitch * args->height;
	args->size = ALIGN(args->size, PAGE_SIZE);

	r = radeon_gem_object_create(rdev, args->size, 0,
				     RADEON_GEM_DOMAIN_VRAM,
				     false, ttm_bo_type_device,
				     &gobj);
	if (r)
		return -ENOMEM;

	r = drm_gem_handle_create(file_priv, gobj, &handle);
	/* drop reference from allocate - handle holds it now */
	drm_gem_object_unreference_unlocked(gobj);
	if (r) {
		return r;
	}
	args->handle = handle;
	return 0;
}

#if defined(CONFIG_DEBUG_FS)
static int radeon_debugfs_gem_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_bo *rbo;
	unsigned i = 0;

	mutex_lock(&rdev->gem.mutex);
	list_for_each_entry(rbo, &rdev->gem.objects, list) {
		unsigned domain;
		const char *placement;

		domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type);
		switch (domain) {
		case RADEON_GEM_DOMAIN_VRAM:
			placement = "VRAM";
			break;
		case RADEON_GEM_DOMAIN_GTT:
			placement = " GTT";
			break;
		case RADEON_GEM_DOMAIN_CPU:
		default:
			placement = " CPU";
			break;
		}
		seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
			   i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20,
			   placement, (unsigned long)rbo->pid);
		i++;
	}
	mutex_unlock(&rdev->gem.mutex);
	return 0;
}

static struct drm_info_list radeon_debugfs_gem_list[] = {
	{"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL},
};
#endif

int radeon_gem_debugfs_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1);
#endif
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
760285e7 DH	28	#include <drm/drmP.h>
760285e7 DH	29	#include <drm/radeon_drm.h>
771fe6b9 JG	30	#include "radeon.h"
771fe6b9 JG	31
771fe6b9 JG	32	void radeon_gem_object_free(struct drm_gem_object *gobj)
771fe6b9 JG	33	{
7e4d15d9	34	struct radeon_bo *robj = gem_to_radeon_bo(gobj);
771fe6b9	35
771fe6b9	36	if (robj) {
40f5cf99 AD	37	if (robj->gem_base.import_attach)
40f5cf99 AD	38	drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
4c788679	39	radeon_bo_unref(&robj);
771fe6b9 JG	40	}
	41	}
	42
	43	int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679 JG	44	int alignment, int initial_domain,
	45	bool discardable, bool kernel,
	46	struct drm_gem_object **obj)
771fe6b9	47	{
4c788679	48	struct radeon_bo *robj;
6c0d112f	49	unsigned long max_size;
771fe6b9 JG	50	int r;
	51
	52	*obj = NULL;
771fe6b9 JG	53	/* At least align on page size */
	54	if (alignment < PAGE_SIZE) {
	55	alignment = PAGE_SIZE;
	56	}
6c0d112f CK	57
	58	/* maximun bo size is the minimun btw visible vram and gtt size */
	59	max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
	60	if (size > max_size) {
	61	printk(KERN_WARNING "%s:%d alloc size %dMb bigger than %ldMb limit\n",
	62	__func__, __LINE__, size >> 20, max_size >> 20);
	63	return -ENOMEM;
	64	}
	65
0fe7158c	66	retry:
40f5cf99	67	r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, NULL, &robj);
771fe6b9	68	if (r) {
0fe7158c CK	69	if (r != -ERESTARTSYS) {
	70	if (initial_domain == RADEON_GEM_DOMAIN_VRAM) {
	71	initial_domain \|= RADEON_GEM_DOMAIN_GTT;
	72	goto retry;
	73	}
ecabd32a DA	74	DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n",
ecabd32a DA	75	size, initial_domain, alignment, r);
0fe7158c	76	}
771fe6b9 JG	77	return r;
771fe6b9 JG	78	}
441921d5	79	*obj = &robj->gem_base;
409851f4	80	robj->pid = task_pid_nr(current);
441921d5 DV	81
	82	mutex_lock(&rdev->gem.mutex);
	83	list_add_tail(&robj->list, &rdev->gem.objects);
	84	mutex_unlock(&rdev->gem.mutex);
	85
771fe6b9 JG	86	return 0;
	87	}
	88
248a6c4a	89	static int radeon_gem_set_domain(struct drm_gem_object *gobj,
771fe6b9 JG	90	uint32_t rdomain, uint32_t wdomain)
771fe6b9 JG	91	{
4c788679	92	struct radeon_bo *robj;
771fe6b9 JG	93	uint32_t domain;
	94	int r;
	95
	96	/* FIXME: reeimplement */
7e4d15d9	97	robj = gem_to_radeon_bo(gobj);
771fe6b9 JG	98	/* work out where to validate the buffer to */
	99	domain = wdomain;
	100	if (!domain) {
	101	domain = rdomain;
	102	}
	103	if (!domain) {
	104	/* Do nothings */
b6cafa27	105	printk(KERN_WARNING "Set domain without domain !\n");
771fe6b9 JG	106	return 0;
	107	}
	108	if (domain == RADEON_GEM_DOMAIN_CPU) {
	109	/* Asking for cpu access wait for object idle */
4c788679	110	r = radeon_bo_wait(robj, NULL, false);
771fe6b9 JG	111	if (r) {
	112	printk(KERN_ERR "Failed to wait for object !\n");
	113	return r;
	114	}
	115	}
	116	return 0;
	117	}
	118
	119	int radeon_gem_init(struct radeon_device *rdev)
	120	{
	121	INIT_LIST_HEAD(&rdev->gem.objects);
	122	return 0;
	123	}
	124
	125	void radeon_gem_fini(struct radeon_device *rdev)
	126	{
4c788679	127	radeon_bo_force_delete(rdev);
771fe6b9 JG	128	}
771fe6b9 JG	129
721604a1 JG	130	/*
	131	* Call from drm_gem_handle_create which appear in both new and open ioctl
	132	* case.
	133	*/
	134	int radeon_gem_object_open(struct drm_gem_object obj, struct drm_file file_priv)
	135	{
e971bd5e CK	136	struct radeon_bo *rbo = gem_to_radeon_bo(obj);
	137	struct radeon_device *rdev = rbo->rdev;
	138	struct radeon_fpriv *fpriv = file_priv->driver_priv;
	139	struct radeon_vm *vm = &fpriv->vm;
	140	struct radeon_bo_va *bo_va;
	141	int r;
	142
	143	if (rdev->family < CHIP_CAYMAN) {
	144	return 0;
	145	}
	146
	147	r = radeon_bo_reserve(rbo, false);
	148	if (r) {
	149	return r;
	150	}
	151
	152	bo_va = radeon_vm_bo_find(vm, rbo);
	153	if (!bo_va) {
	154	bo_va = radeon_vm_bo_add(rdev, vm, rbo);
	155	} else {
	156	++bo_va->ref_count;
	157	}
	158	radeon_bo_unreserve(rbo);
	159
721604a1 JG	160	return 0;
	161	}
	162
	163	void radeon_gem_object_close(struct drm_gem_object *obj,
	164	struct drm_file *file_priv)
	165	{
	166	struct radeon_bo *rbo = gem_to_radeon_bo(obj);
	167	struct radeon_device *rdev = rbo->rdev;
	168	struct radeon_fpriv *fpriv = file_priv->driver_priv;
	169	struct radeon_vm *vm = &fpriv->vm;
e971bd5e	170	struct radeon_bo_va *bo_va;
d59f7021	171	int r;
721604a1 JG	172
	173	if (rdev->family < CHIP_CAYMAN) {
	174	return;
	175	}
	176
d59f7021 CK	177	r = radeon_bo_reserve(rbo, true);
	178	if (r) {
	179	dev_err(rdev->dev, "leaking bo va because "
	180	"we fail to reserve bo (%d)\n", r);
721604a1 JG	181	return;
721604a1 JG	182	}
e971bd5e CK	183	bo_va = radeon_vm_bo_find(vm, rbo);
	184	if (bo_va) {
	185	if (--bo_va->ref_count == 0) {
	186	radeon_vm_bo_rmv(rdev, bo_va);
	187	}
	188	}
721604a1 JG	189	radeon_bo_unreserve(rbo);
	190	}
	191
6c6f4783 CK	192	static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r)
	193	{
	194	if (r == -EDEADLK) {
6c6f4783 CK	195	r = radeon_gpu_reset(rdev);
	196	if (!r)
	197	r = -EAGAIN;
6c6f4783 CK	198	}
	199	return r;
	200	}
771fe6b9 JG	201
	202	/*
	203	* GEM ioctls.
	204	*/
	205	int radeon_gem_info_ioctl(struct drm_device dev, void data,
	206	struct drm_file *filp)
	207	{
	208	struct radeon_device *rdev = dev->dev_private;
	209	struct drm_radeon_gem_info *args = data;
53595338	210	struct ttm_mem_type_manager *man;
bf852799	211	unsigned i;
53595338 DA	212
53595338 DA	213	man = &rdev->mman.bdev.man[TTM_PL_VRAM];
771fe6b9	214
7a50f01a	215	args->vram_size = rdev->mc.real_vram_size;
53595338	216	args->vram_visible = (u64)man->size << PAGE_SHIFT;
38e14921	217	if (rdev->stollen_vga_memory)
4c788679	218	args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory);
38651674	219	args->vram_visible -= radeon_fbdev_total_size(rdev);
7b1f2485	220	args->gart_size = rdev->mc.gtt_size - 4096 - RADEON_IB_POOL_SIZE641024;
bf852799	221	for(i = 0; i < RADEON_NUM_RINGS; ++i)
e32eb50d	222	args->gart_size -= rdev->ring[i].ring_size;
771fe6b9 JG	223	return 0;
	224	}
	225
	226	int radeon_gem_pread_ioctl(struct drm_device dev, void data,
	227	struct drm_file *filp)
	228	{
	229	/* TODO: implement */
	230	DRM_ERROR("unimplemented %s\n", __func__);
	231	return -ENOSYS;
	232	}
	233
	234	int radeon_gem_pwrite_ioctl(struct drm_device dev, void data,
	235	struct drm_file *filp)
	236	{
	237	/* TODO: implement */
	238	DRM_ERROR("unimplemented %s\n", __func__);
	239	return -ENOSYS;
	240	}
	241
	242	int radeon_gem_create_ioctl(struct drm_device dev, void data,
	243	struct drm_file *filp)
	244	{
	245	struct radeon_device *rdev = dev->dev_private;
	246	struct drm_radeon_gem_create *args = data;
	247	struct drm_gem_object *gobj;
	248	uint32_t handle;
	249	int r;
	250
dee53e7f	251	down_read(&rdev->exclusive_lock);
771fe6b9 JG	252	/* create a gem object to contain this object in */
	253	args->size = roundup(args->size, PAGE_SIZE);
	254	r = radeon_gem_object_create(rdev, args->size, args->alignment,
4c788679 JG	255	args->initial_domain, false,
4c788679 JG	256	false, &gobj);
771fe6b9	257	if (r) {
dee53e7f	258	up_read(&rdev->exclusive_lock);
6c6f4783	259	r = radeon_gem_handle_lockup(rdev, r);
771fe6b9 JG	260	return r;
	261	}
	262	r = drm_gem_handle_create(filp, gobj, &handle);
29d08b3e DA	263	/* drop reference from allocate - handle holds it now */
29d08b3e DA	264	drm_gem_object_unreference_unlocked(gobj);
771fe6b9	265	if (r) {
dee53e7f	266	up_read(&rdev->exclusive_lock);
6c6f4783	267	r = radeon_gem_handle_lockup(rdev, r);
771fe6b9 JG	268	return r;
771fe6b9 JG	269	}
771fe6b9	270	args->handle = handle;
dee53e7f	271	up_read(&rdev->exclusive_lock);
771fe6b9 JG	272	return 0;
	273	}
	274
	275	int radeon_gem_set_domain_ioctl(struct drm_device dev, void data,
	276	struct drm_file *filp)
	277	{
	278	/* transition the BO to a domain -
	279	* just validate the BO into a certain domain */
dee53e7f	280	struct radeon_device *rdev = dev->dev_private;
771fe6b9 JG	281	struct drm_radeon_gem_set_domain *args = data;
771fe6b9 JG	282	struct drm_gem_object *gobj;
4c788679	283	struct radeon_bo *robj;
771fe6b9 JG	284	int r;
	285
	286	/* for now if someone requests domain CPU -
	287	* just make sure the buffer is finished with */
dee53e7f	288	down_read(&rdev->exclusive_lock);
771fe6b9 JG	289
	290	/* just do a BO wait for now */
	291	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	292	if (gobj == NULL) {
dee53e7f	293	up_read(&rdev->exclusive_lock);
bf79cb91	294	return -ENOENT;
771fe6b9	295	}
7e4d15d9	296	robj = gem_to_radeon_bo(gobj);
771fe6b9 JG	297
	298	r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
	299
bc9025bd	300	drm_gem_object_unreference_unlocked(gobj);
dee53e7f	301	up_read(&rdev->exclusive_lock);
6c6f4783	302	r = radeon_gem_handle_lockup(robj->rdev, r);
771fe6b9 JG	303	return r;
	304	}
	305
ff72145b DA	306	int radeon_mode_dumb_mmap(struct drm_file *filp,
	307	struct drm_device *dev,
	308	uint32_t handle, uint64_t *offset_p)
771fe6b9	309	{
771fe6b9	310	struct drm_gem_object *gobj;
4c788679	311	struct radeon_bo *robj;
771fe6b9	312
ff72145b	313	gobj = drm_gem_object_lookup(dev, filp, handle);
771fe6b9	314	if (gobj == NULL) {
bf79cb91	315	return -ENOENT;
771fe6b9	316	}
7e4d15d9	317	robj = gem_to_radeon_bo(gobj);
ff72145b	318	*offset_p = radeon_bo_mmap_offset(robj);
bc9025bd	319	drm_gem_object_unreference_unlocked(gobj);
4c788679	320	return 0;
771fe6b9 JG	321	}
771fe6b9 JG	322
ff72145b DA	323	int radeon_gem_mmap_ioctl(struct drm_device dev, void data,
	324	struct drm_file *filp)
	325	{
	326	struct drm_radeon_gem_mmap *args = data;
	327
	328	return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
	329	}
	330
771fe6b9 JG	331	int radeon_gem_busy_ioctl(struct drm_device dev, void data,
	332	struct drm_file *filp)
	333	{
1ef5325b	334	struct radeon_device *rdev = dev->dev_private;
cefb87ef DA	335	struct drm_radeon_gem_busy *args = data;
cefb87ef DA	336	struct drm_gem_object *gobj;
4c788679	337	struct radeon_bo *robj;
cefb87ef	338	int r;
4361e52a	339	uint32_t cur_placement = 0;
cefb87ef DA	340
	341	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	342	if (gobj == NULL) {
bf79cb91	343	return -ENOENT;
cefb87ef	344	}
7e4d15d9	345	robj = gem_to_radeon_bo(gobj);
4c788679	346	r = radeon_bo_wait(robj, &cur_placement, true);
9f844e51 MD	347	switch (cur_placement) {
9f844e51 MD	348	case TTM_PL_VRAM:
cefb87ef	349	args->domain = RADEON_GEM_DOMAIN_VRAM;
9f844e51 MD	350	break;
9f844e51 MD	351	case TTM_PL_TT:
cefb87ef	352	args->domain = RADEON_GEM_DOMAIN_GTT;
9f844e51 MD	353	break;
9f844e51 MD	354	case TTM_PL_SYSTEM:
cefb87ef	355	args->domain = RADEON_GEM_DOMAIN_CPU;
9f844e51 MD	356	default:
	357	break;
	358	}
bc9025bd	359	drm_gem_object_unreference_unlocked(gobj);
1ef5325b	360	r = radeon_gem_handle_lockup(rdev, r);
e3b2415e	361	return r;
771fe6b9 JG	362	}
	363
	364	int radeon_gem_wait_idle_ioctl(struct drm_device dev, void data,
	365	struct drm_file *filp)
	366	{
1ef5325b	367	struct radeon_device *rdev = dev->dev_private;
771fe6b9 JG	368	struct drm_radeon_gem_wait_idle *args = data;
771fe6b9 JG	369	struct drm_gem_object *gobj;
4c788679	370	struct radeon_bo *robj;
771fe6b9 JG	371	int r;
	372
	373	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	374	if (gobj == NULL) {
bf79cb91	375	return -ENOENT;
771fe6b9	376	}
7e4d15d9	377	robj = gem_to_radeon_bo(gobj);
4c788679	378	r = radeon_bo_wait(robj, NULL, false);
062b389c	379	/* callback hw specific functions if any */
1ef5325b JG	380	if (rdev->asic->ioctl_wait_idle)
1ef5325b JG	381	robj->rdev->asic->ioctl_wait_idle(rdev, robj);
bc9025bd	382	drm_gem_object_unreference_unlocked(gobj);
1ef5325b	383	r = radeon_gem_handle_lockup(rdev, r);
771fe6b9 JG	384	return r;
771fe6b9 JG	385	}
e024e110 DA	386
	387	int radeon_gem_set_tiling_ioctl(struct drm_device dev, void data,
	388	struct drm_file *filp)
	389	{
	390	struct drm_radeon_gem_set_tiling *args = data;
	391	struct drm_gem_object *gobj;
4c788679	392	struct radeon_bo *robj;
e024e110 DA	393	int r = 0;
	394
	395	DRM_DEBUG("%d \n", args->handle);
	396	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	397	if (gobj == NULL)
bf79cb91	398	return -ENOENT;
7e4d15d9	399	robj = gem_to_radeon_bo(gobj);
4c788679	400	r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
bc9025bd	401	drm_gem_object_unreference_unlocked(gobj);
e024e110 DA	402	return r;
	403	}
	404
	405	int radeon_gem_get_tiling_ioctl(struct drm_device dev, void data,
	406	struct drm_file *filp)
	407	{
	408	struct drm_radeon_gem_get_tiling *args = data;
	409	struct drm_gem_object *gobj;
4c788679	410	struct radeon_bo *rbo;
e024e110 DA	411	int r = 0;
	412
	413	DRM_DEBUG("\n");
	414	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	415	if (gobj == NULL)
bf79cb91	416	return -ENOENT;
7e4d15d9	417	rbo = gem_to_radeon_bo(gobj);
4c788679 JG	418	r = radeon_bo_reserve(rbo, false);
4c788679 JG	419	if (unlikely(r != 0))
51f07b7e	420	goto out;
4c788679 JG	421	radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
4c788679 JG	422	radeon_bo_unreserve(rbo);
51f07b7e	423	out:
bc9025bd	424	drm_gem_object_unreference_unlocked(gobj);
721604a1 JG	425	return r;
	426	}
	427
	428	int radeon_gem_va_ioctl(struct drm_device dev, void data,
	429	struct drm_file *filp)
	430	{
	431	struct drm_radeon_gem_va *args = data;
	432	struct drm_gem_object *gobj;
	433	struct radeon_device *rdev = dev->dev_private;
	434	struct radeon_fpriv *fpriv = filp->driver_priv;
	435	struct radeon_bo *rbo;
	436	struct radeon_bo_va *bo_va;
	437	u32 invalid_flags;
	438	int r = 0;
	439
67e915e4 AD	440	if (!rdev->vm_manager.enabled) {
	441	args->operation = RADEON_VA_RESULT_ERROR;
	442	return -ENOTTY;
	443	}
	444
721604a1 JG	445	/* !! DONT REMOVE !!
	446	* We don't support vm_id yet, to be sure we don't have have broken
	447	* userspace, reject anyone trying to use non 0 value thus moving
	448	* forward we can use those fields without breaking existant userspace
	449	*/
	450	if (args->vm_id) {
	451	args->operation = RADEON_VA_RESULT_ERROR;
	452	return -EINVAL;
	453	}
	454
	455	if (args->offset < RADEON_VA_RESERVED_SIZE) {
	456	dev_err(&dev->pdev->dev,
	457	"offset 0x%lX is in reserved area 0x%X\n",
	458	(unsigned long)args->offset,
	459	RADEON_VA_RESERVED_SIZE);
	460	args->operation = RADEON_VA_RESULT_ERROR;
	461	return -EINVAL;
	462	}
	463
	464	/* don't remove, we need to enforce userspace to set the snooped flag
	465	* otherwise we will endup with broken userspace and we won't be able
	466	* to enable this feature without adding new interface
	467	*/
	468	invalid_flags = RADEON_VM_PAGE_VALID \| RADEON_VM_PAGE_SYSTEM;
	469	if ((args->flags & invalid_flags)) {
	470	dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
	471	args->flags, invalid_flags);
	472	args->operation = RADEON_VA_RESULT_ERROR;
	473	return -EINVAL;
	474	}
	475	if (!(args->flags & RADEON_VM_PAGE_SNOOPED)) {
	476	dev_err(&dev->pdev->dev, "only supported snooped mapping for now\n");
	477	args->operation = RADEON_VA_RESULT_ERROR;
	478	return -EINVAL;
	479	}
	480
	481	switch (args->operation) {
	482	case RADEON_VA_MAP:
	483	case RADEON_VA_UNMAP:
	484	break;
	485	default:
	486	dev_err(&dev->pdev->dev, "unsupported operation %d\n",
	487	args->operation);
	488	args->operation = RADEON_VA_RESULT_ERROR;
	489	return -EINVAL;
	490	}
	491
	492	gobj = drm_gem_object_lookup(dev, filp, args->handle);
	493	if (gobj == NULL) {
	494	args->operation = RADEON_VA_RESULT_ERROR;
	495	return -ENOENT;
	496	}
	497	rbo = gem_to_radeon_bo(gobj);
	498	r = radeon_bo_reserve(rbo, false);
	499	if (r) {
	500	args->operation = RADEON_VA_RESULT_ERROR;
	501	drm_gem_object_unreference_unlocked(gobj);
	502	return r;
	503	}
e971bd5e CK	504	bo_va = radeon_vm_bo_find(&fpriv->vm, rbo);
	505	if (!bo_va) {
	506	args->operation = RADEON_VA_RESULT_ERROR;
	507	drm_gem_object_unreference_unlocked(gobj);
	508	return -ENOENT;
	509	}
	510
721604a1 JG	511	switch (args->operation) {
721604a1 JG	512	case RADEON_VA_MAP:
e971bd5e	513	if (bo_va->soffset) {
721604a1 JG	514	args->operation = RADEON_VA_RESULT_VA_EXIST;
	515	args->offset = bo_va->soffset;
	516	goto out;
	517	}
e971bd5e	518	r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags);
721604a1 JG	519	break;
721604a1 JG	520	case RADEON_VA_UNMAP:
e971bd5e	521	r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0);
721604a1 JG	522	break;
	523	default:
	524	break;
	525	}
	526	args->operation = RADEON_VA_RESULT_OK;
	527	if (r) {
	528	args->operation = RADEON_VA_RESULT_ERROR;
	529	}
	530	out:
	531	radeon_bo_unreserve(rbo);
	532	drm_gem_object_unreference_unlocked(gobj);
e024e110 DA	533	return r;
e024e110 DA	534	}
ff72145b DA	535
	536	int radeon_mode_dumb_create(struct drm_file *file_priv,
	537	struct drm_device *dev,
	538	struct drm_mode_create_dumb *args)
	539	{
	540	struct radeon_device *rdev = dev->dev_private;
	541	struct drm_gem_object *gobj;
c87a8d8d	542	uint32_t handle;
ff72145b DA	543	int r;
	544
	545	args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
	546	args->size = args->pitch * args->height;
	547	args->size = ALIGN(args->size, PAGE_SIZE);
	548
	549	r = radeon_gem_object_create(rdev, args->size, 0,
	550	RADEON_GEM_DOMAIN_VRAM,
	551	false, ttm_bo_type_device,
	552	&gobj);
	553	if (r)
	554	return -ENOMEM;
	555
c87a8d8d DA	556	r = drm_gem_handle_create(file_priv, gobj, &handle);
	557	/* drop reference from allocate - handle holds it now */
	558	drm_gem_object_unreference_unlocked(gobj);
ff72145b	559	if (r) {
ff72145b DA	560	return r;
ff72145b DA	561	}
c87a8d8d	562	args->handle = handle;
ff72145b DA	563	return 0;
	564	}
	565
409851f4 JG	566	#if defined(CONFIG_DEBUG_FS)
	567	static int radeon_debugfs_gem_info(struct seq_file m, void data)
	568	{
	569	struct drm_info_node node = (struct drm_info_node )m->private;
	570	struct drm_device *dev = node->minor->dev;
	571	struct radeon_device *rdev = dev->dev_private;
	572	struct radeon_bo *rbo;
	573	unsigned i = 0;
	574
	575	mutex_lock(&rdev->gem.mutex);
	576	list_for_each_entry(rbo, &rdev->gem.objects, list) {
	577	unsigned domain;
	578	const char *placement;
	579
	580	domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type);
	581	switch (domain) {
	582	case RADEON_GEM_DOMAIN_VRAM:
	583	placement = "VRAM";
	584	break;
	585	case RADEON_GEM_DOMAIN_GTT:
	586	placement = " GTT";
	587	break;
	588	case RADEON_GEM_DOMAIN_CPU:
	589	default:
	590	placement = " CPU";
	591	break;
	592	}
	593	seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
	594	i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20,
	595	placement, (unsigned long)rbo->pid);
	596	i++;
	597	}
	598	mutex_unlock(&rdev->gem.mutex);
	599	return 0;
	600	}
	601
	602	static struct drm_info_list radeon_debugfs_gem_list[] = {
	603	{"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL},
	604	};
	605	#endif
	606
	607	int radeon_gem_debugfs_init(struct radeon_device *rdev)
	608	{
	609	#if defined(CONFIG_DEBUG_FS)
	610	return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1);
	611	#endif
	612	return 0;
	613	}