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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
40bacf16 | 29 | #include "atom.h" |
771fe6b9 JG |
30 | |
31 | /** | |
32 | * radeon_ddc_probe | |
33 | * | |
34 | */ | |
35 | bool radeon_ddc_probe(struct radeon_connector *radeon_connector) | |
36 | { | |
37 | u8 out_buf[] = { 0x0, 0x0}; | |
38 | u8 buf[2]; | |
39 | int ret; | |
40 | struct i2c_msg msgs[] = { | |
41 | { | |
42 | .addr = 0x50, | |
43 | .flags = 0, | |
44 | .len = 1, | |
45 | .buf = out_buf, | |
46 | }, | |
47 | { | |
48 | .addr = 0x50, | |
49 | .flags = I2C_M_RD, | |
50 | .len = 1, | |
51 | .buf = buf, | |
52 | } | |
53 | }; | |
54 | ||
26b5bc98 AD |
55 | /* on hw with routers, select right port */ |
56 | if (radeon_connector->router.valid) | |
57 | radeon_router_select_port(radeon_connector); | |
58 | ||
771fe6b9 JG |
59 | ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); |
60 | if (ret == 2) | |
61 | return true; | |
62 | ||
63 | return false; | |
64 | } | |
65 | ||
ac1aade6 | 66 | /* bit banging i2c */ |
771fe6b9 | 67 | |
5a6f98f5 | 68 | static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) |
771fe6b9 | 69 | { |
ab1e9ea0 AD |
70 | struct radeon_device *rdev = i2c->dev->dev_private; |
71 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
771fe6b9 | 72 | uint32_t temp; |
771fe6b9 JG |
73 | |
74 | /* RV410 appears to have a bug where the hw i2c in reset | |
75 | * holds the i2c port in a bad state - switch hw i2c away before | |
76 | * doing DDC - do this for all r200s/r300s/r400s for safety sake | |
77 | */ | |
6a93cb25 AD |
78 | if (rec->hw_capable) { |
79 | if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { | |
40bacf16 AD |
80 | u32 reg; |
81 | ||
82 | if (rdev->family >= CHIP_RV350) | |
83 | reg = RADEON_GPIO_MONID; | |
84 | else if ((rdev->family == CHIP_R300) || | |
85 | (rdev->family == CHIP_R350)) | |
86 | reg = RADEON_GPIO_DVI_DDC; | |
87 | else | |
88 | reg = RADEON_GPIO_CRT2_DDC; | |
89 | ||
90 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
91 | if (rec->a_clk_reg == reg) { | |
6a93cb25 AD |
92 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | |
93 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); | |
94 | } else { | |
95 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | | |
96 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); | |
97 | } | |
40bacf16 | 98 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
771fe6b9 JG |
99 | } |
100 | } | |
771fe6b9 | 101 | |
5786e2c5 AD |
102 | /* switch the pads to ddc mode */ |
103 | if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { | |
104 | temp = RREG32(rec->mask_clk_reg); | |
105 | temp &= ~(1 << 16); | |
106 | WREG32(rec->mask_clk_reg, temp); | |
107 | } | |
108 | ||
9b9fe724 AD |
109 | /* clear the output pin values */ |
110 | temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; | |
111 | WREG32(rec->a_clk_reg, temp); | |
112 | ||
113 | temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; | |
114 | WREG32(rec->a_data_reg, temp); | |
115 | ||
6a93cb25 AD |
116 | /* set the pins to input */ |
117 | temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; | |
118 | WREG32(rec->en_clk_reg, temp); | |
119 | ||
120 | temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; | |
121 | WREG32(rec->en_data_reg, temp); | |
9b9fe724 AD |
122 | |
123 | /* mask the gpio pins for software use */ | |
771fe6b9 JG |
124 | temp = RREG32(rec->mask_clk_reg); |
125 | if (lock_state) | |
126 | temp |= rec->mask_clk_mask; | |
127 | else | |
128 | temp &= ~rec->mask_clk_mask; | |
129 | WREG32(rec->mask_clk_reg, temp); | |
130 | temp = RREG32(rec->mask_clk_reg); | |
131 | ||
132 | temp = RREG32(rec->mask_data_reg); | |
133 | if (lock_state) | |
134 | temp |= rec->mask_data_mask; | |
135 | else | |
136 | temp &= ~rec->mask_data_mask; | |
137 | WREG32(rec->mask_data_reg, temp); | |
138 | temp = RREG32(rec->mask_data_reg); | |
139 | } | |
140 | ||
141 | static int get_clock(void *i2c_priv) | |
142 | { | |
143 | struct radeon_i2c_chan *i2c = i2c_priv; | |
144 | struct radeon_device *rdev = i2c->dev->dev_private; | |
145 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
146 | uint32_t val; | |
147 | ||
9b9fe724 AD |
148 | /* read the value off the pin */ |
149 | val = RREG32(rec->y_clk_reg); | |
150 | val &= rec->y_clk_mask; | |
771fe6b9 JG |
151 | |
152 | return (val != 0); | |
153 | } | |
154 | ||
155 | ||
156 | static int get_data(void *i2c_priv) | |
157 | { | |
158 | struct radeon_i2c_chan *i2c = i2c_priv; | |
159 | struct radeon_device *rdev = i2c->dev->dev_private; | |
160 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
161 | uint32_t val; | |
162 | ||
9b9fe724 AD |
163 | /* read the value off the pin */ |
164 | val = RREG32(rec->y_data_reg); | |
165 | val &= rec->y_data_mask; | |
166 | ||
771fe6b9 JG |
167 | return (val != 0); |
168 | } | |
169 | ||
170 | static void set_clock(void *i2c_priv, int clock) | |
171 | { | |
172 | struct radeon_i2c_chan *i2c = i2c_priv; | |
173 | struct radeon_device *rdev = i2c->dev->dev_private; | |
174 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
175 | uint32_t val; | |
176 | ||
9b9fe724 AD |
177 | /* set pin direction */ |
178 | val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; | |
179 | val |= clock ? 0 : rec->en_clk_mask; | |
180 | WREG32(rec->en_clk_reg, val); | |
771fe6b9 JG |
181 | } |
182 | ||
183 | static void set_data(void *i2c_priv, int data) | |
184 | { | |
185 | struct radeon_i2c_chan *i2c = i2c_priv; | |
186 | struct radeon_device *rdev = i2c->dev->dev_private; | |
187 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
188 | uint32_t val; | |
189 | ||
9b9fe724 AD |
190 | /* set pin direction */ |
191 | val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; | |
192 | val |= data ? 0 : rec->en_data_mask; | |
193 | WREG32(rec->en_data_reg, val); | |
771fe6b9 JG |
194 | } |
195 | ||
ac1aade6 AD |
196 | static int pre_xfer(struct i2c_adapter *i2c_adap) |
197 | { | |
198 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
199 | ||
200 | radeon_i2c_do_lock(i2c, 1); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static void post_xfer(struct i2c_adapter *i2c_adap) | |
206 | { | |
207 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
208 | ||
209 | radeon_i2c_do_lock(i2c, 0); | |
210 | } | |
211 | ||
212 | /* hw i2c */ | |
213 | ||
9dad76e8 AD |
214 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) |
215 | { | |
8807286e | 216 | u32 sclk = rdev->pm.current_sclk; |
9dad76e8 | 217 | u32 prescale = 0; |
96a4c8d5 AD |
218 | u32 nm; |
219 | u8 n, m, loop; | |
9dad76e8 AD |
220 | int i2c_clock; |
221 | ||
222 | switch (rdev->family) { | |
223 | case CHIP_R100: | |
224 | case CHIP_RV100: | |
225 | case CHIP_RS100: | |
226 | case CHIP_RV200: | |
227 | case CHIP_RS200: | |
228 | case CHIP_R200: | |
229 | case CHIP_RV250: | |
230 | case CHIP_RS300: | |
231 | case CHIP_RV280: | |
232 | case CHIP_R300: | |
233 | case CHIP_R350: | |
234 | case CHIP_RV350: | |
96a4c8d5 AD |
235 | i2c_clock = 60; |
236 | nm = (sclk * 10) / (i2c_clock * 4); | |
9dad76e8 | 237 | for (loop = 1; loop < 255; loop++) { |
96a4c8d5 | 238 | if ((nm / loop) < loop) |
9dad76e8 AD |
239 | break; |
240 | } | |
96a4c8d5 AD |
241 | n = loop - 1; |
242 | m = loop - 2; | |
243 | prescale = m | (n << 8); | |
9dad76e8 AD |
244 | break; |
245 | case CHIP_RV380: | |
246 | case CHIP_RS400: | |
247 | case CHIP_RS480: | |
248 | case CHIP_R420: | |
249 | case CHIP_R423: | |
250 | case CHIP_RV410: | |
9dad76e8 AD |
251 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
252 | break; | |
253 | case CHIP_RS600: | |
254 | case CHIP_RS690: | |
255 | case CHIP_RS740: | |
256 | /* todo */ | |
257 | break; | |
258 | case CHIP_RV515: | |
259 | case CHIP_R520: | |
260 | case CHIP_RV530: | |
261 | case CHIP_RV560: | |
262 | case CHIP_RV570: | |
263 | case CHIP_R580: | |
264 | i2c_clock = 50; | |
9dad76e8 AD |
265 | if (rdev->family == CHIP_R520) |
266 | prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); | |
267 | else | |
268 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; | |
269 | break; | |
270 | case CHIP_R600: | |
271 | case CHIP_RV610: | |
272 | case CHIP_RV630: | |
273 | case CHIP_RV670: | |
274 | /* todo */ | |
275 | break; | |
276 | case CHIP_RV620: | |
277 | case CHIP_RV635: | |
278 | case CHIP_RS780: | |
279 | case CHIP_RS880: | |
280 | case CHIP_RV770: | |
281 | case CHIP_RV730: | |
282 | case CHIP_RV710: | |
283 | case CHIP_RV740: | |
284 | /* todo */ | |
285 | break; | |
4c36b678 AD |
286 | case CHIP_CEDAR: |
287 | case CHIP_REDWOOD: | |
288 | case CHIP_JUNIPER: | |
289 | case CHIP_CYPRESS: | |
290 | case CHIP_HEMLOCK: | |
291 | /* todo */ | |
292 | break; | |
9dad76e8 AD |
293 | default: |
294 | DRM_ERROR("i2c: unhandled radeon chip\n"); | |
295 | break; | |
296 | } | |
297 | return prescale; | |
298 | } | |
299 | ||
300 | ||
40bacf16 AD |
301 | /* hw i2c engine for r1xx-4xx hardware |
302 | * hw can buffer up to 15 bytes | |
303 | */ | |
304 | static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |
305 | struct i2c_msg *msgs, int num) | |
306 | { | |
307 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
308 | struct radeon_device *rdev = i2c->dev->dev_private; | |
309 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
310 | struct i2c_msg *p; | |
311 | int i, j, k, ret = num; | |
9dad76e8 | 312 | u32 prescale; |
40bacf16 AD |
313 | u32 i2c_cntl_0, i2c_cntl_1, i2c_data; |
314 | u32 tmp, reg; | |
315 | ||
316 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
57fcab62 AD |
317 | /* take the pm lock since we need a constant sclk */ |
318 | mutex_lock(&rdev->pm.mutex); | |
319 | ||
9dad76e8 | 320 | prescale = radeon_get_i2c_prescale(rdev); |
40bacf16 AD |
321 | |
322 | reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | | |
ae08819c | 323 | RADEON_I2C_DRIVE_EN | |
40bacf16 AD |
324 | RADEON_I2C_START | |
325 | RADEON_I2C_STOP | | |
326 | RADEON_I2C_GO); | |
327 | ||
328 | if (rdev->is_atom_bios) { | |
329 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
330 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); | |
331 | } | |
332 | ||
333 | if (rec->mm_i2c) { | |
334 | i2c_cntl_0 = RADEON_I2C_CNTL_0; | |
335 | i2c_cntl_1 = RADEON_I2C_CNTL_1; | |
336 | i2c_data = RADEON_I2C_DATA; | |
337 | } else { | |
338 | i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; | |
339 | i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; | |
340 | i2c_data = RADEON_DVI_I2C_DATA; | |
341 | ||
342 | switch (rdev->family) { | |
343 | case CHIP_R100: | |
344 | case CHIP_RV100: | |
345 | case CHIP_RS100: | |
346 | case CHIP_RV200: | |
347 | case CHIP_RS200: | |
348 | case CHIP_RS300: | |
349 | switch (rec->mask_clk_reg) { | |
350 | case RADEON_GPIO_DVI_DDC: | |
351 | /* no gpio select bit */ | |
352 | break; | |
353 | default: | |
354 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
355 | ret = -EINVAL; | |
356 | goto done; | |
357 | } | |
358 | break; | |
359 | case CHIP_R200: | |
360 | /* only bit 4 on r200 */ | |
361 | switch (rec->mask_clk_reg) { | |
362 | case RADEON_GPIO_DVI_DDC: | |
363 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
364 | break; | |
365 | case RADEON_GPIO_MONID: | |
366 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
367 | break; | |
368 | default: | |
369 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
370 | ret = -EINVAL; | |
371 | goto done; | |
372 | } | |
373 | break; | |
374 | case CHIP_RV250: | |
375 | case CHIP_RV280: | |
376 | /* bits 3 and 4 */ | |
377 | switch (rec->mask_clk_reg) { | |
378 | case RADEON_GPIO_DVI_DDC: | |
379 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
380 | break; | |
381 | case RADEON_GPIO_VGA_DDC: | |
382 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); | |
383 | break; | |
384 | case RADEON_GPIO_CRT2_DDC: | |
385 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
386 | break; | |
387 | default: | |
388 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
389 | ret = -EINVAL; | |
390 | goto done; | |
391 | } | |
392 | break; | |
393 | case CHIP_R300: | |
394 | case CHIP_R350: | |
395 | /* only bit 4 on r300/r350 */ | |
396 | switch (rec->mask_clk_reg) { | |
397 | case RADEON_GPIO_VGA_DDC: | |
398 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
399 | break; | |
400 | case RADEON_GPIO_DVI_DDC: | |
401 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
402 | break; | |
403 | default: | |
404 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
405 | ret = -EINVAL; | |
406 | goto done; | |
407 | } | |
408 | break; | |
409 | case CHIP_RV350: | |
410 | case CHIP_RV380: | |
411 | case CHIP_R420: | |
412 | case CHIP_R423: | |
413 | case CHIP_RV410: | |
414 | case CHIP_RS400: | |
415 | case CHIP_RS480: | |
416 | /* bits 3 and 4 */ | |
417 | switch (rec->mask_clk_reg) { | |
418 | case RADEON_GPIO_VGA_DDC: | |
419 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); | |
420 | break; | |
421 | case RADEON_GPIO_DVI_DDC: | |
422 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); | |
423 | break; | |
424 | case RADEON_GPIO_MONID: | |
425 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); | |
426 | break; | |
427 | default: | |
428 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
429 | ret = -EINVAL; | |
430 | goto done; | |
431 | } | |
432 | break; | |
433 | default: | |
434 | DRM_ERROR("unsupported asic\n"); | |
435 | ret = -EINVAL; | |
436 | goto done; | |
437 | break; | |
438 | } | |
439 | } | |
440 | ||
441 | /* check for bus probe */ | |
442 | p = &msgs[0]; | |
443 | if ((num == 1) && (p->len == 0)) { | |
444 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
445 | RADEON_I2C_NACK | | |
446 | RADEON_I2C_HALT | | |
447 | RADEON_I2C_SOFT_RST)); | |
448 | WREG32(i2c_data, (p->addr << 1) & 0xff); | |
449 | WREG32(i2c_data, 0); | |
450 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
451 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
452 | RADEON_I2C_EN | | |
453 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
454 | WREG32(i2c_cntl_0, reg); | |
455 | for (k = 0; k < 32; k++) { | |
456 | udelay(10); | |
457 | tmp = RREG32(i2c_cntl_0); | |
458 | if (tmp & RADEON_I2C_GO) | |
459 | continue; | |
460 | tmp = RREG32(i2c_cntl_0); | |
461 | if (tmp & RADEON_I2C_DONE) | |
462 | break; | |
463 | else { | |
464 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
465 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
466 | ret = -EIO; | |
467 | goto done; | |
468 | } | |
469 | } | |
470 | goto done; | |
471 | } | |
472 | ||
473 | for (i = 0; i < num; i++) { | |
474 | p = &msgs[i]; | |
475 | for (j = 0; j < p->len; j++) { | |
476 | if (p->flags & I2C_M_RD) { | |
477 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
478 | RADEON_I2C_NACK | | |
479 | RADEON_I2C_HALT | | |
480 | RADEON_I2C_SOFT_RST)); | |
481 | WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); | |
482 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
483 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
484 | RADEON_I2C_EN | | |
485 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
486 | WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); | |
487 | for (k = 0; k < 32; k++) { | |
488 | udelay(10); | |
489 | tmp = RREG32(i2c_cntl_0); | |
490 | if (tmp & RADEON_I2C_GO) | |
491 | continue; | |
492 | tmp = RREG32(i2c_cntl_0); | |
493 | if (tmp & RADEON_I2C_DONE) | |
494 | break; | |
495 | else { | |
496 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); | |
497 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
498 | ret = -EIO; | |
499 | goto done; | |
500 | } | |
501 | } | |
502 | p->buf[j] = RREG32(i2c_data) & 0xff; | |
503 | } else { | |
504 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
505 | RADEON_I2C_NACK | | |
506 | RADEON_I2C_HALT | | |
507 | RADEON_I2C_SOFT_RST)); | |
508 | WREG32(i2c_data, (p->addr << 1) & 0xff); | |
509 | WREG32(i2c_data, p->buf[j]); | |
510 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | | |
511 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | | |
512 | RADEON_I2C_EN | | |
513 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); | |
514 | WREG32(i2c_cntl_0, reg); | |
515 | for (k = 0; k < 32; k++) { | |
516 | udelay(10); | |
517 | tmp = RREG32(i2c_cntl_0); | |
518 | if (tmp & RADEON_I2C_GO) | |
519 | continue; | |
520 | tmp = RREG32(i2c_cntl_0); | |
521 | if (tmp & RADEON_I2C_DONE) | |
522 | break; | |
523 | else { | |
524 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
525 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); | |
526 | ret = -EIO; | |
527 | goto done; | |
528 | } | |
529 | } | |
530 | } | |
531 | } | |
532 | } | |
533 | ||
534 | done: | |
535 | WREG32(i2c_cntl_0, 0); | |
536 | WREG32(i2c_cntl_1, 0); | |
537 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | | |
538 | RADEON_I2C_NACK | | |
539 | RADEON_I2C_HALT | | |
540 | RADEON_I2C_SOFT_RST)); | |
541 | ||
542 | if (rdev->is_atom_bios) { | |
543 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
544 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; | |
545 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); | |
546 | } | |
547 | ||
57fcab62 | 548 | mutex_unlock(&rdev->pm.mutex); |
40bacf16 AD |
549 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
550 | ||
551 | return ret; | |
552 | } | |
553 | ||
554 | /* hw i2c engine for r5xx hardware | |
555 | * hw can buffer up to 15 bytes | |
556 | */ | |
557 | static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |
558 | struct i2c_msg *msgs, int num) | |
559 | { | |
560 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
561 | struct radeon_device *rdev = i2c->dev->dev_private; | |
562 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
563 | struct i2c_msg *p; | |
40bacf16 | 564 | int i, j, remaining, current_count, buffer_offset, ret = num; |
9dad76e8 | 565 | u32 prescale; |
40bacf16 AD |
566 | u32 tmp, reg; |
567 | u32 saved1, saved2; | |
568 | ||
569 | mutex_lock(&rdev->dc_hw_i2c_mutex); | |
57fcab62 AD |
570 | /* take the pm lock since we need a constant sclk */ |
571 | mutex_lock(&rdev->pm.mutex); | |
572 | ||
9dad76e8 | 573 | prescale = radeon_get_i2c_prescale(rdev); |
40bacf16 AD |
574 | |
575 | /* clear gpio mask bits */ | |
576 | tmp = RREG32(rec->mask_clk_reg); | |
577 | tmp &= ~rec->mask_clk_mask; | |
578 | WREG32(rec->mask_clk_reg, tmp); | |
579 | tmp = RREG32(rec->mask_clk_reg); | |
580 | ||
581 | tmp = RREG32(rec->mask_data_reg); | |
582 | tmp &= ~rec->mask_data_mask; | |
583 | WREG32(rec->mask_data_reg, tmp); | |
584 | tmp = RREG32(rec->mask_data_reg); | |
585 | ||
586 | /* clear pin values */ | |
587 | tmp = RREG32(rec->a_clk_reg); | |
588 | tmp &= ~rec->a_clk_mask; | |
589 | WREG32(rec->a_clk_reg, tmp); | |
590 | tmp = RREG32(rec->a_clk_reg); | |
591 | ||
592 | tmp = RREG32(rec->a_data_reg); | |
593 | tmp &= ~rec->a_data_mask; | |
594 | WREG32(rec->a_data_reg, tmp); | |
595 | tmp = RREG32(rec->a_data_reg); | |
596 | ||
597 | /* set the pins to input */ | |
598 | tmp = RREG32(rec->en_clk_reg); | |
599 | tmp &= ~rec->en_clk_mask; | |
600 | WREG32(rec->en_clk_reg, tmp); | |
601 | tmp = RREG32(rec->en_clk_reg); | |
602 | ||
603 | tmp = RREG32(rec->en_data_reg); | |
604 | tmp &= ~rec->en_data_mask; | |
605 | WREG32(rec->en_data_reg, tmp); | |
606 | tmp = RREG32(rec->en_data_reg); | |
607 | ||
608 | /* */ | |
609 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
610 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); | |
611 | saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); | |
612 | saved2 = RREG32(0x494); | |
613 | WREG32(0x494, saved2 | 0x1); | |
614 | ||
615 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); | |
616 | for (i = 0; i < 50; i++) { | |
617 | udelay(1); | |
618 | if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) | |
619 | break; | |
620 | } | |
621 | if (i == 50) { | |
622 | DRM_ERROR("failed to get i2c bus\n"); | |
623 | ret = -EBUSY; | |
624 | goto done; | |
625 | } | |
626 | ||
40bacf16 AD |
627 | reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; |
628 | switch (rec->mask_clk_reg) { | |
629 | case AVIVO_DC_GPIO_DDC1_MASK: | |
630 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); | |
631 | break; | |
632 | case AVIVO_DC_GPIO_DDC2_MASK: | |
633 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); | |
634 | break; | |
635 | case AVIVO_DC_GPIO_DDC3_MASK: | |
636 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); | |
637 | break; | |
638 | default: | |
639 | DRM_ERROR("gpio not supported with hw i2c\n"); | |
640 | ret = -EINVAL; | |
641 | goto done; | |
642 | } | |
643 | ||
644 | /* check for bus probe */ | |
645 | p = &msgs[0]; | |
646 | if ((num == 1) && (p->len == 0)) { | |
647 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
648 | AVIVO_DC_I2C_NACK | | |
649 | AVIVO_DC_I2C_HALT)); | |
650 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
651 | udelay(1); | |
652 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
653 | ||
654 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); | |
655 | WREG32(AVIVO_DC_I2C_DATA, 0); | |
656 | ||
657 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
658 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
659 | AVIVO_DC_I2C_DATA_COUNT(1) | | |
660 | (prescale << 16))); | |
661 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); | |
662 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
663 | for (j = 0; j < 200; j++) { | |
664 | udelay(50); | |
665 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
666 | if (tmp & AVIVO_DC_I2C_GO) | |
667 | continue; | |
668 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
669 | if (tmp & AVIVO_DC_I2C_DONE) | |
670 | break; | |
671 | else { | |
672 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
673 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
674 | ret = -EIO; | |
675 | goto done; | |
676 | } | |
677 | } | |
678 | goto done; | |
679 | } | |
680 | ||
681 | for (i = 0; i < num; i++) { | |
682 | p = &msgs[i]; | |
683 | remaining = p->len; | |
684 | buffer_offset = 0; | |
685 | if (p->flags & I2C_M_RD) { | |
686 | while (remaining) { | |
687 | if (remaining > 15) | |
688 | current_count = 15; | |
689 | else | |
690 | current_count = remaining; | |
691 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
692 | AVIVO_DC_I2C_NACK | | |
693 | AVIVO_DC_I2C_HALT)); | |
694 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
695 | udelay(1); | |
696 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
697 | ||
698 | WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); | |
699 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
700 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
701 | AVIVO_DC_I2C_DATA_COUNT(current_count) | | |
702 | (prescale << 16))); | |
703 | WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); | |
704 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
705 | for (j = 0; j < 200; j++) { | |
706 | udelay(50); | |
707 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
708 | if (tmp & AVIVO_DC_I2C_GO) | |
709 | continue; | |
710 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
711 | if (tmp & AVIVO_DC_I2C_DONE) | |
712 | break; | |
713 | else { | |
714 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); | |
715 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
716 | ret = -EIO; | |
717 | goto done; | |
718 | } | |
719 | } | |
720 | for (j = 0; j < current_count; j++) | |
721 | p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; | |
722 | remaining -= current_count; | |
723 | buffer_offset += current_count; | |
724 | } | |
725 | } else { | |
726 | while (remaining) { | |
727 | if (remaining > 15) | |
728 | current_count = 15; | |
729 | else | |
730 | current_count = remaining; | |
731 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
732 | AVIVO_DC_I2C_NACK | | |
733 | AVIVO_DC_I2C_HALT)); | |
734 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
735 | udelay(1); | |
736 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
737 | ||
738 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); | |
739 | for (j = 0; j < current_count; j++) | |
740 | WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); | |
741 | ||
742 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); | |
743 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | | |
744 | AVIVO_DC_I2C_DATA_COUNT(current_count) | | |
745 | (prescale << 16))); | |
746 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); | |
747 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); | |
748 | for (j = 0; j < 200; j++) { | |
749 | udelay(50); | |
750 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
751 | if (tmp & AVIVO_DC_I2C_GO) | |
752 | continue; | |
753 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); | |
754 | if (tmp & AVIVO_DC_I2C_DONE) | |
755 | break; | |
756 | else { | |
757 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); | |
758 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); | |
759 | ret = -EIO; | |
760 | goto done; | |
761 | } | |
762 | } | |
763 | remaining -= current_count; | |
764 | buffer_offset += current_count; | |
765 | } | |
766 | } | |
767 | } | |
768 | ||
769 | done: | |
770 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | | |
771 | AVIVO_DC_I2C_NACK | | |
772 | AVIVO_DC_I2C_HALT)); | |
773 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); | |
774 | udelay(1); | |
775 | WREG32(AVIVO_DC_I2C_RESET, 0); | |
776 | ||
777 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); | |
778 | WREG32(AVIVO_DC_I2C_CONTROL1, saved1); | |
779 | WREG32(0x494, saved2); | |
780 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); | |
781 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; | |
782 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); | |
783 | ||
57fcab62 | 784 | mutex_unlock(&rdev->pm.mutex); |
40bacf16 AD |
785 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
786 | ||
787 | return ret; | |
788 | } | |
789 | ||
ac1aade6 | 790 | static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
40bacf16 | 791 | struct i2c_msg *msgs, int num) |
40bacf16 AD |
792 | { |
793 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |
794 | struct radeon_device *rdev = i2c->dev->dev_private; | |
795 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |
ac1aade6 | 796 | int ret = 0; |
40bacf16 AD |
797 | |
798 | switch (rdev->family) { | |
799 | case CHIP_R100: | |
800 | case CHIP_RV100: | |
801 | case CHIP_RS100: | |
802 | case CHIP_RV200: | |
803 | case CHIP_RS200: | |
804 | case CHIP_R200: | |
805 | case CHIP_RV250: | |
806 | case CHIP_RS300: | |
807 | case CHIP_RV280: | |
808 | case CHIP_R300: | |
809 | case CHIP_R350: | |
810 | case CHIP_RV350: | |
811 | case CHIP_RV380: | |
812 | case CHIP_R420: | |
813 | case CHIP_R423: | |
814 | case CHIP_RV410: | |
815 | case CHIP_RS400: | |
816 | case CHIP_RS480: | |
ac1aade6 | 817 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
40bacf16 AD |
818 | break; |
819 | case CHIP_RS600: | |
820 | case CHIP_RS690: | |
821 | case CHIP_RS740: | |
822 | /* XXX fill in hw i2c implementation */ | |
40bacf16 AD |
823 | break; |
824 | case CHIP_RV515: | |
825 | case CHIP_R520: | |
826 | case CHIP_RV530: | |
827 | case CHIP_RV560: | |
828 | case CHIP_RV570: | |
829 | case CHIP_R580: | |
ac1aade6 AD |
830 | if (rec->mm_i2c) |
831 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); | |
832 | else | |
833 | ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); | |
40bacf16 AD |
834 | break; |
835 | case CHIP_R600: | |
836 | case CHIP_RV610: | |
837 | case CHIP_RV630: | |
838 | case CHIP_RV670: | |
839 | /* XXX fill in hw i2c implementation */ | |
40bacf16 AD |
840 | break; |
841 | case CHIP_RV620: | |
842 | case CHIP_RV635: | |
843 | case CHIP_RS780: | |
844 | case CHIP_RS880: | |
845 | case CHIP_RV770: | |
846 | case CHIP_RV730: | |
847 | case CHIP_RV710: | |
848 | case CHIP_RV740: | |
849 | /* XXX fill in hw i2c implementation */ | |
40bacf16 | 850 | break; |
4c36b678 AD |
851 | case CHIP_CEDAR: |
852 | case CHIP_REDWOOD: | |
853 | case CHIP_JUNIPER: | |
854 | case CHIP_CYPRESS: | |
855 | case CHIP_HEMLOCK: | |
856 | /* XXX fill in hw i2c implementation */ | |
4c36b678 | 857 | break; |
40bacf16 AD |
858 | default: |
859 | DRM_ERROR("i2c: unhandled radeon chip\n"); | |
860 | ret = -EIO; | |
861 | break; | |
862 | } | |
863 | ||
864 | return ret; | |
865 | } | |
866 | ||
ac1aade6 | 867 | static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) |
5a6f98f5 AD |
868 | { |
869 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
870 | } | |
871 | ||
872 | static const struct i2c_algorithm radeon_i2c_algo = { | |
ac1aade6 AD |
873 | .master_xfer = radeon_hw_i2c_xfer, |
874 | .functionality = radeon_hw_i2c_func, | |
5a6f98f5 AD |
875 | }; |
876 | ||
771fe6b9 | 877 | struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
ab1e9ea0 AD |
878 | struct radeon_i2c_bus_rec *rec, |
879 | const char *name) | |
771fe6b9 | 880 | { |
ac1aade6 | 881 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
882 | struct radeon_i2c_chan *i2c; |
883 | int ret; | |
884 | ||
9a298b2a | 885 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); |
771fe6b9 JG |
886 | if (i2c == NULL) |
887 | return NULL; | |
888 | ||
40bacf16 | 889 | i2c->rec = *rec; |
5a6f98f5 | 890 | i2c->adapter.owner = THIS_MODULE; |
ac1aade6 | 891 | i2c->dev = dev; |
5a6f98f5 | 892 | i2c_set_adapdata(&i2c->adapter, i2c); |
e2b0a8e1 AD |
893 | if (rec->mm_i2c || |
894 | (rec->hw_capable && | |
895 | radeon_hw_i2c && | |
896 | ((rdev->family <= CHIP_RS480) || | |
897 | ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { | |
ac1aade6 AD |
898 | /* set the radeon hw i2c adapter */ |
899 | sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name); | |
900 | i2c->adapter.algo = &radeon_i2c_algo; | |
901 | ret = i2c_add_adapter(&i2c->adapter); | |
902 | if (ret) { | |
903 | DRM_ERROR("Failed to register hw i2c %s\n", name); | |
904 | goto out_free; | |
905 | } | |
906 | } else { | |
907 | /* set the radeon bit adapter */ | |
908 | sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name); | |
909 | i2c->adapter.algo_data = &i2c->algo.bit; | |
910 | i2c->algo.bit.pre_xfer = pre_xfer; | |
911 | i2c->algo.bit.post_xfer = post_xfer; | |
912 | i2c->algo.bit.setsda = set_data; | |
913 | i2c->algo.bit.setscl = set_clock; | |
914 | i2c->algo.bit.getsda = get_data; | |
915 | i2c->algo.bit.getscl = get_clock; | |
916 | i2c->algo.bit.udelay = 20; | |
917 | /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always | |
918 | * make this, 2 jiffies is a lot more reliable */ | |
919 | i2c->algo.bit.timeout = 2; | |
920 | i2c->algo.bit.data = i2c; | |
921 | ret = i2c_bit_add_bus(&i2c->adapter); | |
922 | if (ret) { | |
923 | DRM_ERROR("Failed to register bit i2c %s\n", name); | |
924 | goto out_free; | |
925 | } | |
771fe6b9 JG |
926 | } |
927 | ||
928 | return i2c; | |
929 | out_free: | |
9a298b2a | 930 | kfree(i2c); |
771fe6b9 JG |
931 | return NULL; |
932 | ||
933 | } | |
934 | ||
746c1aa4 | 935 | struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
6a93cb25 AD |
936 | struct radeon_i2c_bus_rec *rec, |
937 | const char *name) | |
746c1aa4 DA |
938 | { |
939 | struct radeon_i2c_chan *i2c; | |
940 | int ret; | |
941 | ||
942 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); | |
943 | if (i2c == NULL) | |
944 | return NULL; | |
945 | ||
6a93cb25 | 946 | i2c->rec = *rec; |
746c1aa4 DA |
947 | i2c->adapter.owner = THIS_MODULE; |
948 | i2c->dev = dev; | |
949 | i2c_set_adapdata(&i2c->adapter, i2c); | |
950 | i2c->adapter.algo_data = &i2c->algo.dp; | |
951 | i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; | |
952 | i2c->algo.dp.address = 0; | |
953 | ret = i2c_dp_aux_add_bus(&i2c->adapter); | |
954 | if (ret) { | |
955 | DRM_INFO("Failed to register i2c %s\n", name); | |
956 | goto out_free; | |
957 | } | |
958 | ||
959 | return i2c; | |
960 | out_free: | |
961 | kfree(i2c); | |
962 | return NULL; | |
963 | ||
964 | } | |
965 | ||
771fe6b9 | 966 | void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) |
5a6f98f5 AD |
967 | { |
968 | if (!i2c) | |
969 | return; | |
771fe6b9 | 970 | i2c_del_adapter(&i2c->adapter); |
9a298b2a | 971 | kfree(i2c); |
771fe6b9 JG |
972 | } |
973 | ||
f376b94f AD |
974 | /* Add the default buses */ |
975 | void radeon_i2c_init(struct radeon_device *rdev) | |
976 | { | |
977 | if (rdev->is_atom_bios) | |
978 | radeon_atombios_i2c_init(rdev); | |
979 | else | |
980 | radeon_combios_i2c_init(rdev); | |
981 | } | |
982 | ||
983 | /* remove all the buses */ | |
984 | void radeon_i2c_fini(struct radeon_device *rdev) | |
985 | { | |
986 | int i; | |
987 | ||
988 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
989 | if (rdev->i2c_bus[i]) { | |
990 | radeon_i2c_destroy(rdev->i2c_bus[i]); | |
991 | rdev->i2c_bus[i] = NULL; | |
992 | } | |
993 | } | |
994 | } | |
995 | ||
996 | /* Add additional buses */ | |
997 | void radeon_i2c_add(struct radeon_device *rdev, | |
998 | struct radeon_i2c_bus_rec *rec, | |
999 | const char *name) | |
1000 | { | |
1001 | struct drm_device *dev = rdev->ddev; | |
1002 | int i; | |
1003 | ||
1004 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
1005 | if (!rdev->i2c_bus[i]) { | |
1006 | rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); | |
1007 | return; | |
1008 | } | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | /* looks up bus based on id */ | |
1013 | struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |
1014 | struct radeon_i2c_bus_rec *i2c_bus) | |
1015 | { | |
1016 | int i; | |
1017 | ||
1018 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { | |
1019 | if (rdev->i2c_bus[i] && | |
1020 | (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { | |
1021 | return rdev->i2c_bus[i]; | |
1022 | } | |
1023 | } | |
1024 | return NULL; | |
1025 | } | |
1026 | ||
771fe6b9 JG |
1027 | struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) |
1028 | { | |
1029 | return NULL; | |
1030 | } | |
fcec570b | 1031 | |
5a6f98f5 AD |
1032 | void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
1033 | u8 slave_addr, | |
1034 | u8 addr, | |
1035 | u8 *val) | |
fcec570b AD |
1036 | { |
1037 | u8 out_buf[2]; | |
1038 | u8 in_buf[2]; | |
1039 | struct i2c_msg msgs[] = { | |
1040 | { | |
1041 | .addr = slave_addr, | |
1042 | .flags = 0, | |
1043 | .len = 1, | |
1044 | .buf = out_buf, | |
1045 | }, | |
1046 | { | |
1047 | .addr = slave_addr, | |
1048 | .flags = I2C_M_RD, | |
1049 | .len = 1, | |
1050 | .buf = in_buf, | |
1051 | } | |
1052 | }; | |
1053 | ||
1054 | out_buf[0] = addr; | |
1055 | out_buf[1] = 0; | |
1056 | ||
1057 | if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { | |
1058 | *val = in_buf[0]; | |
1059 | DRM_DEBUG("val = 0x%02x\n", *val); | |
1060 | } else { | |
1061 | DRM_ERROR("i2c 0x%02x 0x%02x read failed\n", | |
1062 | addr, *val); | |
1063 | } | |
1064 | } | |
1065 | ||
5a6f98f5 AD |
1066 | void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, |
1067 | u8 slave_addr, | |
1068 | u8 addr, | |
1069 | u8 val) | |
fcec570b AD |
1070 | { |
1071 | uint8_t out_buf[2]; | |
1072 | struct i2c_msg msg = { | |
1073 | .addr = slave_addr, | |
1074 | .flags = 0, | |
1075 | .len = 2, | |
1076 | .buf = out_buf, | |
1077 | }; | |
1078 | ||
1079 | out_buf[0] = addr; | |
1080 | out_buf[1] = val; | |
1081 | ||
1082 | if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) | |
1083 | DRM_ERROR("i2c 0x%02x 0x%02x write failed\n", | |
1084 | addr, val); | |
1085 | } | |
1086 | ||
26b5bc98 AD |
1087 | /* router switching */ |
1088 | void radeon_router_select_port(struct radeon_connector *radeon_connector) | |
1089 | { | |
1090 | u8 val; | |
1091 | ||
1092 | if (!radeon_connector->router.valid) | |
1093 | return; | |
1094 | ||
1095 | radeon_i2c_get_byte(radeon_connector->router_bus, | |
1096 | radeon_connector->router.i2c_addr, | |
1097 | 0x3, &val); | |
1098 | val &= radeon_connector->router.mux_control_pin; | |
1099 | radeon_i2c_put_byte(radeon_connector->router_bus, | |
1100 | radeon_connector->router.i2c_addr, | |
1101 | 0x3, val); | |
1102 | radeon_i2c_get_byte(radeon_connector->router_bus, | |
1103 | radeon_connector->router.i2c_addr, | |
1104 | 0x1, &val); | |
1105 | val &= radeon_connector->router.mux_control_pin; | |
1106 | val |= radeon_connector->router.mux_state; | |
1107 | radeon_i2c_put_byte(radeon_connector->router_bus, | |
1108 | radeon_connector->router.i2c_addr, | |
1109 | 0x1, val); | |
1110 | } | |
1111 |