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drm/radeon/kms: use new pre/post_xfer i2c bit algo hooks
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_i2c.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
40bacf16 29#include "atom.h"
771fe6b9
JG		 30
31/**
32 * radeon_ddc_probe
33 *
34 */
35bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
36{
37 u8 out_buf[] = { 0x0, 0x0};
38 u8 buf[2];
39 int ret;
40 struct i2c_msg msgs[] = {
41 {
42 .addr = 0x50,
43 .flags = 0,
44 .len = 1,
45 .buf = out_buf,
46 },
47 {
48 .addr = 0x50,
49 .flags = I2C_M_RD,
50 .len = 1,
51 .buf = buf,
52 }
53 };
54
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
56 if (ret == 2)
57 return true;
58
59 return false;
60}
61
ac1aade6 62/* bit banging i2c */
771fe6b9 63
5a6f98f5 64static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
771fe6b9 65{
ab1e9ea0
AD		 66 struct radeon_device *rdev = i2c->dev->dev_private;
67 struct radeon_i2c_bus_rec *rec = &i2c->rec;
771fe6b9 68 uint32_t temp;
771fe6b9
JG		 69
70 /* RV410 appears to have a bug where the hw i2c in reset
71 * holds the i2c port in a bad state - switch hw i2c away before
72 * doing DDC - do this for all r200s/r300s/r400s for safety sake
73 */
6a93cb25
AD		 74 if (rec->hw_capable) {
75 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
40bacf16
AD		 76 u32 reg;
77
78 if (rdev->family >= CHIP_RV350)
79 reg = RADEON_GPIO_MONID;
80 else if ((rdev->family == CHIP_R300) ||
81 (rdev->family == CHIP_R350))
82 reg = RADEON_GPIO_DVI_DDC;
83 else
84 reg = RADEON_GPIO_CRT2_DDC;
85
86 mutex_lock(&rdev->dc_hw_i2c_mutex);
87 if (rec->a_clk_reg == reg) {
6a93cb25
AD		 88 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
89 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
90 } else {
91 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
92 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
93 }
40bacf16 94 mutex_unlock(&rdev->dc_hw_i2c_mutex);
771fe6b9
JG		 95 }
96 }
771fe6b9 97
9b9fe724
AD		 98 /* clear the output pin values */
99 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
100 WREG32(rec->a_clk_reg, temp);
101
102 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
103 WREG32(rec->a_data_reg, temp);
104
6a93cb25
AD		 105 /* set the pins to input */
106 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
107 WREG32(rec->en_clk_reg, temp);
108
109 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
110 WREG32(rec->en_data_reg, temp);
9b9fe724
AD		 111
112 /* mask the gpio pins for software use */
771fe6b9
JG		 113 temp = RREG32(rec->mask_clk_reg);
114 if (lock_state)
115 temp |= rec->mask_clk_mask;
116 else
117 temp &= ~rec->mask_clk_mask;
118 WREG32(rec->mask_clk_reg, temp);
119 temp = RREG32(rec->mask_clk_reg);
120
121 temp = RREG32(rec->mask_data_reg);
122 if (lock_state)
123 temp |= rec->mask_data_mask;
124 else
125 temp &= ~rec->mask_data_mask;
126 WREG32(rec->mask_data_reg, temp);
127 temp = RREG32(rec->mask_data_reg);
128}
129
130static int get_clock(void *i2c_priv)
131{
132 struct radeon_i2c_chan *i2c = i2c_priv;
133 struct radeon_device *rdev = i2c->dev->dev_private;
134 struct radeon_i2c_bus_rec *rec = &i2c->rec;
135 uint32_t val;
136
9b9fe724
AD		 137 /* read the value off the pin */
138 val = RREG32(rec->y_clk_reg);
139 val &= rec->y_clk_mask;
771fe6b9
JG		 140
141 return (val != 0);
142}
143
144
145static int get_data(void *i2c_priv)
146{
147 struct radeon_i2c_chan *i2c = i2c_priv;
148 struct radeon_device *rdev = i2c->dev->dev_private;
149 struct radeon_i2c_bus_rec *rec = &i2c->rec;
150 uint32_t val;
151
9b9fe724
AD		 152 /* read the value off the pin */
153 val = RREG32(rec->y_data_reg);
154 val &= rec->y_data_mask;
155
771fe6b9
JG		 156 return (val != 0);
157}
158
159static void set_clock(void *i2c_priv, int clock)
160{
161 struct radeon_i2c_chan *i2c = i2c_priv;
162 struct radeon_device *rdev = i2c->dev->dev_private;
163 struct radeon_i2c_bus_rec *rec = &i2c->rec;
164 uint32_t val;
165
9b9fe724
AD		 166 /* set pin direction */
167 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
168 val |= clock ? 0 : rec->en_clk_mask;
169 WREG32(rec->en_clk_reg, val);
771fe6b9
JG		 170}
171
172static void set_data(void *i2c_priv, int data)
173{
174 struct radeon_i2c_chan *i2c = i2c_priv;
175 struct radeon_device *rdev = i2c->dev->dev_private;
176 struct radeon_i2c_bus_rec *rec = &i2c->rec;
177 uint32_t val;
178
9b9fe724
AD		 179 /* set pin direction */
180 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
181 val |= data ? 0 : rec->en_data_mask;
182 WREG32(rec->en_data_reg, val);
771fe6b9
JG		 183}
184
ac1aade6
AD		 185static int pre_xfer(struct i2c_adapter *i2c_adap)
186{
187 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
188
189 radeon_i2c_do_lock(i2c, 1);
190
191 return 0;
192}
193
194static void post_xfer(struct i2c_adapter *i2c_adap)
195{
196 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
197
198 radeon_i2c_do_lock(i2c, 0);
199}
200
201/* hw i2c */
202
9dad76e8
AD		 203static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
204{
9dad76e8
AD		 205 u32 sclk = radeon_get_engine_clock(rdev);
206 u32 prescale = 0;
96a4c8d5
AD		 207 u32 nm;
208 u8 n, m, loop;
9dad76e8
AD		 209 int i2c_clock;
210
211 switch (rdev->family) {
212 case CHIP_R100:
213 case CHIP_RV100:
214 case CHIP_RS100:
215 case CHIP_RV200:
216 case CHIP_RS200:
217 case CHIP_R200:
218 case CHIP_RV250:
219 case CHIP_RS300:
220 case CHIP_RV280:
221 case CHIP_R300:
222 case CHIP_R350:
223 case CHIP_RV350:
96a4c8d5
AD		 224 i2c_clock = 60;
225 nm = (sclk * 10) / (i2c_clock * 4);
9dad76e8 226 for (loop = 1; loop < 255; loop++) {
96a4c8d5 227 if ((nm / loop) < loop)
9dad76e8
AD		 228 break;
229 }
96a4c8d5
AD		 230 n = loop - 1;
231 m = loop - 2;
232 prescale = m | (n << 8);
9dad76e8
AD		 233 break;
234 case CHIP_RV380:
235 case CHIP_RS400:
236 case CHIP_RS480:
237 case CHIP_R420:
238 case CHIP_R423:
239 case CHIP_RV410:
9dad76e8
AD		 240 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
241 break;
242 case CHIP_RS600:
243 case CHIP_RS690:
244 case CHIP_RS740:
245 /* todo */
246 break;
247 case CHIP_RV515:
248 case CHIP_R520:
249 case CHIP_RV530:
250 case CHIP_RV560:
251 case CHIP_RV570:
252 case CHIP_R580:
253 i2c_clock = 50;
9dad76e8
AD		 254 if (rdev->family == CHIP_R520)
255 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
256 else
257 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
258 break;
259 case CHIP_R600:
260 case CHIP_RV610:
261 case CHIP_RV630:
262 case CHIP_RV670:
263 /* todo */
264 break;
265 case CHIP_RV620:
266 case CHIP_RV635:
267 case CHIP_RS780:
268 case CHIP_RS880:
269 case CHIP_RV770:
270 case CHIP_RV730:
271 case CHIP_RV710:
272 case CHIP_RV740:
273 /* todo */
274 break;
4c36b678
AD		 275 case CHIP_CEDAR:
276 case CHIP_REDWOOD:
277 case CHIP_JUNIPER:
278 case CHIP_CYPRESS:
279 case CHIP_HEMLOCK:
280 /* todo */
281 break;
9dad76e8
AD		 282 default:
283 DRM_ERROR("i2c: unhandled radeon chip\n");
284 break;
285 }
286 return prescale;
287}
288
289
40bacf16
AD		 290/* hw i2c engine for r1xx-4xx hardware
291 * hw can buffer up to 15 bytes
292 */
293static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
294 struct i2c_msg *msgs, int num)
295{
296 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
297 struct radeon_device *rdev = i2c->dev->dev_private;
298 struct radeon_i2c_bus_rec *rec = &i2c->rec;
299 struct i2c_msg *p;
300 int i, j, k, ret = num;
9dad76e8 301 u32 prescale;
40bacf16
AD		 302 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
303 u32 tmp, reg;
304
305 mutex_lock(&rdev->dc_hw_i2c_mutex);
57fcab62
AD		 306 /* take the pm lock since we need a constant sclk */
307 mutex_lock(&rdev->pm.mutex);
308
9dad76e8 309 prescale = radeon_get_i2c_prescale(rdev);
40bacf16
AD		 310
311 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
ae08819c 312 RADEON_I2C_DRIVE_EN |
40bacf16
AD		 313 RADEON_I2C_START |
314 RADEON_I2C_STOP |
315 RADEON_I2C_GO);
316
317 if (rdev->is_atom_bios) {
318 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
319 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
320 }
321
322 if (rec->mm_i2c) {
323 i2c_cntl_0 = RADEON_I2C_CNTL_0;
324 i2c_cntl_1 = RADEON_I2C_CNTL_1;
325 i2c_data = RADEON_I2C_DATA;
326 } else {
327 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
328 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
329 i2c_data = RADEON_DVI_I2C_DATA;
330
331 switch (rdev->family) {
332 case CHIP_R100:
333 case CHIP_RV100:
334 case CHIP_RS100:
335 case CHIP_RV200:
336 case CHIP_RS200:
337 case CHIP_RS300:
338 switch (rec->mask_clk_reg) {
339 case RADEON_GPIO_DVI_DDC:
340 /* no gpio select bit */
341 break;
342 default:
343 DRM_ERROR("gpio not supported with hw i2c\n");
344 ret = -EINVAL;
345 goto done;
346 }
347 break;
348 case CHIP_R200:
349 /* only bit 4 on r200 */
350 switch (rec->mask_clk_reg) {
351 case RADEON_GPIO_DVI_DDC:
352 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
353 break;
354 case RADEON_GPIO_MONID:
355 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
356 break;
357 default:
358 DRM_ERROR("gpio not supported with hw i2c\n");
359 ret = -EINVAL;
360 goto done;
361 }
362 break;
363 case CHIP_RV250:
364 case CHIP_RV280:
365 /* bits 3 and 4 */
366 switch (rec->mask_clk_reg) {
367 case RADEON_GPIO_DVI_DDC:
368 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
369 break;
370 case RADEON_GPIO_VGA_DDC:
371 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
372 break;
373 case RADEON_GPIO_CRT2_DDC:
374 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
375 break;
376 default:
377 DRM_ERROR("gpio not supported with hw i2c\n");
378 ret = -EINVAL;
379 goto done;
380 }
381 break;
382 case CHIP_R300:
383 case CHIP_R350:
384 /* only bit 4 on r300/r350 */
385 switch (rec->mask_clk_reg) {
386 case RADEON_GPIO_VGA_DDC:
387 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
388 break;
389 case RADEON_GPIO_DVI_DDC:
390 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
391 break;
392 default:
393 DRM_ERROR("gpio not supported with hw i2c\n");
394 ret = -EINVAL;
395 goto done;
396 }
397 break;
398 case CHIP_RV350:
399 case CHIP_RV380:
400 case CHIP_R420:
401 case CHIP_R423:
402 case CHIP_RV410:
403 case CHIP_RS400:
404 case CHIP_RS480:
405 /* bits 3 and 4 */
406 switch (rec->mask_clk_reg) {
407 case RADEON_GPIO_VGA_DDC:
408 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
409 break;
410 case RADEON_GPIO_DVI_DDC:
411 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
412 break;
413 case RADEON_GPIO_MONID:
414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
415 break;
416 default:
417 DRM_ERROR("gpio not supported with hw i2c\n");
418 ret = -EINVAL;
419 goto done;
420 }
421 break;
422 default:
423 DRM_ERROR("unsupported asic\n");
424 ret = -EINVAL;
425 goto done;
426 break;
427 }
428 }
429
430 /* check for bus probe */
431 p = &msgs[0];
432 if ((num == 1) && (p->len == 0)) {
433 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
434 RADEON_I2C_NACK |
435 RADEON_I2C_HALT |
436 RADEON_I2C_SOFT_RST));
437 WREG32(i2c_data, (p->addr << 1) & 0xff);
438 WREG32(i2c_data, 0);
439 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
440 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
441 RADEON_I2C_EN |
442 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
443 WREG32(i2c_cntl_0, reg);
444 for (k = 0; k < 32; k++) {
445 udelay(10);
446 tmp = RREG32(i2c_cntl_0);
447 if (tmp & RADEON_I2C_GO)
448 continue;
449 tmp = RREG32(i2c_cntl_0);
450 if (tmp & RADEON_I2C_DONE)
451 break;
452 else {
453 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
454 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
455 ret = -EIO;
456 goto done;
457 }
458 }
459 goto done;
460 }
461
462 for (i = 0; i < num; i++) {
463 p = &msgs[i];
464 for (j = 0; j < p->len; j++) {
465 if (p->flags & I2C_M_RD) {
466 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
467 RADEON_I2C_NACK |
468 RADEON_I2C_HALT |
469 RADEON_I2C_SOFT_RST));
470 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
471 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
472 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
473 RADEON_I2C_EN |
474 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
475 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
476 for (k = 0; k < 32; k++) {
477 udelay(10);
478 tmp = RREG32(i2c_cntl_0);
479 if (tmp & RADEON_I2C_GO)
480 continue;
481 tmp = RREG32(i2c_cntl_0);
482 if (tmp & RADEON_I2C_DONE)
483 break;
484 else {
485 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
486 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
487 ret = -EIO;
488 goto done;
489 }
490 }
491 p->buf[j] = RREG32(i2c_data) & 0xff;
492 } else {
493 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
494 RADEON_I2C_NACK |
495 RADEON_I2C_HALT |
496 RADEON_I2C_SOFT_RST));
497 WREG32(i2c_data, (p->addr << 1) & 0xff);
498 WREG32(i2c_data, p->buf[j]);
499 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
500 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
501 RADEON_I2C_EN |
502 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
503 WREG32(i2c_cntl_0, reg);
504 for (k = 0; k < 32; k++) {
505 udelay(10);
506 tmp = RREG32(i2c_cntl_0);
507 if (tmp & RADEON_I2C_GO)
508 continue;
509 tmp = RREG32(i2c_cntl_0);
510 if (tmp & RADEON_I2C_DONE)
511 break;
512 else {
513 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
514 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
515 ret = -EIO;
516 goto done;
517 }
518 }
519 }
520 }
521 }
522
523done:
524 WREG32(i2c_cntl_0, 0);
525 WREG32(i2c_cntl_1, 0);
526 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
527 RADEON_I2C_NACK |
528 RADEON_I2C_HALT |
529 RADEON_I2C_SOFT_RST));
530
531 if (rdev->is_atom_bios) {
532 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
533 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
534 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
535 }
536
57fcab62 537 mutex_unlock(&rdev->pm.mutex);
40bacf16
AD		 538 mutex_unlock(&rdev->dc_hw_i2c_mutex);
539
540 return ret;
541}
542
543/* hw i2c engine for r5xx hardware
544 * hw can buffer up to 15 bytes
545 */
546static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
547 struct i2c_msg *msgs, int num)
548{
549 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
550 struct radeon_device *rdev = i2c->dev->dev_private;
551 struct radeon_i2c_bus_rec *rec = &i2c->rec;
552 struct i2c_msg *p;
40bacf16 553 int i, j, remaining, current_count, buffer_offset, ret = num;
9dad76e8 554 u32 prescale;
40bacf16
AD		 555 u32 tmp, reg;
556 u32 saved1, saved2;
557
558 mutex_lock(&rdev->dc_hw_i2c_mutex);
57fcab62
AD		 559 /* take the pm lock since we need a constant sclk */
560 mutex_lock(&rdev->pm.mutex);
561
9dad76e8 562 prescale = radeon_get_i2c_prescale(rdev);
40bacf16
AD		 563
564 /* clear gpio mask bits */
565 tmp = RREG32(rec->mask_clk_reg);
566 tmp &= ~rec->mask_clk_mask;
567 WREG32(rec->mask_clk_reg, tmp);
568 tmp = RREG32(rec->mask_clk_reg);
569
570 tmp = RREG32(rec->mask_data_reg);
571 tmp &= ~rec->mask_data_mask;
572 WREG32(rec->mask_data_reg, tmp);
573 tmp = RREG32(rec->mask_data_reg);
574
575 /* clear pin values */
576 tmp = RREG32(rec->a_clk_reg);
577 tmp &= ~rec->a_clk_mask;
578 WREG32(rec->a_clk_reg, tmp);
579 tmp = RREG32(rec->a_clk_reg);
580
581 tmp = RREG32(rec->a_data_reg);
582 tmp &= ~rec->a_data_mask;
583 WREG32(rec->a_data_reg, tmp);
584 tmp = RREG32(rec->a_data_reg);
585
586 /* set the pins to input */
587 tmp = RREG32(rec->en_clk_reg);
588 tmp &= ~rec->en_clk_mask;
589 WREG32(rec->en_clk_reg, tmp);
590 tmp = RREG32(rec->en_clk_reg);
591
592 tmp = RREG32(rec->en_data_reg);
593 tmp &= ~rec->en_data_mask;
594 WREG32(rec->en_data_reg, tmp);
595 tmp = RREG32(rec->en_data_reg);
596
597 /* */
598 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
599 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
600 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
601 saved2 = RREG32(0x494);
602 WREG32(0x494, saved2 | 0x1);
603
604 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
605 for (i = 0; i < 50; i++) {
606 udelay(1);
607 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
608 break;
609 }
610 if (i == 50) {
611 DRM_ERROR("failed to get i2c bus\n");
612 ret = -EBUSY;
613 goto done;
614 }
615
40bacf16
AD		 616 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
617 switch (rec->mask_clk_reg) {
618 case AVIVO_DC_GPIO_DDC1_MASK:
619 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
620 break;
621 case AVIVO_DC_GPIO_DDC2_MASK:
622 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
623 break;
624 case AVIVO_DC_GPIO_DDC3_MASK:
625 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
626 break;
627 default:
628 DRM_ERROR("gpio not supported with hw i2c\n");
629 ret = -EINVAL;
630 goto done;
631 }
632
633 /* check for bus probe */
634 p = &msgs[0];
635 if ((num == 1) && (p->len == 0)) {
636 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
637 AVIVO_DC_I2C_NACK |
638 AVIVO_DC_I2C_HALT));
639 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
640 udelay(1);
641 WREG32(AVIVO_DC_I2C_RESET, 0);
642
643 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
644 WREG32(AVIVO_DC_I2C_DATA, 0);
645
646 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
647 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
648 AVIVO_DC_I2C_DATA_COUNT(1) |
649 (prescale << 16)));
650 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
651 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
652 for (j = 0; j < 200; j++) {
653 udelay(50);
654 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
655 if (tmp & AVIVO_DC_I2C_GO)
656 continue;
657 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
658 if (tmp & AVIVO_DC_I2C_DONE)
659 break;
660 else {
661 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
662 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
663 ret = -EIO;
664 goto done;
665 }
666 }
667 goto done;
668 }
669
670 for (i = 0; i < num; i++) {
671 p = &msgs[i];
672 remaining = p->len;
673 buffer_offset = 0;
674 if (p->flags & I2C_M_RD) {
675 while (remaining) {
676 if (remaining > 15)
677 current_count = 15;
678 else
679 current_count = remaining;
680 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
681 AVIVO_DC_I2C_NACK |
682 AVIVO_DC_I2C_HALT));
683 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
684 udelay(1);
685 WREG32(AVIVO_DC_I2C_RESET, 0);
686
687 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
688 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
689 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
690 AVIVO_DC_I2C_DATA_COUNT(current_count) |
691 (prescale << 16)));
692 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
693 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
694 for (j = 0; j < 200; j++) {
695 udelay(50);
696 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
697 if (tmp & AVIVO_DC_I2C_GO)
698 continue;
699 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
700 if (tmp & AVIVO_DC_I2C_DONE)
701 break;
702 else {
703 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
704 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
705 ret = -EIO;
706 goto done;
707 }
708 }
709 for (j = 0; j < current_count; j++)
710 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
711 remaining -= current_count;
712 buffer_offset += current_count;
713 }
714 } else {
715 while (remaining) {
716 if (remaining > 15)
717 current_count = 15;
718 else
719 current_count = remaining;
720 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
721 AVIVO_DC_I2C_NACK |
722 AVIVO_DC_I2C_HALT));
723 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
724 udelay(1);
725 WREG32(AVIVO_DC_I2C_RESET, 0);
726
727 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
728 for (j = 0; j < current_count; j++)
729 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
730
731 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
732 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
733 AVIVO_DC_I2C_DATA_COUNT(current_count) |
734 (prescale << 16)));
735 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
736 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
737 for (j = 0; j < 200; j++) {
738 udelay(50);
739 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
740 if (tmp & AVIVO_DC_I2C_GO)
741 continue;
742 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
743 if (tmp & AVIVO_DC_I2C_DONE)
744 break;
745 else {
746 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
747 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
748 ret = -EIO;
749 goto done;
750 }
751 }
752 remaining -= current_count;
753 buffer_offset += current_count;
754 }
755 }
756 }
757
758done:
759 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
760 AVIVO_DC_I2C_NACK |
761 AVIVO_DC_I2C_HALT));
762 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
763 udelay(1);
764 WREG32(AVIVO_DC_I2C_RESET, 0);
765
766 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
767 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
768 WREG32(0x494, saved2);
769 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
770 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
771 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
772
57fcab62 773 mutex_unlock(&rdev->pm.mutex);
40bacf16
AD		 774 mutex_unlock(&rdev->dc_hw_i2c_mutex);
775
776 return ret;
777}
778
ac1aade6 779static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
40bacf16 780 struct i2c_msg *msgs, int num)
40bacf16
AD		 781{
782 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
783 struct radeon_device *rdev = i2c->dev->dev_private;
784 struct radeon_i2c_bus_rec *rec = &i2c->rec;
ac1aade6 785 int ret = 0;
40bacf16
AD		 786
787 switch (rdev->family) {
788 case CHIP_R100:
789 case CHIP_RV100:
790 case CHIP_RS100:
791 case CHIP_RV200:
792 case CHIP_RS200:
793 case CHIP_R200:
794 case CHIP_RV250:
795 case CHIP_RS300:
796 case CHIP_RV280:
797 case CHIP_R300:
798 case CHIP_R350:
799 case CHIP_RV350:
800 case CHIP_RV380:
801 case CHIP_R420:
802 case CHIP_R423:
803 case CHIP_RV410:
804 case CHIP_RS400:
805 case CHIP_RS480:
ac1aade6 806 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
40bacf16
AD		 807 break;
808 case CHIP_RS600:
809 case CHIP_RS690:
810 case CHIP_RS740:
811 /* XXX fill in hw i2c implementation */
40bacf16
AD		 812 break;
813 case CHIP_RV515:
814 case CHIP_R520:
815 case CHIP_RV530:
816 case CHIP_RV560:
817 case CHIP_RV570:
818 case CHIP_R580:
ac1aade6
AD		 819 if (rec->mm_i2c)
820 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
821 else
822 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
40bacf16
AD		 823 break;
824 case CHIP_R600:
825 case CHIP_RV610:
826 case CHIP_RV630:
827 case CHIP_RV670:
828 /* XXX fill in hw i2c implementation */
40bacf16
AD		 829 break;
830 case CHIP_RV620:
831 case CHIP_RV635:
832 case CHIP_RS780:
833 case CHIP_RS880:
834 case CHIP_RV770:
835 case CHIP_RV730:
836 case CHIP_RV710:
837 case CHIP_RV740:
838 /* XXX fill in hw i2c implementation */
40bacf16 839 break;
4c36b678
AD		 840 case CHIP_CEDAR:
841 case CHIP_REDWOOD:
842 case CHIP_JUNIPER:
843 case CHIP_CYPRESS:
844 case CHIP_HEMLOCK:
845 /* XXX fill in hw i2c implementation */
4c36b678 846 break;
40bacf16
AD		 847 default:
848 DRM_ERROR("i2c: unhandled radeon chip\n");
849 ret = -EIO;
850 break;
851 }
852
853 return ret;
854}
855
ac1aade6 856static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
5a6f98f5
AD		 857{
858 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
859}
860
861static const struct i2c_algorithm radeon_i2c_algo = {
ac1aade6
AD		 862 .master_xfer = radeon_hw_i2c_xfer,
863 .functionality = radeon_hw_i2c_func,
5a6f98f5
AD		 864};
865
771fe6b9 866struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
ab1e9ea0
AD		 867 struct radeon_i2c_bus_rec *rec,
868 const char *name)
771fe6b9 869{
ac1aade6 870 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 871 struct radeon_i2c_chan *i2c;
872 int ret;
873
9a298b2a 874 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
771fe6b9
JG		 875 if (i2c == NULL)
876 return NULL;
877
40bacf16 878 i2c->rec = *rec;
5a6f98f5 879 i2c->adapter.owner = THIS_MODULE;
ac1aade6 880 i2c->dev = dev;
5a6f98f5 881 i2c_set_adapdata(&i2c->adapter, i2c);
ac1aade6
AD		 882 if (rec->hw_capable &&
883 ((rdev->family <= CHIP_RS480) ||
884 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580)))) {
885 /* set the radeon hw i2c adapter */
886 sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name);
887 i2c->adapter.algo = &radeon_i2c_algo;
888 ret = i2c_add_adapter(&i2c->adapter);
889 if (ret) {
890 DRM_ERROR("Failed to register hw i2c %s\n", name);
891 goto out_free;
892 }
893 } else {
894 /* set the radeon bit adapter */
895 sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name);
896 i2c->adapter.algo_data = &i2c->algo.bit;
897 i2c->algo.bit.pre_xfer = pre_xfer;
898 i2c->algo.bit.post_xfer = post_xfer;
899 i2c->algo.bit.setsda = set_data;
900 i2c->algo.bit.setscl = set_clock;
901 i2c->algo.bit.getsda = get_data;
902 i2c->algo.bit.getscl = get_clock;
903 i2c->algo.bit.udelay = 20;
904 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
905 * make this, 2 jiffies is a lot more reliable */
906 i2c->algo.bit.timeout = 2;
907 i2c->algo.bit.data = i2c;
908 ret = i2c_bit_add_bus(&i2c->adapter);
909 if (ret) {
910 DRM_ERROR("Failed to register bit i2c %s\n", name);
911 goto out_free;
912 }
771fe6b9
JG		 913 }
914
915 return i2c;
916out_free:
9a298b2a 917 kfree(i2c);
771fe6b9
JG		 918 return NULL;
919
920}
921
746c1aa4 922struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 923 struct radeon_i2c_bus_rec *rec,
924 const char *name)
746c1aa4
DA		 925{
926 struct radeon_i2c_chan *i2c;
927 int ret;
928
929 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
930 if (i2c == NULL)
931 return NULL;
932
6a93cb25 933 i2c->rec = *rec;
746c1aa4
DA		 934 i2c->adapter.owner = THIS_MODULE;
935 i2c->dev = dev;
936 i2c_set_adapdata(&i2c->adapter, i2c);
937 i2c->adapter.algo_data = &i2c->algo.dp;
938 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
939 i2c->algo.dp.address = 0;
940 ret = i2c_dp_aux_add_bus(&i2c->adapter);
941 if (ret) {
942 DRM_INFO("Failed to register i2c %s\n", name);
943 goto out_free;
944 }
945
946 return i2c;
947out_free:
948 kfree(i2c);
949 return NULL;
950
951}
952
771fe6b9 953void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
5a6f98f5
AD		 954{
955 if (!i2c)
956 return;
771fe6b9 957 i2c_del_adapter(&i2c->adapter);
9a298b2a 958 kfree(i2c);
771fe6b9
JG		 959}
960
961struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
962{
963 return NULL;
964}
fcec570b 965
5a6f98f5
AD		 966void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
967 u8 slave_addr,
968 u8 addr,
969 u8 *val)
fcec570b
AD		 970{
971 u8 out_buf[2];
972 u8 in_buf[2];
973 struct i2c_msg msgs[] = {
974 {
975 .addr = slave_addr,
976 .flags = 0,
977 .len = 1,
978 .buf = out_buf,
979 },
980 {
981 .addr = slave_addr,
982 .flags = I2C_M_RD,
983 .len = 1,
984 .buf = in_buf,
985 }
986 };
987
988 out_buf[0] = addr;
989 out_buf[1] = 0;
990
991 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
992 *val = in_buf[0];
993 DRM_DEBUG("val = 0x%02x\n", *val);
994 } else {
995 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
996 addr, *val);
997 }
998}
999
5a6f98f5
AD		 1000void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1001 u8 slave_addr,
1002 u8 addr,
1003 u8 val)
fcec570b
AD		 1004{
1005 uint8_t out_buf[2];
1006 struct i2c_msg msg = {
1007 .addr = slave_addr,
1008 .flags = 0,
1009 .len = 2,
1010 .buf = out_buf,
1011 };
1012
1013 out_buf[0] = addr;
1014 out_buf[1] = val;
1015
1016 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1017 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
1018 addr, val);
1019}
1020
Linux kernel - Deliverables
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