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drm/radeon/kms: add initial Evergreen support (Radeon HD 5xxx)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_i2c.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
40bacf16 29#include "atom.h"
771fe6b9
JG		 30
31/**
32 * radeon_ddc_probe
33 *
34 */
35bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
36{
37 u8 out_buf[] = { 0x0, 0x0};
38 u8 buf[2];
39 int ret;
40 struct i2c_msg msgs[] = {
41 {
42 .addr = 0x50,
43 .flags = 0,
44 .len = 1,
45 .buf = out_buf,
46 },
47 {
48 .addr = 0x50,
49 .flags = I2C_M_RD,
50 .len = 1,
51 .buf = buf,
52 }
53 };
54
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
56 if (ret == 2)
57 return true;
58
59 return false;
60}
61
62
5a6f98f5 63static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
771fe6b9 64{
ab1e9ea0
AD		 65 struct radeon_device *rdev = i2c->dev->dev_private;
66 struct radeon_i2c_bus_rec *rec = &i2c->rec;
771fe6b9 67 uint32_t temp;
771fe6b9
JG		 68
69 /* RV410 appears to have a bug where the hw i2c in reset
70 * holds the i2c port in a bad state - switch hw i2c away before
71 * doing DDC - do this for all r200s/r300s/r400s for safety sake
72 */
6a93cb25
AD		 73 if (rec->hw_capable) {
74 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
40bacf16
AD		 75 u32 reg;
76
77 if (rdev->family >= CHIP_RV350)
78 reg = RADEON_GPIO_MONID;
79 else if ((rdev->family == CHIP_R300) ||
80 (rdev->family == CHIP_R350))
81 reg = RADEON_GPIO_DVI_DDC;
82 else
83 reg = RADEON_GPIO_CRT2_DDC;
84
85 mutex_lock(&rdev->dc_hw_i2c_mutex);
86 if (rec->a_clk_reg == reg) {
6a93cb25
AD		 87 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
88 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
89 } else {
90 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
91 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
92 }
40bacf16 93 mutex_unlock(&rdev->dc_hw_i2c_mutex);
771fe6b9
JG		 94 }
95 }
771fe6b9 96
9b9fe724
AD		 97 /* clear the output pin values */
98 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
99 WREG32(rec->a_clk_reg, temp);
100
101 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
102 WREG32(rec->a_data_reg, temp);
103
6a93cb25
AD		 104 /* set the pins to input */
105 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
106 WREG32(rec->en_clk_reg, temp);
107
108 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
109 WREG32(rec->en_data_reg, temp);
9b9fe724
AD		 110
111 /* mask the gpio pins for software use */
771fe6b9
JG		 112 temp = RREG32(rec->mask_clk_reg);
113 if (lock_state)
114 temp |= rec->mask_clk_mask;
115 else
116 temp &= ~rec->mask_clk_mask;
117 WREG32(rec->mask_clk_reg, temp);
118 temp = RREG32(rec->mask_clk_reg);
119
120 temp = RREG32(rec->mask_data_reg);
121 if (lock_state)
122 temp |= rec->mask_data_mask;
123 else
124 temp &= ~rec->mask_data_mask;
125 WREG32(rec->mask_data_reg, temp);
126 temp = RREG32(rec->mask_data_reg);
127}
128
129static int get_clock(void *i2c_priv)
130{
131 struct radeon_i2c_chan *i2c = i2c_priv;
132 struct radeon_device *rdev = i2c->dev->dev_private;
133 struct radeon_i2c_bus_rec *rec = &i2c->rec;
134 uint32_t val;
135
9b9fe724
AD		 136 /* read the value off the pin */
137 val = RREG32(rec->y_clk_reg);
138 val &= rec->y_clk_mask;
771fe6b9
JG		 139
140 return (val != 0);
141}
142
143
144static int get_data(void *i2c_priv)
145{
146 struct radeon_i2c_chan *i2c = i2c_priv;
147 struct radeon_device *rdev = i2c->dev->dev_private;
148 struct radeon_i2c_bus_rec *rec = &i2c->rec;
149 uint32_t val;
150
9b9fe724
AD		 151 /* read the value off the pin */
152 val = RREG32(rec->y_data_reg);
153 val &= rec->y_data_mask;
154
771fe6b9
JG		 155 return (val != 0);
156}
157
158static void set_clock(void *i2c_priv, int clock)
159{
160 struct radeon_i2c_chan *i2c = i2c_priv;
161 struct radeon_device *rdev = i2c->dev->dev_private;
162 struct radeon_i2c_bus_rec *rec = &i2c->rec;
163 uint32_t val;
164
9b9fe724
AD		 165 /* set pin direction */
166 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
167 val |= clock ? 0 : rec->en_clk_mask;
168 WREG32(rec->en_clk_reg, val);
771fe6b9
JG		 169}
170
171static void set_data(void *i2c_priv, int data)
172{
173 struct radeon_i2c_chan *i2c = i2c_priv;
174 struct radeon_device *rdev = i2c->dev->dev_private;
175 struct radeon_i2c_bus_rec *rec = &i2c->rec;
176 uint32_t val;
177
9b9fe724
AD		 178 /* set pin direction */
179 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
180 val |= data ? 0 : rec->en_data_mask;
181 WREG32(rec->en_data_reg, val);
771fe6b9
JG		 182}
183
40bacf16
AD		 184/* hw i2c engine for r1xx-4xx hardware
185 * hw can buffer up to 15 bytes
186 */
187static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
188 struct i2c_msg *msgs, int num)
189{
190 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
191 struct radeon_device *rdev = i2c->dev->dev_private;
192 struct radeon_i2c_bus_rec *rec = &i2c->rec;
193 struct i2c_msg *p;
194 int i, j, k, ret = num;
57fcab62 195 u32 sclk, prescale;
40bacf16
AD		 196 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
197 u32 tmp, reg;
198
199 mutex_lock(&rdev->dc_hw_i2c_mutex);
57fcab62
AD		 200 /* take the pm lock since we need a constant sclk */
201 mutex_lock(&rdev->pm.mutex);
202
203 sclk = radeon_get_engine_clock(rdev);
204 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
40bacf16
AD		 205
206 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
207 RADEON_I2C_START |
208 RADEON_I2C_STOP |
209 RADEON_I2C_GO);
210
211 if (rdev->is_atom_bios) {
212 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
213 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
214 }
215
216 if (rec->mm_i2c) {
217 i2c_cntl_0 = RADEON_I2C_CNTL_0;
218 i2c_cntl_1 = RADEON_I2C_CNTL_1;
219 i2c_data = RADEON_I2C_DATA;
220 } else {
221 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
222 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
223 i2c_data = RADEON_DVI_I2C_DATA;
224
225 switch (rdev->family) {
226 case CHIP_R100:
227 case CHIP_RV100:
228 case CHIP_RS100:
229 case CHIP_RV200:
230 case CHIP_RS200:
231 case CHIP_RS300:
232 switch (rec->mask_clk_reg) {
233 case RADEON_GPIO_DVI_DDC:
234 /* no gpio select bit */
235 break;
236 default:
237 DRM_ERROR("gpio not supported with hw i2c\n");
238 ret = -EINVAL;
239 goto done;
240 }
241 break;
242 case CHIP_R200:
243 /* only bit 4 on r200 */
244 switch (rec->mask_clk_reg) {
245 case RADEON_GPIO_DVI_DDC:
246 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
247 break;
248 case RADEON_GPIO_MONID:
249 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
250 break;
251 default:
252 DRM_ERROR("gpio not supported with hw i2c\n");
253 ret = -EINVAL;
254 goto done;
255 }
256 break;
257 case CHIP_RV250:
258 case CHIP_RV280:
259 /* bits 3 and 4 */
260 switch (rec->mask_clk_reg) {
261 case RADEON_GPIO_DVI_DDC:
262 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
263 break;
264 case RADEON_GPIO_VGA_DDC:
265 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
266 break;
267 case RADEON_GPIO_CRT2_DDC:
268 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
269 break;
270 default:
271 DRM_ERROR("gpio not supported with hw i2c\n");
272 ret = -EINVAL;
273 goto done;
274 }
275 break;
276 case CHIP_R300:
277 case CHIP_R350:
278 /* only bit 4 on r300/r350 */
279 switch (rec->mask_clk_reg) {
280 case RADEON_GPIO_VGA_DDC:
281 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
282 break;
283 case RADEON_GPIO_DVI_DDC:
284 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
285 break;
286 default:
287 DRM_ERROR("gpio not supported with hw i2c\n");
288 ret = -EINVAL;
289 goto done;
290 }
291 break;
292 case CHIP_RV350:
293 case CHIP_RV380:
294 case CHIP_R420:
295 case CHIP_R423:
296 case CHIP_RV410:
297 case CHIP_RS400:
298 case CHIP_RS480:
299 /* bits 3 and 4 */
300 switch (rec->mask_clk_reg) {
301 case RADEON_GPIO_VGA_DDC:
302 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
303 break;
304 case RADEON_GPIO_DVI_DDC:
305 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
306 break;
307 case RADEON_GPIO_MONID:
308 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
309 break;
310 default:
311 DRM_ERROR("gpio not supported with hw i2c\n");
312 ret = -EINVAL;
313 goto done;
314 }
315 break;
316 default:
317 DRM_ERROR("unsupported asic\n");
318 ret = -EINVAL;
319 goto done;
320 break;
321 }
322 }
323
324 /* check for bus probe */
325 p = &msgs[0];
326 if ((num == 1) && (p->len == 0)) {
327 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
328 RADEON_I2C_NACK |
329 RADEON_I2C_HALT |
330 RADEON_I2C_SOFT_RST));
331 WREG32(i2c_data, (p->addr << 1) & 0xff);
332 WREG32(i2c_data, 0);
333 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
334 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
335 RADEON_I2C_EN |
336 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
337 WREG32(i2c_cntl_0, reg);
338 for (k = 0; k < 32; k++) {
339 udelay(10);
340 tmp = RREG32(i2c_cntl_0);
341 if (tmp & RADEON_I2C_GO)
342 continue;
343 tmp = RREG32(i2c_cntl_0);
344 if (tmp & RADEON_I2C_DONE)
345 break;
346 else {
347 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
348 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
349 ret = -EIO;
350 goto done;
351 }
352 }
353 goto done;
354 }
355
356 for (i = 0; i < num; i++) {
357 p = &msgs[i];
358 for (j = 0; j < p->len; j++) {
359 if (p->flags & I2C_M_RD) {
360 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
361 RADEON_I2C_NACK |
362 RADEON_I2C_HALT |
363 RADEON_I2C_SOFT_RST));
364 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
365 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
366 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
367 RADEON_I2C_EN |
368 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
369 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
370 for (k = 0; k < 32; k++) {
371 udelay(10);
372 tmp = RREG32(i2c_cntl_0);
373 if (tmp & RADEON_I2C_GO)
374 continue;
375 tmp = RREG32(i2c_cntl_0);
376 if (tmp & RADEON_I2C_DONE)
377 break;
378 else {
379 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
380 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
381 ret = -EIO;
382 goto done;
383 }
384 }
385 p->buf[j] = RREG32(i2c_data) & 0xff;
386 } else {
387 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
388 RADEON_I2C_NACK |
389 RADEON_I2C_HALT |
390 RADEON_I2C_SOFT_RST));
391 WREG32(i2c_data, (p->addr << 1) & 0xff);
392 WREG32(i2c_data, p->buf[j]);
393 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
394 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
395 RADEON_I2C_EN |
396 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
397 WREG32(i2c_cntl_0, reg);
398 for (k = 0; k < 32; k++) {
399 udelay(10);
400 tmp = RREG32(i2c_cntl_0);
401 if (tmp & RADEON_I2C_GO)
402 continue;
403 tmp = RREG32(i2c_cntl_0);
404 if (tmp & RADEON_I2C_DONE)
405 break;
406 else {
407 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
408 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
409 ret = -EIO;
410 goto done;
411 }
412 }
413 }
414 }
415 }
416
417done:
418 WREG32(i2c_cntl_0, 0);
419 WREG32(i2c_cntl_1, 0);
420 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
421 RADEON_I2C_NACK |
422 RADEON_I2C_HALT |
423 RADEON_I2C_SOFT_RST));
424
425 if (rdev->is_atom_bios) {
426 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
427 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
428 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
429 }
430
57fcab62 431 mutex_unlock(&rdev->pm.mutex);
40bacf16
AD		 432 mutex_unlock(&rdev->dc_hw_i2c_mutex);
433
434 return ret;
435}
436
437/* hw i2c engine for r5xx hardware
438 * hw can buffer up to 15 bytes
439 */
440static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
441 struct i2c_msg *msgs, int num)
442{
443 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
444 struct radeon_device *rdev = i2c->dev->dev_private;
445 struct radeon_i2c_bus_rec *rec = &i2c->rec;
446 struct i2c_msg *p;
447 int i2c_clock = 50;
448 int i, j, remaining, current_count, buffer_offset, ret = num;
57fcab62 449 u32 sclk, prescale;
40bacf16
AD		 450 u32 tmp, reg;
451 u32 saved1, saved2;
452
453 mutex_lock(&rdev->dc_hw_i2c_mutex);
57fcab62
AD		 454 /* take the pm lock since we need a constant sclk */
455 mutex_lock(&rdev->pm.mutex);
456
457 sclk = radeon_get_engine_clock(rdev);
458 if (rdev->family == CHIP_R520)
459 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
460 else
461 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
40bacf16
AD		 462
463 /* clear gpio mask bits */
464 tmp = RREG32(rec->mask_clk_reg);
465 tmp &= ~rec->mask_clk_mask;
466 WREG32(rec->mask_clk_reg, tmp);
467 tmp = RREG32(rec->mask_clk_reg);
468
469 tmp = RREG32(rec->mask_data_reg);
470 tmp &= ~rec->mask_data_mask;
471 WREG32(rec->mask_data_reg, tmp);
472 tmp = RREG32(rec->mask_data_reg);
473
474 /* clear pin values */
475 tmp = RREG32(rec->a_clk_reg);
476 tmp &= ~rec->a_clk_mask;
477 WREG32(rec->a_clk_reg, tmp);
478 tmp = RREG32(rec->a_clk_reg);
479
480 tmp = RREG32(rec->a_data_reg);
481 tmp &= ~rec->a_data_mask;
482 WREG32(rec->a_data_reg, tmp);
483 tmp = RREG32(rec->a_data_reg);
484
485 /* set the pins to input */
486 tmp = RREG32(rec->en_clk_reg);
487 tmp &= ~rec->en_clk_mask;
488 WREG32(rec->en_clk_reg, tmp);
489 tmp = RREG32(rec->en_clk_reg);
490
491 tmp = RREG32(rec->en_data_reg);
492 tmp &= ~rec->en_data_mask;
493 WREG32(rec->en_data_reg, tmp);
494 tmp = RREG32(rec->en_data_reg);
495
496 /* */
497 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
498 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
499 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
500 saved2 = RREG32(0x494);
501 WREG32(0x494, saved2 | 0x1);
502
503 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
504 for (i = 0; i < 50; i++) {
505 udelay(1);
506 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
507 break;
508 }
509 if (i == 50) {
510 DRM_ERROR("failed to get i2c bus\n");
511 ret = -EBUSY;
512 goto done;
513 }
514
40bacf16
AD		 515 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
516 switch (rec->mask_clk_reg) {
517 case AVIVO_DC_GPIO_DDC1_MASK:
518 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
519 break;
520 case AVIVO_DC_GPIO_DDC2_MASK:
521 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
522 break;
523 case AVIVO_DC_GPIO_DDC3_MASK:
524 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
525 break;
526 default:
527 DRM_ERROR("gpio not supported with hw i2c\n");
528 ret = -EINVAL;
529 goto done;
530 }
531
532 /* check for bus probe */
533 p = &msgs[0];
534 if ((num == 1) && (p->len == 0)) {
535 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
536 AVIVO_DC_I2C_NACK |
537 AVIVO_DC_I2C_HALT));
538 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
539 udelay(1);
540 WREG32(AVIVO_DC_I2C_RESET, 0);
541
542 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
543 WREG32(AVIVO_DC_I2C_DATA, 0);
544
545 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
546 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
547 AVIVO_DC_I2C_DATA_COUNT(1) |
548 (prescale << 16)));
549 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
550 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
551 for (j = 0; j < 200; j++) {
552 udelay(50);
553 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
554 if (tmp & AVIVO_DC_I2C_GO)
555 continue;
556 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
557 if (tmp & AVIVO_DC_I2C_DONE)
558 break;
559 else {
560 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
561 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
562 ret = -EIO;
563 goto done;
564 }
565 }
566 goto done;
567 }
568
569 for (i = 0; i < num; i++) {
570 p = &msgs[i];
571 remaining = p->len;
572 buffer_offset = 0;
573 if (p->flags & I2C_M_RD) {
574 while (remaining) {
575 if (remaining > 15)
576 current_count = 15;
577 else
578 current_count = remaining;
579 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
580 AVIVO_DC_I2C_NACK |
581 AVIVO_DC_I2C_HALT));
582 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
583 udelay(1);
584 WREG32(AVIVO_DC_I2C_RESET, 0);
585
586 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
587 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
588 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
589 AVIVO_DC_I2C_DATA_COUNT(current_count) |
590 (prescale << 16)));
591 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
592 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
593 for (j = 0; j < 200; j++) {
594 udelay(50);
595 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
596 if (tmp & AVIVO_DC_I2C_GO)
597 continue;
598 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
599 if (tmp & AVIVO_DC_I2C_DONE)
600 break;
601 else {
602 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
603 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
604 ret = -EIO;
605 goto done;
606 }
607 }
608 for (j = 0; j < current_count; j++)
609 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
610 remaining -= current_count;
611 buffer_offset += current_count;
612 }
613 } else {
614 while (remaining) {
615 if (remaining > 15)
616 current_count = 15;
617 else
618 current_count = remaining;
619 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
620 AVIVO_DC_I2C_NACK |
621 AVIVO_DC_I2C_HALT));
622 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
623 udelay(1);
624 WREG32(AVIVO_DC_I2C_RESET, 0);
625
626 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
627 for (j = 0; j < current_count; j++)
628 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
629
630 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
631 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
632 AVIVO_DC_I2C_DATA_COUNT(current_count) |
633 (prescale << 16)));
634 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
635 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
636 for (j = 0; j < 200; j++) {
637 udelay(50);
638 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
639 if (tmp & AVIVO_DC_I2C_GO)
640 continue;
641 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
642 if (tmp & AVIVO_DC_I2C_DONE)
643 break;
644 else {
645 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
646 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
647 ret = -EIO;
648 goto done;
649 }
650 }
651 remaining -= current_count;
652 buffer_offset += current_count;
653 }
654 }
655 }
656
657done:
658 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
659 AVIVO_DC_I2C_NACK |
660 AVIVO_DC_I2C_HALT));
661 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
662 udelay(1);
663 WREG32(AVIVO_DC_I2C_RESET, 0);
664
665 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
666 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
667 WREG32(0x494, saved2);
668 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
669 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
670 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
671
57fcab62 672 mutex_unlock(&rdev->pm.mutex);
40bacf16
AD		 673 mutex_unlock(&rdev->dc_hw_i2c_mutex);
674
675 return ret;
676}
677
678static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
679 struct i2c_msg *msgs, int num)
5a6f98f5
AD		 680{
681 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
682 int ret;
683
684 radeon_i2c_do_lock(i2c, 1);
40bacf16 685 ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
5a6f98f5
AD		 686 radeon_i2c_do_lock(i2c, 0);
687
688 return ret;
689}
690
40bacf16
AD		 691static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
692 struct i2c_msg *msgs, int num)
693{
694 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
695 struct radeon_device *rdev = i2c->dev->dev_private;
696 struct radeon_i2c_bus_rec *rec = &i2c->rec;
697 int ret;
698
699 switch (rdev->family) {
700 case CHIP_R100:
701 case CHIP_RV100:
702 case CHIP_RS100:
703 case CHIP_RV200:
704 case CHIP_RS200:
705 case CHIP_R200:
706 case CHIP_RV250:
707 case CHIP_RS300:
708 case CHIP_RV280:
709 case CHIP_R300:
710 case CHIP_R350:
711 case CHIP_RV350:
712 case CHIP_RV380:
713 case CHIP_R420:
714 case CHIP_R423:
715 case CHIP_RV410:
716 case CHIP_RS400:
717 case CHIP_RS480:
718 if (rec->hw_capable)
719 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
720 else
721 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
722 break;
723 case CHIP_RS600:
724 case CHIP_RS690:
725 case CHIP_RS740:
726 /* XXX fill in hw i2c implementation */
727 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
728 break;
729 case CHIP_RV515:
730 case CHIP_R520:
731 case CHIP_RV530:
732 case CHIP_RV560:
733 case CHIP_RV570:
734 case CHIP_R580:
735 if (rec->hw_capable) {
736 if (rec->mm_i2c)
737 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
738 else
739 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
740 } else
741 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
742 break;
743 case CHIP_R600:
744 case CHIP_RV610:
745 case CHIP_RV630:
746 case CHIP_RV670:
747 /* XXX fill in hw i2c implementation */
748 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
749 break;
750 case CHIP_RV620:
751 case CHIP_RV635:
752 case CHIP_RS780:
753 case CHIP_RS880:
754 case CHIP_RV770:
755 case CHIP_RV730:
756 case CHIP_RV710:
757 case CHIP_RV740:
758 /* XXX fill in hw i2c implementation */
759 ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
760 break;
761 default:
762 DRM_ERROR("i2c: unhandled radeon chip\n");
763 ret = -EIO;
764 break;
765 }
766
767 return ret;
768}
769
5a6f98f5
AD		 770static u32 radeon_i2c_func(struct i2c_adapter *adap)
771{
772 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
773}
774
775static const struct i2c_algorithm radeon_i2c_algo = {
776 .master_xfer = radeon_i2c_xfer,
777 .functionality = radeon_i2c_func,
778};
779
771fe6b9 780struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
ab1e9ea0
AD		 781 struct radeon_i2c_bus_rec *rec,
782 const char *name)
771fe6b9
JG		 783{
784 struct radeon_i2c_chan *i2c;
785 int ret;
786
9a298b2a 787 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
771fe6b9
JG		 788 if (i2c == NULL)
789 return NULL;
790
5a6f98f5
AD		 791 /* set the internal bit adapter */
792 i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
793 i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
794 sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
795 i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
796 i2c->algo.radeon.bit_data.setsda = set_data;
797 i2c->algo.radeon.bit_data.setscl = set_clock;
798 i2c->algo.radeon.bit_data.getsda = get_data;
799 i2c->algo.radeon.bit_data.getscl = get_clock;
800 i2c->algo.radeon.bit_data.udelay = 20;
771fe6b9
JG		 801 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
802 * make this, 2 jiffies is a lot more reliable */
5a6f98f5
AD		 803 i2c->algo.radeon.bit_data.timeout = 2;
804 i2c->algo.radeon.bit_data.data = i2c;
805 ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
806 if (ret) {
40bacf16 807 DRM_ERROR("Failed to register internal bit i2c %s\n", name);
5a6f98f5
AD		 808 goto out_free;
809 }
810 /* set the radeon i2c adapter */
40bacf16
AD		 811 i2c->dev = dev;
812 i2c->rec = *rec;
5a6f98f5
AD		 813 i2c->adapter.owner = THIS_MODULE;
814 i2c_set_adapdata(&i2c->adapter, i2c);
815 sprintf(i2c->adapter.name, "Radeon i2c %s", name);
816 i2c->adapter.algo_data = &i2c->algo.radeon;
817 i2c->adapter.algo = &radeon_i2c_algo;
818 ret = i2c_add_adapter(&i2c->adapter);
771fe6b9 819 if (ret) {
40bacf16 820 DRM_ERROR("Failed to register i2c %s\n", name);
771fe6b9
JG		 821 goto out_free;
822 }
823
824 return i2c;
825out_free:
9a298b2a 826 kfree(i2c);
771fe6b9
JG		 827 return NULL;
828
829}
830
746c1aa4 831struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 832 struct radeon_i2c_bus_rec *rec,
833 const char *name)
746c1aa4
DA		 834{
835 struct radeon_i2c_chan *i2c;
836 int ret;
837
838 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
839 if (i2c == NULL)
840 return NULL;
841
6a93cb25 842 i2c->rec = *rec;
746c1aa4
DA		 843 i2c->adapter.owner = THIS_MODULE;
844 i2c->dev = dev;
845 i2c_set_adapdata(&i2c->adapter, i2c);
846 i2c->adapter.algo_data = &i2c->algo.dp;
847 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
848 i2c->algo.dp.address = 0;
849 ret = i2c_dp_aux_add_bus(&i2c->adapter);
850 if (ret) {
851 DRM_INFO("Failed to register i2c %s\n", name);
852 goto out_free;
853 }
854
855 return i2c;
856out_free:
857 kfree(i2c);
858 return NULL;
859
860}
861
771fe6b9 862void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
5a6f98f5
AD		 863{
864 if (!i2c)
865 return;
866 i2c_del_adapter(&i2c->algo.radeon.bit_adapter);
867 i2c_del_adapter(&i2c->adapter);
868 kfree(i2c);
869}
870
871void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
771fe6b9
JG		 872{
873 if (!i2c)
874 return;
875
876 i2c_del_adapter(&i2c->adapter);
9a298b2a 877 kfree(i2c);
771fe6b9
JG		 878}
879
880struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
881{
882 return NULL;
883}
fcec570b 884
5a6f98f5
AD		 885void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
886 u8 slave_addr,
887 u8 addr,
888 u8 *val)
fcec570b
AD		 889{
890 u8 out_buf[2];
891 u8 in_buf[2];
892 struct i2c_msg msgs[] = {
893 {
894 .addr = slave_addr,
895 .flags = 0,
896 .len = 1,
897 .buf = out_buf,
898 },
899 {
900 .addr = slave_addr,
901 .flags = I2C_M_RD,
902 .len = 1,
903 .buf = in_buf,
904 }
905 };
906
907 out_buf[0] = addr;
908 out_buf[1] = 0;
909
910 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
911 *val = in_buf[0];
912 DRM_DEBUG("val = 0x%02x\n", *val);
913 } else {
914 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
915 addr, *val);
916 }
917}
918
5a6f98f5
AD		 919void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
920 u8 slave_addr,
921 u8 addr,
922 u8 val)
fcec570b
AD		 923{
924 uint8_t out_buf[2];
925 struct i2c_msg msg = {
926 .addr = slave_addr,
927 .flags = 0,
928 .len = 2,
929 .buf = out_buf,
930 };
931
932 out_buf[0] = addr;
933 out_buf[1] = val;
934
935 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
936 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
937 addr, val);
938}
939
Linux kernel - Deliverables
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