[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_irq_kms.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"

irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *) arg;
	struct radeon_device *rdev = dev->dev_private;

	return radeon_irq_process(rdev);
}

/*
 * Handle hotplug events outside the interrupt handler proper.
 */
static void radeon_hotplug_work_func(struct work_struct *work)
{
	struct radeon_device *rdev = container_of(work, struct radeon_device,
						  hotplug_work);
	struct drm_device *dev = rdev->ddev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;

	if (mode_config->num_connector) {
		list_for_each_entry(connector, &mode_config->connector_list, head)
			radeon_connector_hotplug(connector);
	}
	/* Just fire off a uevent and let userspace tell us what to do */
	drm_helper_hpd_irq_event(dev);
}

void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	unsigned i;

	/* Disable *all* interrupts */
	for (i = 0; i < RADEON_NUM_RINGS; i++)
		rdev->irq.sw_int[i] = false;
	rdev->irq.gui_idle = false;
	for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
		rdev->irq.hpd[i] = false;
	for (i = 0; i < RADEON_MAX_CRTCS; i++) {
		rdev->irq.crtc_vblank_int[i] = false;
		rdev->irq.pflip[i] = false;
	}
	radeon_irq_set(rdev);
	/* Clear bits */
	radeon_irq_process(rdev);
}

int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	unsigned i;

	dev->max_vblank_count = 0x001fffff;
	for (i = 0; i < RADEON_NUM_RINGS; i++)
		rdev->irq.sw_int[i] = true;
	radeon_irq_set(rdev);
	return 0;
}

void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	unsigned i;

	if (rdev == NULL) {
		return;
	}
	/* Disable *all* interrupts */
	for (i = 0; i < RADEON_NUM_RINGS; i++)
		rdev->irq.sw_int[i] = false;
	rdev->irq.gui_idle = false;
	for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
		rdev->irq.hpd[i] = false;
	for (i = 0; i < RADEON_MAX_CRTCS; i++) {
		rdev->irq.crtc_vblank_int[i] = false;
		rdev->irq.pflip[i] = false;
	}
	radeon_irq_set(rdev);
}

static bool radeon_msi_ok(struct radeon_device *rdev)
{
	/* RV370/RV380 was first asic with MSI support */
	if (rdev->family < CHIP_RV380)
		return false;

	/* MSIs don't work on AGP */
	if (rdev->flags & RADEON_IS_AGP)
		return false;

	/* force MSI on */
	if (radeon_msi == 1)
		return true;
	else if (radeon_msi == 0)
		return false;

	/* Quirks */
	/* HP RS690 only seems to work with MSIs. */
	if ((rdev->pdev->device == 0x791f) &&
	    (rdev->pdev->subsystem_vendor == 0x103c) &&
	    (rdev->pdev->subsystem_device == 0x30c2))
		return true;

	/* Dell RS690 only seems to work with MSIs. */
	if ((rdev->pdev->device == 0x791f) &&
	    (rdev->pdev->subsystem_vendor == 0x1028) &&
	    (rdev->pdev->subsystem_device == 0x01fd))
		return true;

	if (rdev->flags & RADEON_IS_IGP) {
		/* APUs work fine with MSIs */
		if (rdev->family >= CHIP_PALM)
			return true;
		/* lots of IGPs have problems with MSIs */
		return false;
	}

	return true;
}

int radeon_irq_kms_init(struct radeon_device *rdev)
{
	int i;
	int r = 0;

	INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);

	spin_lock_init(&rdev->irq.sw_lock);
	for (i = 0; i < rdev->num_crtc; i++)
		spin_lock_init(&rdev->irq.pflip_lock[i]);
	r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
	if (r) {
		return r;
	}
	/* enable msi */
	rdev->msi_enabled = 0;

	if (radeon_msi_ok(rdev)) {
		int ret = pci_enable_msi(rdev->pdev);
		if (!ret) {
			rdev->msi_enabled = 1;
			dev_info(rdev->dev, "radeon: using MSI.\n");
		}
	}
	rdev->irq.installed = true;
	r = drm_irq_install(rdev->ddev);
	if (r) {
		rdev->irq.installed = false;
		return r;
	}
	DRM_INFO("radeon: irq initialized.\n");
	return 0;
}

void radeon_irq_kms_fini(struct radeon_device *rdev)
{
	drm_vblank_cleanup(rdev->ddev);
	if (rdev->irq.installed) {
		drm_irq_uninstall(rdev->ddev);
		rdev->irq.installed = false;
		if (rdev->msi_enabled)
			pci_disable_msi(rdev->pdev);
	}
	flush_work_sync(&rdev->hotplug_work);
}

void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring)
{
	unsigned long irqflags;

	spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
	if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount[ring] == 1)) {
		rdev->irq.sw_int[ring] = true;
		radeon_irq_set(rdev);
	}
	spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
}

void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
{
	unsigned long irqflags;

	spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
	BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount[ring] <= 0);
	if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount[ring] == 0)) {
		rdev->irq.sw_int[ring] = false;
		radeon_irq_set(rdev);
	}
	spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
}

void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
{
	unsigned long irqflags;

	if (crtc < 0 || crtc >= rdev->num_crtc)
		return;

	spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
	if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
		rdev->irq.pflip[crtc] = true;
		radeon_irq_set(rdev);
	}
	spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
}

void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
{
	unsigned long irqflags;

	if (crtc < 0 || crtc >= rdev->num_crtc)
		return;

	spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
	BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
	if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
		rdev->irq.pflip[crtc] = false;
		radeon_irq_set(rdev);
	}
	spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
eb1f8e4f	29	#include "drm_crtc_helper.h"
771fe6b9 JG	30	#include "radeon_drm.h"
771fe6b9 JG	31	#include "radeon_reg.h"
771fe6b9 JG	32	#include "radeon.h"
	33	#include "atom.h"
	34
771fe6b9 JG	35	irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
	36	{
	37	struct drm_device dev = (struct drm_device ) arg;
	38	struct radeon_device *rdev = dev->dev_private;
	39
	40	return radeon_irq_process(rdev);
	41	}
	42
d4877cf2 AD	43	/*
	44	* Handle hotplug events outside the interrupt handler proper.
	45	*/
	46	static void radeon_hotplug_work_func(struct work_struct *work)
	47	{
	48	struct radeon_device *rdev = container_of(work, struct radeon_device,
	49	hotplug_work);
	50	struct drm_device *dev = rdev->ddev;
	51	struct drm_mode_config *mode_config = &dev->mode_config;
	52	struct drm_connector *connector;
	53
	54	if (mode_config->num_connector) {
	55	list_for_each_entry(connector, &mode_config->connector_list, head)
	56	radeon_connector_hotplug(connector);
	57	}
	58	/* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f	59	drm_helper_hpd_irq_event(dev);
d4877cf2 AD	60	}
d4877cf2 AD	61
771fe6b9 JG	62	void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
	63	{
	64	struct radeon_device *rdev = dev->dev_private;
	65	unsigned i;
	66
	67	/* Disable all interrupts */
1b37078b AD	68	for (i = 0; i < RADEON_NUM_RINGS; i++)
1b37078b AD	69	rdev->irq.sw_int[i] = false;
2031f77c	70	rdev->irq.gui_idle = false;
54bd5206	71	for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
9e7b414e	72	rdev->irq.hpd[i] = false;
54bd5206 IH	73	for (i = 0; i < RADEON_MAX_CRTCS; i++) {
54bd5206 IH	74	rdev->irq.crtc_vblank_int[i] = false;
6f34be50 AD	75	rdev->irq.pflip[i] = false;
6f34be50 AD	76	}
771fe6b9 JG	77	radeon_irq_set(rdev);
	78	/* Clear bits */
	79	radeon_irq_process(rdev);
	80	}
	81
	82	int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
	83	{
	84	struct radeon_device *rdev = dev->dev_private;
1b37078b	85	unsigned i;
771fe6b9 JG	86
771fe6b9 JG	87	dev->max_vblank_count = 0x001fffff;
1b37078b AD	88	for (i = 0; i < RADEON_NUM_RINGS; i++)
1b37078b AD	89	rdev->irq.sw_int[i] = true;
771fe6b9 JG	90	radeon_irq_set(rdev);
	91	return 0;
	92	}
	93
	94	void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
	95	{
	96	struct radeon_device *rdev = dev->dev_private;
	97	unsigned i;
	98
	99	if (rdev == NULL) {
	100	return;
	101	}
	102	/* Disable all interrupts */
1b37078b AD	103	for (i = 0; i < RADEON_NUM_RINGS; i++)
1b37078b AD	104	rdev->irq.sw_int[i] = false;
2031f77c	105	rdev->irq.gui_idle = false;
54bd5206	106	for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
003e69f9	107	rdev->irq.hpd[i] = false;
54bd5206 IH	108	for (i = 0; i < RADEON_MAX_CRTCS; i++) {
54bd5206 IH	109	rdev->irq.crtc_vblank_int[i] = false;
6f34be50 AD	110	rdev->irq.pflip[i] = false;
6f34be50 AD	111	}
771fe6b9 JG	112	radeon_irq_set(rdev);
	113	}
	114
8f6c25c5 AD	115	static bool radeon_msi_ok(struct radeon_device *rdev)
	116	{
	117	/* RV370/RV380 was first asic with MSI support */
	118	if (rdev->family < CHIP_RV380)
	119	return false;
	120
	121	/* MSIs don't work on AGP */
	122	if (rdev->flags & RADEON_IS_AGP)
	123	return false;
	124
a18cee15 AD	125	/* force MSI on */
	126	if (radeon_msi == 1)
	127	return true;
	128	else if (radeon_msi == 0)
	129	return false;
	130
b362105f AD	131	/* Quirks */
	132	/* HP RS690 only seems to work with MSIs. */
	133	if ((rdev->pdev->device == 0x791f) &&
	134	(rdev->pdev->subsystem_vendor == 0x103c) &&
	135	(rdev->pdev->subsystem_device == 0x30c2))
	136	return true;
	137
01e718ec AD	138	/* Dell RS690 only seems to work with MSIs. */
	139	if ((rdev->pdev->device == 0x791f) &&
	140	(rdev->pdev->subsystem_vendor == 0x1028) &&
	141	(rdev->pdev->subsystem_device == 0x01fd))
	142	return true;
	143
8f6c25c5 AD	144	if (rdev->flags & RADEON_IS_IGP) {
	145	/* APUs work fine with MSIs */
	146	if (rdev->family >= CHIP_PALM)
	147	return true;
	148	/* lots of IGPs have problems with MSIs */
	149	return false;
	150	}
	151
	152	return true;
	153	}
	154
771fe6b9 JG	155	int radeon_irq_kms_init(struct radeon_device *rdev)
771fe6b9 JG	156	{
29d9ebc4	157	int i;
771fe6b9 JG	158	int r = 0;
771fe6b9 JG	159
32c87fca TH	160	INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
32c87fca TH	161
1614f8b1	162	spin_lock_init(&rdev->irq.sw_lock);
29d9ebc4 MD	163	for (i = 0; i < rdev->num_crtc; i++)
29d9ebc4 MD	164	spin_lock_init(&rdev->irq.pflip_lock[i]);
9e7b414e	165	r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
771fe6b9 JG	166	if (r) {
	167	return r;
	168	}
3e5cb98d AD	169	/* enable msi */
3e5cb98d AD	170	rdev->msi_enabled = 0;
8f6c25c5 AD	171
8f6c25c5 AD	172	if (radeon_msi_ok(rdev)) {
3e5cb98d	173	int ret = pci_enable_msi(rdev->pdev);
d8f60cfc	174	if (!ret) {
3e5cb98d	175	rdev->msi_enabled = 1;
da7be684	176	dev_info(rdev->dev, "radeon: using MSI.\n");
d8f60cfc	177	}
3e5cb98d	178	}
771fe6b9	179	rdev->irq.installed = true;
003e69f9 JG	180	r = drm_irq_install(rdev->ddev);
	181	if (r) {
	182	rdev->irq.installed = false;
	183	return r;
	184	}
771fe6b9 JG	185	DRM_INFO("radeon: irq initialized.\n");
	186	return 0;
	187	}
	188
	189	void radeon_irq_kms_fini(struct radeon_device *rdev)
	190	{
003e69f9	191	drm_vblank_cleanup(rdev->ddev);
771fe6b9	192	if (rdev->irq.installed) {
771fe6b9	193	drm_irq_uninstall(rdev->ddev);
003e69f9	194	rdev->irq.installed = false;
3e5cb98d AD	195	if (rdev->msi_enabled)
3e5cb98d AD	196	pci_disable_msi(rdev->pdev);
771fe6b9	197	}
32c87fca	198	flush_work_sync(&rdev->hotplug_work);
771fe6b9	199	}
1614f8b1	200
1b37078b	201	void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring)
1614f8b1 DA	202	{
	203	unsigned long irqflags;
	204
	205	spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
1b37078b AD	206	if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount[ring] == 1)) {
1b37078b AD	207	rdev->irq.sw_int[ring] = true;
1614f8b1 DA	208	radeon_irq_set(rdev);
	209	}
	210	spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
	211	}
	212
1b37078b	213	void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
1614f8b1 DA	214	{
	215	unsigned long irqflags;
	216
	217	spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
1b37078b AD	218	BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount[ring] <= 0);
	219	if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount[ring] == 0)) {
	220	rdev->irq.sw_int[ring] = false;
1614f8b1 DA	221	radeon_irq_set(rdev);
	222	}
	223	spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
	224	}
	225
6f34be50 AD	226	void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
	227	{
	228	unsigned long irqflags;
	229
	230	if (crtc < 0 \|\| crtc >= rdev->num_crtc)
	231	return;
	232
	233	spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
	234	if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
	235	rdev->irq.pflip[crtc] = true;
	236	radeon_irq_set(rdev);
	237	}
	238	spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
	239	}
	240
	241	void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
	242	{
	243	unsigned long irqflags;
	244
	245	if (crtc < 0 \|\| crtc >= rdev->num_crtc)
	246	return;
	247
	248	spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
	249	BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
	250	if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
	251	rdev->irq.pflip[crtc] = false;
	252	radeon_irq_set(rdev);
	253	}
	254	spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
	255	}
	256