Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 | 29 | #include "radeon.h" |
760285e7 | 30 | #include <drm/radeon_drm.h> |
6759a0a7 | 31 | #include "radeon_asic.h" |
771fe6b9 | 32 | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
10ebc0bc | 35 | #include <linux/pm_runtime.h> |
78488659 | 36 | |
e28740ec OG |
37 | #include "radeon_kfd.h" |
38 | ||
78488659 | 39 | #if defined(CONFIG_VGA_SWITCHEROO) |
90c4cde9 | 40 | bool radeon_has_atpx(void); |
78488659 | 41 | #else |
90c4cde9 | 42 | static inline bool radeon_has_atpx(void) { return false; } |
78488659 AD |
43 | #endif |
44 | ||
f482a141 AD |
45 | /** |
46 | * radeon_driver_unload_kms - Main unload function for KMS. | |
47 | * | |
48 | * @dev: drm dev pointer | |
49 | * | |
50 | * This is the main unload function for KMS (all asics). | |
51 | * It calls radeon_modeset_fini() to tear down the | |
52 | * displays, and radeon_device_fini() to tear down | |
53 | * the rest of the device (CP, writeback, etc.). | |
54 | * Returns 0 on success. | |
55 | */ | |
cf0fe456 JG |
56 | int radeon_driver_unload_kms(struct drm_device *dev) |
57 | { | |
58 | struct radeon_device *rdev = dev->dev_private; | |
59 | ||
60 | if (rdev == NULL) | |
61 | return 0; | |
10ebc0bc | 62 | |
0cd9cb76 AD |
63 | if (rdev->rmmio == NULL) |
64 | goto done_free; | |
10ebc0bc DA |
65 | |
66 | pm_runtime_get_sync(dev->dev); | |
67 | ||
e28740ec OG |
68 | radeon_kfd_device_fini(rdev); |
69 | ||
c4917074 | 70 | radeon_acpi_fini(rdev); |
10ebc0bc | 71 | |
cf0fe456 JG |
72 | radeon_modeset_fini(rdev); |
73 | radeon_device_fini(rdev); | |
0cd9cb76 AD |
74 | |
75 | done_free: | |
cf0fe456 JG |
76 | kfree(rdev); |
77 | dev->dev_private = NULL; | |
78 | return 0; | |
79 | } | |
771fe6b9 | 80 | |
f482a141 AD |
81 | /** |
82 | * radeon_driver_load_kms - Main load function for KMS. | |
83 | * | |
84 | * @dev: drm dev pointer | |
85 | * @flags: device flags | |
86 | * | |
87 | * This is the main load function for KMS (all asics). | |
88 | * It calls radeon_device_init() to set up the non-display | |
89 | * parts of the chip (asic init, CP, writeback, etc.), and | |
90 | * radeon_modeset_init() to set up the display parts | |
91 | * (crtcs, encoders, hotplug detect, etc.). | |
92 | * Returns 0 on success, error on failure. | |
93 | */ | |
771fe6b9 JG |
94 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
95 | { | |
96 | struct radeon_device *rdev; | |
d7a2952f | 97 | int r, acpi_status; |
771fe6b9 JG |
98 | |
99 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
100 | if (rdev == NULL) { | |
101 | return -ENOMEM; | |
102 | } | |
103 | dev->dev_private = (void *)rdev; | |
104 | ||
105 | /* update BUS flag */ | |
8410ea3b | 106 | if (drm_pci_device_is_agp(dev)) { |
771fe6b9 | 107 | flags |= RADEON_IS_AGP; |
58b6542b | 108 | } else if (pci_is_pcie(dev->pdev)) { |
771fe6b9 JG |
109 | flags |= RADEON_IS_PCIE; |
110 | } else { | |
111 | flags |= RADEON_IS_PCI; | |
112 | } | |
113 | ||
73acacc7 AD |
114 | if ((radeon_runtime_pm != 0) && |
115 | radeon_has_atpx() && | |
116 | ((flags & RADEON_IS_IGP) == 0)) | |
90c4cde9 AD |
117 | flags |= RADEON_IS_PX; |
118 | ||
6cf8a3f5 JG |
119 | /* radeon_device_init should report only fatal error |
120 | * like memory allocation failure or iomapping failure, | |
121 | * or memory manager initialization failure, it must | |
122 | * properly initialize the GPU MC controller and permit | |
123 | * VRAM allocation | |
124 | */ | |
771fe6b9 JG |
125 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
126 | if (r) { | |
cf0fe456 JG |
127 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
128 | goto out; | |
6cf8a3f5 | 129 | } |
d7a2952f | 130 | |
6cf8a3f5 JG |
131 | /* Again modeset_init should fail only on fatal error |
132 | * otherwise it should provide enough functionalities | |
133 | * for shadowfb to run | |
134 | */ | |
135 | r = radeon_modeset_init(rdev); | |
cf0fe456 JG |
136 | if (r) |
137 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); | |
fda4b25c LT |
138 | |
139 | /* Call ACPI methods: require modeset init | |
140 | * but failure is not fatal | |
141 | */ | |
142 | if (!r) { | |
143 | acpi_status = radeon_acpi_init(rdev); | |
144 | if (acpi_status) | |
145 | dev_dbg(&dev->pdev->dev, | |
146 | "Error during ACPI methods call\n"); | |
147 | } | |
148 | ||
e28740ec OG |
149 | radeon_kfd_device_probe(rdev); |
150 | radeon_kfd_device_init(rdev); | |
151 | ||
90c4cde9 | 152 | if (radeon_is_px(dev)) { |
10ebc0bc DA |
153 | pm_runtime_use_autosuspend(dev->dev); |
154 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
155 | pm_runtime_set_active(dev->dev); | |
156 | pm_runtime_allow(dev->dev); | |
157 | pm_runtime_mark_last_busy(dev->dev); | |
158 | pm_runtime_put_autosuspend(dev->dev); | |
159 | } | |
160 | ||
cf0fe456 JG |
161 | out: |
162 | if (r) | |
163 | radeon_driver_unload_kms(dev); | |
10ebc0bc DA |
164 | |
165 | ||
cf0fe456 | 166 | return r; |
771fe6b9 JG |
167 | } |
168 | ||
f482a141 AD |
169 | /** |
170 | * radeon_set_filp_rights - Set filp right. | |
171 | * | |
172 | * @dev: drm dev pointer | |
173 | * @owner: drm file | |
174 | * @applier: drm file | |
175 | * @value: value | |
176 | * | |
177 | * Sets the filp rights for the device (all asics). | |
178 | */ | |
9eba4a93 MO |
179 | static void radeon_set_filp_rights(struct drm_device *dev, |
180 | struct drm_file **owner, | |
181 | struct drm_file *applier, | |
182 | uint32_t *value) | |
183 | { | |
184 | mutex_lock(&dev->struct_mutex); | |
185 | if (*value == 1) { | |
186 | /* wants rights */ | |
187 | if (!*owner) | |
188 | *owner = applier; | |
189 | } else if (*value == 0) { | |
190 | /* revokes rights */ | |
191 | if (*owner == applier) | |
192 | *owner = NULL; | |
193 | } | |
194 | *value = *owner == applier ? 1 : 0; | |
195 | mutex_unlock(&dev->struct_mutex); | |
196 | } | |
771fe6b9 JG |
197 | |
198 | /* | |
9eba4a93 | 199 | * Userspace get information ioctl |
771fe6b9 | 200 | */ |
f482a141 AD |
201 | /** |
202 | * radeon_info_ioctl - answer a device specific request. | |
203 | * | |
204 | * @rdev: radeon device pointer | |
205 | * @data: request object | |
206 | * @filp: drm filp | |
207 | * | |
208 | * This function is used to pass device specific parameters to the userspace | |
209 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
210 | * etc. (all asics). | |
211 | * Returns 0 on success, -EINVAL on failure. | |
212 | */ | |
5520345f | 213 | static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
771fe6b9 JG |
214 | { |
215 | struct radeon_device *rdev = dev->dev_private; | |
6759a0a7 | 216 | struct drm_radeon_info *info = data; |
bc35afdb | 217 | struct radeon_mode_info *minfo = &rdev->mode_info; |
64d7b8be JG |
218 | uint32_t *value, value_tmp, *value_ptr, value_size; |
219 | uint64_t value64; | |
bc35afdb JG |
220 | struct drm_crtc *crtc; |
221 | int i, found; | |
771fe6b9 | 222 | |
771fe6b9 | 223 | value_ptr = (uint32_t *)((unsigned long)info->value); |
64d7b8be JG |
224 | value = &value_tmp; |
225 | value_size = sizeof(uint32_t); | |
d8ab3557 | 226 | |
771fe6b9 JG |
227 | switch (info->request) { |
228 | case RADEON_INFO_DEVICE_ID: | |
ffbab09b | 229 | *value = dev->pdev->device; |
771fe6b9 JG |
230 | break; |
231 | case RADEON_INFO_NUM_GB_PIPES: | |
64d7b8be | 232 | *value = rdev->num_gb_pipes; |
771fe6b9 | 233 | break; |
f779b3e5 | 234 | case RADEON_INFO_NUM_Z_PIPES: |
64d7b8be | 235 | *value = rdev->num_z_pipes; |
f779b3e5 | 236 | break; |
733289c2 | 237 | case RADEON_INFO_ACCEL_WORKING: |
148a03bc AD |
238 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
239 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) | |
64d7b8be | 240 | *value = false; |
148a03bc | 241 | else |
64d7b8be | 242 | *value = rdev->accel_working; |
733289c2 | 243 | break; |
bc35afdb | 244 | case RADEON_INFO_CRTC_FROM_ID: |
1d6ac185 | 245 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
246 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
247 | return -EFAULT; | |
248 | } | |
bc35afdb JG |
249 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { |
250 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
64d7b8be | 251 | if (crtc && crtc->base.id == *value) { |
0baf2d8f | 252 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
64d7b8be | 253 | *value = radeon_crtc->crtc_id; |
bc35afdb JG |
254 | found = 1; |
255 | break; | |
256 | } | |
257 | } | |
258 | if (!found) { | |
64d7b8be | 259 | DRM_DEBUG_KMS("unknown crtc id %d\n", *value); |
bc35afdb JG |
260 | return -EINVAL; |
261 | } | |
262 | break; | |
148a03bc | 263 | case RADEON_INFO_ACCEL_WORKING2: |
3c64bd26 | 264 | if (rdev->family == CHIP_HAWAII) { |
9eb401af AB |
265 | if (rdev->accel_working) { |
266 | if (rdev->new_fw) | |
267 | *value = 3; | |
268 | else | |
269 | *value = 2; | |
270 | } else { | |
3c64bd26 | 271 | *value = 0; |
9eb401af | 272 | } |
3c64bd26 AD |
273 | } else { |
274 | *value = rdev->accel_working; | |
275 | } | |
148a03bc | 276 | break; |
e7aeeba6 | 277 | case RADEON_INFO_TILING_CONFIG: |
64f759cc AD |
278 | if (rdev->family >= CHIP_BONAIRE) |
279 | *value = rdev->config.cik.tile_config; | |
280 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 281 | *value = rdev->config.si.tile_config; |
c1b2f69f | 282 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 283 | *value = rdev->config.cayman.tile_config; |
fecf1d07 | 284 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 285 | *value = rdev->config.evergreen.tile_config; |
e7aeeba6 | 286 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 287 | *value = rdev->config.rv770.tile_config; |
e7aeeba6 | 288 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 289 | *value = rdev->config.r600.tile_config; |
e7aeeba6 | 290 | else { |
d9fdaafb | 291 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
e7aeeba6 AD |
292 | return -EINVAL; |
293 | } | |
b824b364 | 294 | break; |
ab9e1f59 | 295 | case RADEON_INFO_WANT_HYPERZ: |
43861f71 MO |
296 | /* The "value" here is both an input and output parameter. |
297 | * If the input value is 1, filp requests hyper-z access. | |
298 | * If the input value is 0, filp revokes its hyper-z access. | |
299 | * | |
300 | * When returning, the value is 1 if filp owns hyper-z access, | |
301 | * 0 otherwise. */ | |
1d6ac185 | 302 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
303 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
304 | return -EFAULT; | |
305 | } | |
306 | if (*value >= 2) { | |
307 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); | |
43861f71 MO |
308 | return -EINVAL; |
309 | } | |
64d7b8be | 310 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); |
9eba4a93 MO |
311 | break; |
312 | case RADEON_INFO_WANT_CMASK: | |
313 | /* The same logic as Hyper-Z. */ | |
1d6ac185 | 314 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
315 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
316 | return -EFAULT; | |
317 | } | |
318 | if (*value >= 2) { | |
319 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); | |
9eba4a93 | 320 | return -EINVAL; |
ab9e1f59 | 321 | } |
64d7b8be | 322 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); |
e7aeeba6 | 323 | break; |
58bbf018 AD |
324 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
325 | /* return clock value in KHz */ | |
454d2e2a | 326 | if (rdev->asic->get_xclk) |
64d7b8be | 327 | *value = radeon_get_xclk(rdev) * 10; |
454d2e2a | 328 | else |
64d7b8be | 329 | *value = rdev->clock.spll.reference_freq * 10; |
58bbf018 | 330 | break; |
486af189 | 331 | case RADEON_INFO_NUM_BACKENDS: |
64f759cc AD |
332 | if (rdev->family >= CHIP_BONAIRE) |
333 | *value = rdev->config.cik.max_backends_per_se * | |
334 | rdev->config.cik.max_shader_engines; | |
335 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 336 | *value = rdev->config.si.max_backends_per_se * |
c1b2f69f MD |
337 | rdev->config.si.max_shader_engines; |
338 | else if (rdev->family >= CHIP_CAYMAN) | |
64d7b8be | 339 | *value = rdev->config.cayman.max_backends_per_se * |
fecf1d07 AD |
340 | rdev->config.cayman.max_shader_engines; |
341 | else if (rdev->family >= CHIP_CEDAR) | |
64d7b8be | 342 | *value = rdev->config.evergreen.max_backends; |
486af189 | 343 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 344 | *value = rdev->config.rv770.max_backends; |
486af189 | 345 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 346 | *value = rdev->config.r600.max_backends; |
486af189 DA |
347 | else { |
348 | return -EINVAL; | |
349 | } | |
350 | break; | |
6565945b | 351 | case RADEON_INFO_NUM_TILE_PIPES: |
64f759cc AD |
352 | if (rdev->family >= CHIP_BONAIRE) |
353 | *value = rdev->config.cik.max_tile_pipes; | |
354 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 355 | *value = rdev->config.si.max_tile_pipes; |
c1b2f69f | 356 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 357 | *value = rdev->config.cayman.max_tile_pipes; |
6565945b | 358 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 359 | *value = rdev->config.evergreen.max_tile_pipes; |
6565945b | 360 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 361 | *value = rdev->config.rv770.max_tile_pipes; |
6565945b | 362 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 363 | *value = rdev->config.r600.max_tile_pipes; |
6565945b AD |
364 | else { |
365 | return -EINVAL; | |
366 | } | |
367 | break; | |
8aeb96f8 | 368 | case RADEON_INFO_FUSION_GART_WORKING: |
64d7b8be | 369 | *value = 1; |
8aeb96f8 | 370 | break; |
e55b9422 | 371 | case RADEON_INFO_BACKEND_MAP: |
64f759cc | 372 | if (rdev->family >= CHIP_BONAIRE) |
1ddce27d | 373 | *value = rdev->config.cik.backend_map; |
64f759cc | 374 | else if (rdev->family >= CHIP_TAHITI) |
64d7b8be | 375 | *value = rdev->config.si.backend_map; |
c1b2f69f | 376 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 377 | *value = rdev->config.cayman.backend_map; |
e55b9422 | 378 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 379 | *value = rdev->config.evergreen.backend_map; |
e55b9422 | 380 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 381 | *value = rdev->config.rv770.backend_map; |
e55b9422 | 382 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 383 | *value = rdev->config.r600.backend_map; |
e55b9422 AD |
384 | else { |
385 | return -EINVAL; | |
386 | } | |
387 | break; | |
721604a1 JG |
388 | case RADEON_INFO_VA_START: |
389 | /* this is where we report if vm is supported or not */ | |
390 | if (rdev->family < CHIP_CAYMAN) | |
391 | return -EINVAL; | |
64d7b8be | 392 | *value = RADEON_VA_RESERVED_SIZE; |
721604a1 JG |
393 | break; |
394 | case RADEON_INFO_IB_VM_MAX_SIZE: | |
395 | /* this is where we report if vm is supported or not */ | |
396 | if (rdev->family < CHIP_CAYMAN) | |
397 | return -EINVAL; | |
64d7b8be | 398 | *value = RADEON_IB_VM_MAX_SIZE; |
721604a1 | 399 | break; |
609c1e15 | 400 | case RADEON_INFO_MAX_PIPES: |
64f759cc AD |
401 | if (rdev->family >= CHIP_BONAIRE) |
402 | *value = rdev->config.cik.max_cu_per_sh; | |
403 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 404 | *value = rdev->config.si.max_cu_per_sh; |
c1b2f69f | 405 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 406 | *value = rdev->config.cayman.max_pipes_per_simd; |
609c1e15 | 407 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 408 | *value = rdev->config.evergreen.max_pipes; |
609c1e15 | 409 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 410 | *value = rdev->config.rv770.max_pipes; |
609c1e15 | 411 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 412 | *value = rdev->config.r600.max_pipes; |
609c1e15 TS |
413 | else { |
414 | return -EINVAL; | |
415 | } | |
416 | break; | |
64d7b8be JG |
417 | case RADEON_INFO_TIMESTAMP: |
418 | if (rdev->family < CHIP_R600) { | |
419 | DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); | |
420 | return -EINVAL; | |
421 | } | |
422 | value = (uint32_t*)&value64; | |
423 | value_size = sizeof(uint64_t); | |
424 | value64 = radeon_get_gpu_clock_counter(rdev); | |
425 | break; | |
2e1a7674 | 426 | case RADEON_INFO_MAX_SE: |
64f759cc AD |
427 | if (rdev->family >= CHIP_BONAIRE) |
428 | *value = rdev->config.cik.max_shader_engines; | |
429 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 430 | *value = rdev->config.si.max_shader_engines; |
2e1a7674 | 431 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 432 | *value = rdev->config.cayman.max_shader_engines; |
2e1a7674 | 433 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 434 | *value = rdev->config.evergreen.num_ses; |
2e1a7674 | 435 | else |
64d7b8be | 436 | *value = 1; |
2e1a7674 AD |
437 | break; |
438 | case RADEON_INFO_MAX_SH_PER_SE: | |
64f759cc AD |
439 | if (rdev->family >= CHIP_BONAIRE) |
440 | *value = rdev->config.cik.max_sh_per_se; | |
441 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 442 | *value = rdev->config.si.max_sh_per_se; |
2e1a7674 AD |
443 | else |
444 | return -EINVAL; | |
445 | break; | |
a0a53aa8 | 446 | case RADEON_INFO_FASTFB_WORKING: |
64d7b8be | 447 | *value = rdev->fastfb_working; |
a0a53aa8 | 448 | break; |
902aaef6 | 449 | case RADEON_INFO_RING_WORKING: |
1d6ac185 | 450 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
451 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
452 | return -EFAULT; | |
453 | } | |
454 | switch (*value) { | |
902aaef6 CK |
455 | case RADEON_CS_RING_GFX: |
456 | case RADEON_CS_RING_COMPUTE: | |
64d7b8be | 457 | *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; |
902aaef6 CK |
458 | break; |
459 | case RADEON_CS_RING_DMA: | |
64d7b8be JG |
460 | *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; |
461 | *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; | |
902aaef6 CK |
462 | break; |
463 | case RADEON_CS_RING_UVD: | |
64d7b8be | 464 | *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; |
902aaef6 | 465 | break; |
f7ba8b04 CK |
466 | case RADEON_CS_RING_VCE: |
467 | *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; | |
468 | break; | |
902aaef6 CK |
469 | default: |
470 | return -EINVAL; | |
471 | } | |
472 | break; | |
64d7b8be | 473 | case RADEON_INFO_SI_TILE_MODE_ARRAY: |
64f759cc | 474 | if (rdev->family >= CHIP_BONAIRE) { |
39aee490 AD |
475 | value = rdev->config.cik.tile_mode_array; |
476 | value_size = sizeof(uint32_t)*32; | |
477 | } else if (rdev->family >= CHIP_TAHITI) { | |
478 | value = rdev->config.si.tile_mode_array; | |
479 | value_size = sizeof(uint32_t)*32; | |
480 | } else { | |
481 | DRM_DEBUG_KMS("tile mode array is si+ only!\n"); | |
64f759cc AD |
482 | return -EINVAL; |
483 | } | |
64d7b8be | 484 | break; |
32f79a8a MD |
485 | case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: |
486 | if (rdev->family >= CHIP_BONAIRE) { | |
487 | value = rdev->config.cik.macrotile_mode_array; | |
488 | value_size = sizeof(uint32_t)*16; | |
489 | } else { | |
490 | DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); | |
491 | return -EINVAL; | |
492 | } | |
493 | break; | |
e5b9e750 TS |
494 | case RADEON_INFO_SI_CP_DMA_COMPUTE: |
495 | *value = 1; | |
496 | break; | |
439a1cff MO |
497 | case RADEON_INFO_SI_BACKEND_ENABLED_MASK: |
498 | if (rdev->family >= CHIP_BONAIRE) { | |
499 | *value = rdev->config.cik.backend_enable_mask; | |
500 | } else if (rdev->family >= CHIP_TAHITI) { | |
501 | *value = rdev->config.si.backend_enable_mask; | |
502 | } else { | |
503 | DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); | |
504 | } | |
505 | break; | |
f5f1f897 AD |
506 | case RADEON_INFO_MAX_SCLK: |
507 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && | |
508 | rdev->pm.dpm_enabled) | |
509 | *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
510 | else | |
511 | *value = rdev->pm.default_sclk * 10; | |
512 | break; | |
98ccc291 CK |
513 | case RADEON_INFO_VCE_FW_VERSION: |
514 | *value = rdev->vce.fw_version; | |
515 | break; | |
516 | case RADEON_INFO_VCE_FB_VERSION: | |
517 | *value = rdev->vce.fb_version; | |
518 | break; | |
67e8e3f9 MO |
519 | case RADEON_INFO_NUM_BYTES_MOVED: |
520 | value = (uint32_t*)&value64; | |
521 | value_size = sizeof(uint64_t); | |
522 | value64 = atomic64_read(&rdev->num_bytes_moved); | |
523 | break; | |
524 | case RADEON_INFO_VRAM_USAGE: | |
525 | value = (uint32_t*)&value64; | |
526 | value_size = sizeof(uint64_t); | |
527 | value64 = atomic64_read(&rdev->vram_usage); | |
528 | break; | |
529 | case RADEON_INFO_GTT_USAGE: | |
530 | value = (uint32_t*)&value64; | |
531 | value_size = sizeof(uint64_t); | |
532 | value64 = atomic64_read(&rdev->gtt_usage); | |
533 | break; | |
65fcf668 AD |
534 | case RADEON_INFO_ACTIVE_CU_COUNT: |
535 | if (rdev->family >= CHIP_BONAIRE) | |
536 | *value = rdev->config.cik.active_cus; | |
537 | else if (rdev->family >= CHIP_TAHITI) | |
538 | *value = rdev->config.si.active_cus; | |
539 | else if (rdev->family >= CHIP_CAYMAN) | |
540 | *value = rdev->config.cayman.active_simds; | |
541 | else if (rdev->family >= CHIP_CEDAR) | |
542 | *value = rdev->config.evergreen.active_simds; | |
543 | else if (rdev->family >= CHIP_RV770) | |
544 | *value = rdev->config.rv770.active_simds; | |
545 | else if (rdev->family >= CHIP_R600) | |
546 | *value = rdev->config.r600.active_simds; | |
547 | else | |
548 | *value = 1; | |
549 | break; | |
771fe6b9 | 550 | default: |
d9fdaafb | 551 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
771fe6b9 JG |
552 | return -EINVAL; |
553 | } | |
1d6ac185 | 554 | if (copy_to_user(value_ptr, (char*)value, value_size)) { |
6759a0a7 | 555 | DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); |
771fe6b9 JG |
556 | return -EFAULT; |
557 | } | |
558 | return 0; | |
559 | } | |
560 | ||
561 | ||
562 | /* | |
563 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
564 | */ | |
f482a141 AD |
565 | /** |
566 | * radeon_driver_firstopen_kms - drm callback for last close | |
567 | * | |
568 | * @dev: drm dev pointer | |
569 | * | |
570 | * Switch vga switcheroo state after last close (all asics). | |
571 | */ | |
771fe6b9 JG |
572 | void radeon_driver_lastclose_kms(struct drm_device *dev) |
573 | { | |
6a9ee8af | 574 | vga_switcheroo_process_delayed_switch(); |
771fe6b9 JG |
575 | } |
576 | ||
f482a141 AD |
577 | /** |
578 | * radeon_driver_open_kms - drm callback for open | |
579 | * | |
580 | * @dev: drm dev pointer | |
581 | * @file_priv: drm file | |
582 | * | |
583 | * On device open, init vm on cayman+ (all asics). | |
584 | * Returns 0 on success, error on failure. | |
585 | */ | |
771fe6b9 JG |
586 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) |
587 | { | |
721604a1 | 588 | struct radeon_device *rdev = dev->dev_private; |
10ebc0bc | 589 | int r; |
721604a1 JG |
590 | |
591 | file_priv->driver_priv = NULL; | |
592 | ||
10ebc0bc DA |
593 | r = pm_runtime_get_sync(dev->dev); |
594 | if (r < 0) | |
595 | return r; | |
596 | ||
721604a1 JG |
597 | /* new gpu have virtual address space support */ |
598 | if (rdev->family >= CHIP_CAYMAN) { | |
599 | struct radeon_fpriv *fpriv; | |
cc9e67e3 | 600 | struct radeon_vm *vm; |
721604a1 JG |
601 | int r; |
602 | ||
603 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
604 | if (unlikely(!fpriv)) { | |
605 | return -ENOMEM; | |
606 | } | |
607 | ||
24f47acc | 608 | if (rdev->accel_working) { |
544143f9 AD |
609 | vm = &fpriv->vm; |
610 | r = radeon_vm_init(rdev, vm); | |
611 | if (r) { | |
612 | kfree(fpriv); | |
613 | return r; | |
614 | } | |
615 | ||
24f47acc JG |
616 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); |
617 | if (r) { | |
cc9e67e3 | 618 | radeon_vm_fini(rdev, vm); |
24f47acc JG |
619 | kfree(fpriv); |
620 | return r; | |
621 | } | |
f1e3dc70 | 622 | |
24f47acc JG |
623 | /* map the ib pool buffer read only into |
624 | * virtual address space */ | |
cc9e67e3 CK |
625 | vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, |
626 | rdev->ring_tmp_bo.bo); | |
627 | r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, | |
628 | RADEON_VA_IB_OFFSET, | |
24f47acc JG |
629 | RADEON_VM_PAGE_READABLE | |
630 | RADEON_VM_PAGE_SNOOPED); | |
24f47acc | 631 | if (r) { |
cc9e67e3 | 632 | radeon_vm_fini(rdev, vm); |
24f47acc JG |
633 | kfree(fpriv); |
634 | return r; | |
635 | } | |
721604a1 | 636 | } |
721604a1 JG |
637 | file_priv->driver_priv = fpriv; |
638 | } | |
10ebc0bc DA |
639 | |
640 | pm_runtime_mark_last_busy(dev->dev); | |
641 | pm_runtime_put_autosuspend(dev->dev); | |
771fe6b9 JG |
642 | return 0; |
643 | } | |
644 | ||
f482a141 AD |
645 | /** |
646 | * radeon_driver_postclose_kms - drm callback for post close | |
647 | * | |
648 | * @dev: drm dev pointer | |
649 | * @file_priv: drm file | |
650 | * | |
651 | * On device post close, tear down vm on cayman+ (all asics). | |
652 | */ | |
771fe6b9 JG |
653 | void radeon_driver_postclose_kms(struct drm_device *dev, |
654 | struct drm_file *file_priv) | |
655 | { | |
721604a1 JG |
656 | struct radeon_device *rdev = dev->dev_private; |
657 | ||
658 | /* new gpu have virtual address space support */ | |
659 | if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { | |
660 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
cc9e67e3 | 661 | struct radeon_vm *vm = &fpriv->vm; |
d72d43cf CK |
662 | int r; |
663 | ||
24f47acc JG |
664 | if (rdev->accel_working) { |
665 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); | |
666 | if (!r) { | |
cc9e67e3 CK |
667 | if (vm->ib_bo_va) |
668 | radeon_vm_bo_rmv(rdev, vm->ib_bo_va); | |
24f47acc JG |
669 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); |
670 | } | |
544143f9 | 671 | radeon_vm_fini(rdev, vm); |
d72d43cf | 672 | } |
721604a1 | 673 | |
721604a1 JG |
674 | kfree(fpriv); |
675 | file_priv->driver_priv = NULL; | |
676 | } | |
771fe6b9 JG |
677 | } |
678 | ||
f482a141 AD |
679 | /** |
680 | * radeon_driver_preclose_kms - drm callback for pre close | |
681 | * | |
682 | * @dev: drm dev pointer | |
683 | * @file_priv: drm file | |
684 | * | |
685 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
686 | * (all asics). | |
687 | */ | |
771fe6b9 JG |
688 | void radeon_driver_preclose_kms(struct drm_device *dev, |
689 | struct drm_file *file_priv) | |
690 | { | |
ab9e1f59 DA |
691 | struct radeon_device *rdev = dev->dev_private; |
692 | if (rdev->hyperz_filp == file_priv) | |
693 | rdev->hyperz_filp = NULL; | |
dca0d612 MO |
694 | if (rdev->cmask_filp == file_priv) |
695 | rdev->cmask_filp = NULL; | |
f2ba57b5 | 696 | radeon_uvd_free_handles(rdev, file_priv); |
d93f7937 | 697 | radeon_vce_free_handles(rdev, file_priv); |
771fe6b9 JG |
698 | } |
699 | ||
771fe6b9 JG |
700 | /* |
701 | * VBlank related functions. | |
702 | */ | |
f482a141 AD |
703 | /** |
704 | * radeon_get_vblank_counter_kms - get frame count | |
705 | * | |
706 | * @dev: drm dev pointer | |
707 | * @crtc: crtc to get the frame count from | |
708 | * | |
709 | * Gets the frame count on the requested crtc (all asics). | |
710 | * Returns frame count on success, -EINVAL on failure. | |
711 | */ | |
771fe6b9 JG |
712 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) |
713 | { | |
7ed220d7 MD |
714 | struct radeon_device *rdev = dev->dev_private; |
715 | ||
9c950a43 | 716 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
717 | DRM_ERROR("Invalid crtc %d\n", crtc); |
718 | return -EINVAL; | |
719 | } | |
720 | ||
721 | return radeon_get_vblank_counter(rdev, crtc); | |
771fe6b9 JG |
722 | } |
723 | ||
f482a141 AD |
724 | /** |
725 | * radeon_enable_vblank_kms - enable vblank interrupt | |
726 | * | |
727 | * @dev: drm dev pointer | |
728 | * @crtc: crtc to enable vblank interrupt for | |
729 | * | |
730 | * Enable the interrupt on the requested crtc (all asics). | |
731 | * Returns 0 on success, -EINVAL on failure. | |
732 | */ | |
771fe6b9 JG |
733 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
734 | { | |
7ed220d7 | 735 | struct radeon_device *rdev = dev->dev_private; |
fb98257a CK |
736 | unsigned long irqflags; |
737 | int r; | |
7ed220d7 | 738 | |
9c950a43 | 739 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
740 | DRM_ERROR("Invalid crtc %d\n", crtc); |
741 | return -EINVAL; | |
742 | } | |
743 | ||
fb98257a | 744 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 745 | rdev->irq.crtc_vblank_int[crtc] = true; |
fb98257a CK |
746 | r = radeon_irq_set(rdev); |
747 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
748 | return r; | |
771fe6b9 JG |
749 | } |
750 | ||
f482a141 AD |
751 | /** |
752 | * radeon_disable_vblank_kms - disable vblank interrupt | |
753 | * | |
754 | * @dev: drm dev pointer | |
755 | * @crtc: crtc to disable vblank interrupt for | |
756 | * | |
757 | * Disable the interrupt on the requested crtc (all asics). | |
758 | */ | |
771fe6b9 JG |
759 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
760 | { | |
7ed220d7 | 761 | struct radeon_device *rdev = dev->dev_private; |
fb98257a | 762 | unsigned long irqflags; |
7ed220d7 | 763 | |
9c950a43 | 764 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
765 | DRM_ERROR("Invalid crtc %d\n", crtc); |
766 | return; | |
767 | } | |
768 | ||
fb98257a | 769 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 770 | rdev->irq.crtc_vblank_int[crtc] = false; |
7ed220d7 | 771 | radeon_irq_set(rdev); |
fb98257a | 772 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
771fe6b9 JG |
773 | } |
774 | ||
f482a141 AD |
775 | /** |
776 | * radeon_get_vblank_timestamp_kms - get vblank timestamp | |
777 | * | |
778 | * @dev: drm dev pointer | |
779 | * @crtc: crtc to get the timestamp for | |
780 | * @max_error: max error | |
781 | * @vblank_time: time value | |
782 | * @flags: flags passed to the driver | |
783 | * | |
784 | * Gets the timestamp on the requested crtc based on the | |
785 | * scanout position. (all asics). | |
786 | * Returns postive status flags on success, negative error on failure. | |
787 | */ | |
f5a80209 MK |
788 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
789 | int *max_error, | |
790 | struct timeval *vblank_time, | |
791 | unsigned flags) | |
792 | { | |
793 | struct drm_crtc *drmcrtc; | |
794 | struct radeon_device *rdev = dev->dev_private; | |
795 | ||
796 | if (crtc < 0 || crtc >= dev->num_crtcs) { | |
797 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
798 | return -EINVAL; | |
799 | } | |
800 | ||
801 | /* Get associated drm_crtc: */ | |
802 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; | |
f5475cc4 PM |
803 | if (!drmcrtc) |
804 | return -EINVAL; | |
f5a80209 MK |
805 | |
806 | /* Helper routine in DRM core does all the work: */ | |
807 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, | |
808 | vblank_time, flags, | |
7da903ef | 809 | drmcrtc, &drmcrtc->hwmode); |
f5a80209 | 810 | } |
771fe6b9 | 811 | |
771fe6b9 | 812 | #define KMS_INVALID_IOCTL(name) \ |
f6e2e407 RK |
813 | static int name(struct drm_device *dev, void *data, struct drm_file \ |
814 | *file_priv) \ | |
771fe6b9 JG |
815 | { \ |
816 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ | |
817 | return -EINVAL; \ | |
818 | } | |
819 | ||
820 | /* | |
821 | * All these ioctls are invalid in kms world. | |
822 | */ | |
823 | KMS_INVALID_IOCTL(radeon_cp_init_kms) | |
824 | KMS_INVALID_IOCTL(radeon_cp_start_kms) | |
825 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) | |
826 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) | |
827 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) | |
828 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) | |
829 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) | |
830 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) | |
831 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) | |
832 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) | |
833 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) | |
834 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) | |
835 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) | |
836 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) | |
837 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) | |
838 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) | |
839 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) | |
840 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) | |
841 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) | |
842 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) | |
843 | KMS_INVALID_IOCTL(radeon_mem_free_kms) | |
844 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) | |
845 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) | |
846 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) | |
847 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) | |
848 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) | |
849 | KMS_INVALID_IOCTL(radeon_surface_free_kms) | |
850 | ||
851 | ||
baa70943 | 852 | const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
1b2f1489 DA |
853 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
854 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
855 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
856 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
857 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), | |
858 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), | |
859 | DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), | |
860 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), | |
861 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), | |
862 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), | |
863 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), | |
864 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), | |
865 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), | |
866 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), | |
867 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
868 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), | |
869 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), | |
870 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), | |
871 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), | |
872 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), | |
873 | DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), | |
874 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
875 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), | |
876 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), | |
877 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), | |
878 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), | |
879 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), | |
771fe6b9 | 880 | /* KMS */ |
f33bcab9 CK |
881 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
882 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
883 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
884 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
885 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), |
886 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
f33bcab9 CK |
887 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
888 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
889 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
890 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
891 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
892 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
893 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
bda72d58 | 894 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
f72a113a | 895 | DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
771fe6b9 | 896 | }; |
f95aeb17 | 897 | int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); |