Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 | 29 | #include "radeon.h" |
760285e7 | 30 | #include <drm/radeon_drm.h> |
6759a0a7 | 31 | #include "radeon_asic.h" |
771fe6b9 | 32 | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
10ebc0bc | 35 | #include <linux/pm_runtime.h> |
78488659 AD |
36 | |
37 | #if defined(CONFIG_VGA_SWITCHEROO) | |
90c4cde9 | 38 | bool radeon_has_atpx(void); |
78488659 | 39 | #else |
90c4cde9 | 40 | static inline bool radeon_has_atpx(void) { return false; } |
78488659 AD |
41 | #endif |
42 | ||
f482a141 AD |
43 | /** |
44 | * radeon_driver_unload_kms - Main unload function for KMS. | |
45 | * | |
46 | * @dev: drm dev pointer | |
47 | * | |
48 | * This is the main unload function for KMS (all asics). | |
49 | * It calls radeon_modeset_fini() to tear down the | |
50 | * displays, and radeon_device_fini() to tear down | |
51 | * the rest of the device (CP, writeback, etc.). | |
52 | * Returns 0 on success. | |
53 | */ | |
cf0fe456 JG |
54 | int radeon_driver_unload_kms(struct drm_device *dev) |
55 | { | |
56 | struct radeon_device *rdev = dev->dev_private; | |
57 | ||
58 | if (rdev == NULL) | |
59 | return 0; | |
10ebc0bc | 60 | |
0cd9cb76 AD |
61 | if (rdev->rmmio == NULL) |
62 | goto done_free; | |
10ebc0bc DA |
63 | |
64 | pm_runtime_get_sync(dev->dev); | |
65 | ||
c4917074 | 66 | radeon_acpi_fini(rdev); |
10ebc0bc | 67 | |
cf0fe456 JG |
68 | radeon_modeset_fini(rdev); |
69 | radeon_device_fini(rdev); | |
0cd9cb76 AD |
70 | |
71 | done_free: | |
cf0fe456 JG |
72 | kfree(rdev); |
73 | dev->dev_private = NULL; | |
74 | return 0; | |
75 | } | |
771fe6b9 | 76 | |
f482a141 AD |
77 | /** |
78 | * radeon_driver_load_kms - Main load function for KMS. | |
79 | * | |
80 | * @dev: drm dev pointer | |
81 | * @flags: device flags | |
82 | * | |
83 | * This is the main load function for KMS (all asics). | |
84 | * It calls radeon_device_init() to set up the non-display | |
85 | * parts of the chip (asic init, CP, writeback, etc.), and | |
86 | * radeon_modeset_init() to set up the display parts | |
87 | * (crtcs, encoders, hotplug detect, etc.). | |
88 | * Returns 0 on success, error on failure. | |
89 | */ | |
771fe6b9 JG |
90 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
91 | { | |
92 | struct radeon_device *rdev; | |
d7a2952f | 93 | int r, acpi_status; |
771fe6b9 JG |
94 | |
95 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
96 | if (rdev == NULL) { | |
97 | return -ENOMEM; | |
98 | } | |
99 | dev->dev_private = (void *)rdev; | |
100 | ||
101 | /* update BUS flag */ | |
8410ea3b | 102 | if (drm_pci_device_is_agp(dev)) { |
771fe6b9 | 103 | flags |= RADEON_IS_AGP; |
58b6542b | 104 | } else if (pci_is_pcie(dev->pdev)) { |
771fe6b9 JG |
105 | flags |= RADEON_IS_PCIE; |
106 | } else { | |
107 | flags |= RADEON_IS_PCI; | |
108 | } | |
109 | ||
90c4cde9 AD |
110 | if (radeon_runtime_pm == 1) |
111 | flags |= RADEON_IS_PX; | |
112 | else if ((radeon_runtime_pm == -1) && | |
113 | radeon_has_atpx() && | |
114 | ((flags & RADEON_IS_IGP) == 0)) | |
115 | flags |= RADEON_IS_PX; | |
116 | ||
6cf8a3f5 JG |
117 | /* radeon_device_init should report only fatal error |
118 | * like memory allocation failure or iomapping failure, | |
119 | * or memory manager initialization failure, it must | |
120 | * properly initialize the GPU MC controller and permit | |
121 | * VRAM allocation | |
122 | */ | |
771fe6b9 JG |
123 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
124 | if (r) { | |
cf0fe456 JG |
125 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
126 | goto out; | |
6cf8a3f5 | 127 | } |
d7a2952f | 128 | |
6cf8a3f5 JG |
129 | /* Again modeset_init should fail only on fatal error |
130 | * otherwise it should provide enough functionalities | |
131 | * for shadowfb to run | |
132 | */ | |
133 | r = radeon_modeset_init(rdev); | |
cf0fe456 JG |
134 | if (r) |
135 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); | |
fda4b25c LT |
136 | |
137 | /* Call ACPI methods: require modeset init | |
138 | * but failure is not fatal | |
139 | */ | |
140 | if (!r) { | |
141 | acpi_status = radeon_acpi_init(rdev); | |
142 | if (acpi_status) | |
143 | dev_dbg(&dev->pdev->dev, | |
144 | "Error during ACPI methods call\n"); | |
145 | } | |
146 | ||
90c4cde9 | 147 | if (radeon_is_px(dev)) { |
10ebc0bc DA |
148 | pm_runtime_use_autosuspend(dev->dev); |
149 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
150 | pm_runtime_set_active(dev->dev); | |
151 | pm_runtime_allow(dev->dev); | |
152 | pm_runtime_mark_last_busy(dev->dev); | |
153 | pm_runtime_put_autosuspend(dev->dev); | |
154 | } | |
155 | ||
cf0fe456 JG |
156 | out: |
157 | if (r) | |
158 | radeon_driver_unload_kms(dev); | |
10ebc0bc DA |
159 | |
160 | ||
cf0fe456 | 161 | return r; |
771fe6b9 JG |
162 | } |
163 | ||
f482a141 AD |
164 | /** |
165 | * radeon_set_filp_rights - Set filp right. | |
166 | * | |
167 | * @dev: drm dev pointer | |
168 | * @owner: drm file | |
169 | * @applier: drm file | |
170 | * @value: value | |
171 | * | |
172 | * Sets the filp rights for the device (all asics). | |
173 | */ | |
9eba4a93 MO |
174 | static void radeon_set_filp_rights(struct drm_device *dev, |
175 | struct drm_file **owner, | |
176 | struct drm_file *applier, | |
177 | uint32_t *value) | |
178 | { | |
179 | mutex_lock(&dev->struct_mutex); | |
180 | if (*value == 1) { | |
181 | /* wants rights */ | |
182 | if (!*owner) | |
183 | *owner = applier; | |
184 | } else if (*value == 0) { | |
185 | /* revokes rights */ | |
186 | if (*owner == applier) | |
187 | *owner = NULL; | |
188 | } | |
189 | *value = *owner == applier ? 1 : 0; | |
190 | mutex_unlock(&dev->struct_mutex); | |
191 | } | |
771fe6b9 JG |
192 | |
193 | /* | |
9eba4a93 | 194 | * Userspace get information ioctl |
771fe6b9 | 195 | */ |
f482a141 AD |
196 | /** |
197 | * radeon_info_ioctl - answer a device specific request. | |
198 | * | |
199 | * @rdev: radeon device pointer | |
200 | * @data: request object | |
201 | * @filp: drm filp | |
202 | * | |
203 | * This function is used to pass device specific parameters to the userspace | |
204 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
205 | * etc. (all asics). | |
206 | * Returns 0 on success, -EINVAL on failure. | |
207 | */ | |
5520345f | 208 | static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
771fe6b9 JG |
209 | { |
210 | struct radeon_device *rdev = dev->dev_private; | |
6759a0a7 | 211 | struct drm_radeon_info *info = data; |
bc35afdb | 212 | struct radeon_mode_info *minfo = &rdev->mode_info; |
64d7b8be JG |
213 | uint32_t *value, value_tmp, *value_ptr, value_size; |
214 | uint64_t value64; | |
bc35afdb JG |
215 | struct drm_crtc *crtc; |
216 | int i, found; | |
771fe6b9 | 217 | |
771fe6b9 | 218 | value_ptr = (uint32_t *)((unsigned long)info->value); |
64d7b8be JG |
219 | value = &value_tmp; |
220 | value_size = sizeof(uint32_t); | |
d8ab3557 | 221 | |
771fe6b9 JG |
222 | switch (info->request) { |
223 | case RADEON_INFO_DEVICE_ID: | |
ffbab09b | 224 | *value = dev->pdev->device; |
771fe6b9 JG |
225 | break; |
226 | case RADEON_INFO_NUM_GB_PIPES: | |
64d7b8be | 227 | *value = rdev->num_gb_pipes; |
771fe6b9 | 228 | break; |
f779b3e5 | 229 | case RADEON_INFO_NUM_Z_PIPES: |
64d7b8be | 230 | *value = rdev->num_z_pipes; |
f779b3e5 | 231 | break; |
733289c2 | 232 | case RADEON_INFO_ACCEL_WORKING: |
148a03bc AD |
233 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
234 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) | |
64d7b8be | 235 | *value = false; |
148a03bc | 236 | else |
64d7b8be | 237 | *value = rdev->accel_working; |
733289c2 | 238 | break; |
bc35afdb | 239 | case RADEON_INFO_CRTC_FROM_ID: |
1d6ac185 | 240 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
241 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
242 | return -EFAULT; | |
243 | } | |
bc35afdb JG |
244 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { |
245 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
64d7b8be | 246 | if (crtc && crtc->base.id == *value) { |
0baf2d8f | 247 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
64d7b8be | 248 | *value = radeon_crtc->crtc_id; |
bc35afdb JG |
249 | found = 1; |
250 | break; | |
251 | } | |
252 | } | |
253 | if (!found) { | |
64d7b8be | 254 | DRM_DEBUG_KMS("unknown crtc id %d\n", *value); |
bc35afdb JG |
255 | return -EINVAL; |
256 | } | |
257 | break; | |
148a03bc | 258 | case RADEON_INFO_ACCEL_WORKING2: |
64d7b8be | 259 | *value = rdev->accel_working; |
148a03bc | 260 | break; |
e7aeeba6 | 261 | case RADEON_INFO_TILING_CONFIG: |
64f759cc AD |
262 | if (rdev->family >= CHIP_BONAIRE) |
263 | *value = rdev->config.cik.tile_config; | |
264 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 265 | *value = rdev->config.si.tile_config; |
c1b2f69f | 266 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 267 | *value = rdev->config.cayman.tile_config; |
fecf1d07 | 268 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 269 | *value = rdev->config.evergreen.tile_config; |
e7aeeba6 | 270 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 271 | *value = rdev->config.rv770.tile_config; |
e7aeeba6 | 272 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 273 | *value = rdev->config.r600.tile_config; |
e7aeeba6 | 274 | else { |
d9fdaafb | 275 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
e7aeeba6 AD |
276 | return -EINVAL; |
277 | } | |
b824b364 | 278 | break; |
ab9e1f59 | 279 | case RADEON_INFO_WANT_HYPERZ: |
43861f71 MO |
280 | /* The "value" here is both an input and output parameter. |
281 | * If the input value is 1, filp requests hyper-z access. | |
282 | * If the input value is 0, filp revokes its hyper-z access. | |
283 | * | |
284 | * When returning, the value is 1 if filp owns hyper-z access, | |
285 | * 0 otherwise. */ | |
1d6ac185 | 286 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
287 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
288 | return -EFAULT; | |
289 | } | |
290 | if (*value >= 2) { | |
291 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); | |
43861f71 MO |
292 | return -EINVAL; |
293 | } | |
64d7b8be | 294 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); |
9eba4a93 MO |
295 | break; |
296 | case RADEON_INFO_WANT_CMASK: | |
297 | /* The same logic as Hyper-Z. */ | |
1d6ac185 | 298 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
299 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
300 | return -EFAULT; | |
301 | } | |
302 | if (*value >= 2) { | |
303 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); | |
9eba4a93 | 304 | return -EINVAL; |
ab9e1f59 | 305 | } |
64d7b8be | 306 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); |
e7aeeba6 | 307 | break; |
58bbf018 AD |
308 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
309 | /* return clock value in KHz */ | |
454d2e2a | 310 | if (rdev->asic->get_xclk) |
64d7b8be | 311 | *value = radeon_get_xclk(rdev) * 10; |
454d2e2a | 312 | else |
64d7b8be | 313 | *value = rdev->clock.spll.reference_freq * 10; |
58bbf018 | 314 | break; |
486af189 | 315 | case RADEON_INFO_NUM_BACKENDS: |
64f759cc AD |
316 | if (rdev->family >= CHIP_BONAIRE) |
317 | *value = rdev->config.cik.max_backends_per_se * | |
318 | rdev->config.cik.max_shader_engines; | |
319 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 320 | *value = rdev->config.si.max_backends_per_se * |
c1b2f69f MD |
321 | rdev->config.si.max_shader_engines; |
322 | else if (rdev->family >= CHIP_CAYMAN) | |
64d7b8be | 323 | *value = rdev->config.cayman.max_backends_per_se * |
fecf1d07 AD |
324 | rdev->config.cayman.max_shader_engines; |
325 | else if (rdev->family >= CHIP_CEDAR) | |
64d7b8be | 326 | *value = rdev->config.evergreen.max_backends; |
486af189 | 327 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 328 | *value = rdev->config.rv770.max_backends; |
486af189 | 329 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 330 | *value = rdev->config.r600.max_backends; |
486af189 DA |
331 | else { |
332 | return -EINVAL; | |
333 | } | |
334 | break; | |
6565945b | 335 | case RADEON_INFO_NUM_TILE_PIPES: |
64f759cc AD |
336 | if (rdev->family >= CHIP_BONAIRE) |
337 | *value = rdev->config.cik.max_tile_pipes; | |
338 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 339 | *value = rdev->config.si.max_tile_pipes; |
c1b2f69f | 340 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 341 | *value = rdev->config.cayman.max_tile_pipes; |
6565945b | 342 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 343 | *value = rdev->config.evergreen.max_tile_pipes; |
6565945b | 344 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 345 | *value = rdev->config.rv770.max_tile_pipes; |
6565945b | 346 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 347 | *value = rdev->config.r600.max_tile_pipes; |
6565945b AD |
348 | else { |
349 | return -EINVAL; | |
350 | } | |
351 | break; | |
8aeb96f8 | 352 | case RADEON_INFO_FUSION_GART_WORKING: |
64d7b8be | 353 | *value = 1; |
8aeb96f8 | 354 | break; |
e55b9422 | 355 | case RADEON_INFO_BACKEND_MAP: |
64f759cc | 356 | if (rdev->family >= CHIP_BONAIRE) |
1ddce27d | 357 | *value = rdev->config.cik.backend_map; |
64f759cc | 358 | else if (rdev->family >= CHIP_TAHITI) |
64d7b8be | 359 | *value = rdev->config.si.backend_map; |
c1b2f69f | 360 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 361 | *value = rdev->config.cayman.backend_map; |
e55b9422 | 362 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 363 | *value = rdev->config.evergreen.backend_map; |
e55b9422 | 364 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 365 | *value = rdev->config.rv770.backend_map; |
e55b9422 | 366 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 367 | *value = rdev->config.r600.backend_map; |
e55b9422 AD |
368 | else { |
369 | return -EINVAL; | |
370 | } | |
371 | break; | |
721604a1 JG |
372 | case RADEON_INFO_VA_START: |
373 | /* this is where we report if vm is supported or not */ | |
374 | if (rdev->family < CHIP_CAYMAN) | |
375 | return -EINVAL; | |
64d7b8be | 376 | *value = RADEON_VA_RESERVED_SIZE; |
721604a1 JG |
377 | break; |
378 | case RADEON_INFO_IB_VM_MAX_SIZE: | |
379 | /* this is where we report if vm is supported or not */ | |
380 | if (rdev->family < CHIP_CAYMAN) | |
381 | return -EINVAL; | |
64d7b8be | 382 | *value = RADEON_IB_VM_MAX_SIZE; |
721604a1 | 383 | break; |
609c1e15 | 384 | case RADEON_INFO_MAX_PIPES: |
64f759cc AD |
385 | if (rdev->family >= CHIP_BONAIRE) |
386 | *value = rdev->config.cik.max_cu_per_sh; | |
387 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 388 | *value = rdev->config.si.max_cu_per_sh; |
c1b2f69f | 389 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 390 | *value = rdev->config.cayman.max_pipes_per_simd; |
609c1e15 | 391 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 392 | *value = rdev->config.evergreen.max_pipes; |
609c1e15 | 393 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 394 | *value = rdev->config.rv770.max_pipes; |
609c1e15 | 395 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 396 | *value = rdev->config.r600.max_pipes; |
609c1e15 TS |
397 | else { |
398 | return -EINVAL; | |
399 | } | |
400 | break; | |
64d7b8be JG |
401 | case RADEON_INFO_TIMESTAMP: |
402 | if (rdev->family < CHIP_R600) { | |
403 | DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); | |
404 | return -EINVAL; | |
405 | } | |
406 | value = (uint32_t*)&value64; | |
407 | value_size = sizeof(uint64_t); | |
408 | value64 = radeon_get_gpu_clock_counter(rdev); | |
409 | break; | |
2e1a7674 | 410 | case RADEON_INFO_MAX_SE: |
64f759cc AD |
411 | if (rdev->family >= CHIP_BONAIRE) |
412 | *value = rdev->config.cik.max_shader_engines; | |
413 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 414 | *value = rdev->config.si.max_shader_engines; |
2e1a7674 | 415 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 416 | *value = rdev->config.cayman.max_shader_engines; |
2e1a7674 | 417 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 418 | *value = rdev->config.evergreen.num_ses; |
2e1a7674 | 419 | else |
64d7b8be | 420 | *value = 1; |
2e1a7674 AD |
421 | break; |
422 | case RADEON_INFO_MAX_SH_PER_SE: | |
64f759cc AD |
423 | if (rdev->family >= CHIP_BONAIRE) |
424 | *value = rdev->config.cik.max_sh_per_se; | |
425 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 426 | *value = rdev->config.si.max_sh_per_se; |
2e1a7674 AD |
427 | else |
428 | return -EINVAL; | |
429 | break; | |
a0a53aa8 | 430 | case RADEON_INFO_FASTFB_WORKING: |
64d7b8be | 431 | *value = rdev->fastfb_working; |
a0a53aa8 | 432 | break; |
902aaef6 | 433 | case RADEON_INFO_RING_WORKING: |
1d6ac185 | 434 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
435 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
436 | return -EFAULT; | |
437 | } | |
438 | switch (*value) { | |
902aaef6 CK |
439 | case RADEON_CS_RING_GFX: |
440 | case RADEON_CS_RING_COMPUTE: | |
64d7b8be | 441 | *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; |
902aaef6 CK |
442 | break; |
443 | case RADEON_CS_RING_DMA: | |
64d7b8be JG |
444 | *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; |
445 | *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; | |
902aaef6 CK |
446 | break; |
447 | case RADEON_CS_RING_UVD: | |
64d7b8be | 448 | *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; |
902aaef6 | 449 | break; |
f7ba8b04 CK |
450 | case RADEON_CS_RING_VCE: |
451 | *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; | |
452 | break; | |
902aaef6 CK |
453 | default: |
454 | return -EINVAL; | |
455 | } | |
456 | break; | |
64d7b8be | 457 | case RADEON_INFO_SI_TILE_MODE_ARRAY: |
64f759cc | 458 | if (rdev->family >= CHIP_BONAIRE) { |
39aee490 AD |
459 | value = rdev->config.cik.tile_mode_array; |
460 | value_size = sizeof(uint32_t)*32; | |
461 | } else if (rdev->family >= CHIP_TAHITI) { | |
462 | value = rdev->config.si.tile_mode_array; | |
463 | value_size = sizeof(uint32_t)*32; | |
464 | } else { | |
465 | DRM_DEBUG_KMS("tile mode array is si+ only!\n"); | |
64f759cc AD |
466 | return -EINVAL; |
467 | } | |
64d7b8be | 468 | break; |
32f79a8a MD |
469 | case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: |
470 | if (rdev->family >= CHIP_BONAIRE) { | |
471 | value = rdev->config.cik.macrotile_mode_array; | |
472 | value_size = sizeof(uint32_t)*16; | |
473 | } else { | |
474 | DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); | |
475 | return -EINVAL; | |
476 | } | |
477 | break; | |
e5b9e750 TS |
478 | case RADEON_INFO_SI_CP_DMA_COMPUTE: |
479 | *value = 1; | |
480 | break; | |
439a1cff MO |
481 | case RADEON_INFO_SI_BACKEND_ENABLED_MASK: |
482 | if (rdev->family >= CHIP_BONAIRE) { | |
483 | *value = rdev->config.cik.backend_enable_mask; | |
484 | } else if (rdev->family >= CHIP_TAHITI) { | |
485 | *value = rdev->config.si.backend_enable_mask; | |
486 | } else { | |
487 | DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); | |
488 | } | |
489 | break; | |
f5f1f897 AD |
490 | case RADEON_INFO_MAX_SCLK: |
491 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && | |
492 | rdev->pm.dpm_enabled) | |
493 | *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
494 | else | |
495 | *value = rdev->pm.default_sclk * 10; | |
496 | break; | |
98ccc291 CK |
497 | case RADEON_INFO_VCE_FW_VERSION: |
498 | *value = rdev->vce.fw_version; | |
499 | break; | |
500 | case RADEON_INFO_VCE_FB_VERSION: | |
501 | *value = rdev->vce.fb_version; | |
502 | break; | |
67e8e3f9 MO |
503 | case RADEON_INFO_NUM_BYTES_MOVED: |
504 | value = (uint32_t*)&value64; | |
505 | value_size = sizeof(uint64_t); | |
506 | value64 = atomic64_read(&rdev->num_bytes_moved); | |
507 | break; | |
508 | case RADEON_INFO_VRAM_USAGE: | |
509 | value = (uint32_t*)&value64; | |
510 | value_size = sizeof(uint64_t); | |
511 | value64 = atomic64_read(&rdev->vram_usage); | |
512 | break; | |
513 | case RADEON_INFO_GTT_USAGE: | |
514 | value = (uint32_t*)&value64; | |
515 | value_size = sizeof(uint64_t); | |
516 | value64 = atomic64_read(&rdev->gtt_usage); | |
517 | break; | |
771fe6b9 | 518 | default: |
d9fdaafb | 519 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
771fe6b9 JG |
520 | return -EINVAL; |
521 | } | |
1d6ac185 | 522 | if (copy_to_user(value_ptr, (char*)value, value_size)) { |
6759a0a7 | 523 | DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); |
771fe6b9 JG |
524 | return -EFAULT; |
525 | } | |
526 | return 0; | |
527 | } | |
528 | ||
529 | ||
530 | /* | |
531 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
532 | */ | |
f482a141 AD |
533 | /** |
534 | * radeon_driver_firstopen_kms - drm callback for last close | |
535 | * | |
536 | * @dev: drm dev pointer | |
537 | * | |
538 | * Switch vga switcheroo state after last close (all asics). | |
539 | */ | |
771fe6b9 JG |
540 | void radeon_driver_lastclose_kms(struct drm_device *dev) |
541 | { | |
6a9ee8af | 542 | vga_switcheroo_process_delayed_switch(); |
771fe6b9 JG |
543 | } |
544 | ||
f482a141 AD |
545 | /** |
546 | * radeon_driver_open_kms - drm callback for open | |
547 | * | |
548 | * @dev: drm dev pointer | |
549 | * @file_priv: drm file | |
550 | * | |
551 | * On device open, init vm on cayman+ (all asics). | |
552 | * Returns 0 on success, error on failure. | |
553 | */ | |
771fe6b9 JG |
554 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) |
555 | { | |
721604a1 | 556 | struct radeon_device *rdev = dev->dev_private; |
10ebc0bc | 557 | int r; |
721604a1 JG |
558 | |
559 | file_priv->driver_priv = NULL; | |
560 | ||
10ebc0bc DA |
561 | r = pm_runtime_get_sync(dev->dev); |
562 | if (r < 0) | |
563 | return r; | |
564 | ||
721604a1 JG |
565 | /* new gpu have virtual address space support */ |
566 | if (rdev->family >= CHIP_CAYMAN) { | |
567 | struct radeon_fpriv *fpriv; | |
d72d43cf | 568 | struct radeon_bo_va *bo_va; |
721604a1 JG |
569 | int r; |
570 | ||
571 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
572 | if (unlikely(!fpriv)) { | |
573 | return -ENOMEM; | |
574 | } | |
575 | ||
6d2f2944 | 576 | r = radeon_vm_init(rdev, &fpriv->vm); |
74073c9d QC |
577 | if (r) { |
578 | kfree(fpriv); | |
6d2f2944 | 579 | return r; |
74073c9d | 580 | } |
d72d43cf | 581 | |
f1e3dc70 | 582 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); |
74073c9d QC |
583 | if (r) { |
584 | radeon_vm_fini(rdev, &fpriv->vm); | |
585 | kfree(fpriv); | |
f1e3dc70 | 586 | return r; |
74073c9d | 587 | } |
f1e3dc70 | 588 | |
d72d43cf CK |
589 | /* map the ib pool buffer read only into |
590 | * virtual address space */ | |
591 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, | |
592 | rdev->ring_tmp_bo.bo); | |
593 | r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, | |
594 | RADEON_VM_PAGE_READABLE | | |
595 | RADEON_VM_PAGE_SNOOPED); | |
f1e3dc70 CK |
596 | |
597 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); | |
721604a1 JG |
598 | if (r) { |
599 | radeon_vm_fini(rdev, &fpriv->vm); | |
600 | kfree(fpriv); | |
601 | return r; | |
602 | } | |
603 | ||
604 | file_priv->driver_priv = fpriv; | |
605 | } | |
10ebc0bc DA |
606 | |
607 | pm_runtime_mark_last_busy(dev->dev); | |
608 | pm_runtime_put_autosuspend(dev->dev); | |
771fe6b9 JG |
609 | return 0; |
610 | } | |
611 | ||
f482a141 AD |
612 | /** |
613 | * radeon_driver_postclose_kms - drm callback for post close | |
614 | * | |
615 | * @dev: drm dev pointer | |
616 | * @file_priv: drm file | |
617 | * | |
618 | * On device post close, tear down vm on cayman+ (all asics). | |
619 | */ | |
771fe6b9 JG |
620 | void radeon_driver_postclose_kms(struct drm_device *dev, |
621 | struct drm_file *file_priv) | |
622 | { | |
721604a1 JG |
623 | struct radeon_device *rdev = dev->dev_private; |
624 | ||
625 | /* new gpu have virtual address space support */ | |
626 | if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { | |
627 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
d72d43cf CK |
628 | struct radeon_bo_va *bo_va; |
629 | int r; | |
630 | ||
631 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); | |
632 | if (!r) { | |
633 | bo_va = radeon_vm_bo_find(&fpriv->vm, | |
634 | rdev->ring_tmp_bo.bo); | |
635 | if (bo_va) | |
636 | radeon_vm_bo_rmv(rdev, bo_va); | |
637 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); | |
638 | } | |
721604a1 JG |
639 | |
640 | radeon_vm_fini(rdev, &fpriv->vm); | |
641 | kfree(fpriv); | |
642 | file_priv->driver_priv = NULL; | |
643 | } | |
771fe6b9 JG |
644 | } |
645 | ||
f482a141 AD |
646 | /** |
647 | * radeon_driver_preclose_kms - drm callback for pre close | |
648 | * | |
649 | * @dev: drm dev pointer | |
650 | * @file_priv: drm file | |
651 | * | |
652 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
653 | * (all asics). | |
654 | */ | |
771fe6b9 JG |
655 | void radeon_driver_preclose_kms(struct drm_device *dev, |
656 | struct drm_file *file_priv) | |
657 | { | |
ab9e1f59 DA |
658 | struct radeon_device *rdev = dev->dev_private; |
659 | if (rdev->hyperz_filp == file_priv) | |
660 | rdev->hyperz_filp = NULL; | |
dca0d612 MO |
661 | if (rdev->cmask_filp == file_priv) |
662 | rdev->cmask_filp = NULL; | |
f2ba57b5 | 663 | radeon_uvd_free_handles(rdev, file_priv); |
d93f7937 | 664 | radeon_vce_free_handles(rdev, file_priv); |
771fe6b9 JG |
665 | } |
666 | ||
771fe6b9 JG |
667 | /* |
668 | * VBlank related functions. | |
669 | */ | |
f482a141 AD |
670 | /** |
671 | * radeon_get_vblank_counter_kms - get frame count | |
672 | * | |
673 | * @dev: drm dev pointer | |
674 | * @crtc: crtc to get the frame count from | |
675 | * | |
676 | * Gets the frame count on the requested crtc (all asics). | |
677 | * Returns frame count on success, -EINVAL on failure. | |
678 | */ | |
771fe6b9 JG |
679 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) |
680 | { | |
7ed220d7 MD |
681 | struct radeon_device *rdev = dev->dev_private; |
682 | ||
9c950a43 | 683 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
684 | DRM_ERROR("Invalid crtc %d\n", crtc); |
685 | return -EINVAL; | |
686 | } | |
687 | ||
688 | return radeon_get_vblank_counter(rdev, crtc); | |
771fe6b9 JG |
689 | } |
690 | ||
f482a141 AD |
691 | /** |
692 | * radeon_enable_vblank_kms - enable vblank interrupt | |
693 | * | |
694 | * @dev: drm dev pointer | |
695 | * @crtc: crtc to enable vblank interrupt for | |
696 | * | |
697 | * Enable the interrupt on the requested crtc (all asics). | |
698 | * Returns 0 on success, -EINVAL on failure. | |
699 | */ | |
771fe6b9 JG |
700 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
701 | { | |
7ed220d7 | 702 | struct radeon_device *rdev = dev->dev_private; |
fb98257a CK |
703 | unsigned long irqflags; |
704 | int r; | |
7ed220d7 | 705 | |
9c950a43 | 706 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
707 | DRM_ERROR("Invalid crtc %d\n", crtc); |
708 | return -EINVAL; | |
709 | } | |
710 | ||
fb98257a | 711 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 712 | rdev->irq.crtc_vblank_int[crtc] = true; |
fb98257a CK |
713 | r = radeon_irq_set(rdev); |
714 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
715 | return r; | |
771fe6b9 JG |
716 | } |
717 | ||
f482a141 AD |
718 | /** |
719 | * radeon_disable_vblank_kms - disable vblank interrupt | |
720 | * | |
721 | * @dev: drm dev pointer | |
722 | * @crtc: crtc to disable vblank interrupt for | |
723 | * | |
724 | * Disable the interrupt on the requested crtc (all asics). | |
725 | */ | |
771fe6b9 JG |
726 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
727 | { | |
7ed220d7 | 728 | struct radeon_device *rdev = dev->dev_private; |
fb98257a | 729 | unsigned long irqflags; |
7ed220d7 | 730 | |
9c950a43 | 731 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
732 | DRM_ERROR("Invalid crtc %d\n", crtc); |
733 | return; | |
734 | } | |
735 | ||
fb98257a | 736 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 737 | rdev->irq.crtc_vblank_int[crtc] = false; |
7ed220d7 | 738 | radeon_irq_set(rdev); |
fb98257a | 739 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
771fe6b9 JG |
740 | } |
741 | ||
f482a141 AD |
742 | /** |
743 | * radeon_get_vblank_timestamp_kms - get vblank timestamp | |
744 | * | |
745 | * @dev: drm dev pointer | |
746 | * @crtc: crtc to get the timestamp for | |
747 | * @max_error: max error | |
748 | * @vblank_time: time value | |
749 | * @flags: flags passed to the driver | |
750 | * | |
751 | * Gets the timestamp on the requested crtc based on the | |
752 | * scanout position. (all asics). | |
753 | * Returns postive status flags on success, negative error on failure. | |
754 | */ | |
f5a80209 MK |
755 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
756 | int *max_error, | |
757 | struct timeval *vblank_time, | |
758 | unsigned flags) | |
759 | { | |
760 | struct drm_crtc *drmcrtc; | |
761 | struct radeon_device *rdev = dev->dev_private; | |
762 | ||
763 | if (crtc < 0 || crtc >= dev->num_crtcs) { | |
764 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
765 | return -EINVAL; | |
766 | } | |
767 | ||
768 | /* Get associated drm_crtc: */ | |
769 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; | |
770 | ||
771 | /* Helper routine in DRM core does all the work: */ | |
772 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, | |
773 | vblank_time, flags, | |
7da903ef | 774 | drmcrtc, &drmcrtc->hwmode); |
f5a80209 | 775 | } |
771fe6b9 | 776 | |
771fe6b9 | 777 | #define KMS_INVALID_IOCTL(name) \ |
f6e2e407 RK |
778 | static int name(struct drm_device *dev, void *data, struct drm_file \ |
779 | *file_priv) \ | |
771fe6b9 JG |
780 | { \ |
781 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ | |
782 | return -EINVAL; \ | |
783 | } | |
784 | ||
785 | /* | |
786 | * All these ioctls are invalid in kms world. | |
787 | */ | |
788 | KMS_INVALID_IOCTL(radeon_cp_init_kms) | |
789 | KMS_INVALID_IOCTL(radeon_cp_start_kms) | |
790 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) | |
791 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) | |
792 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) | |
793 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) | |
794 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) | |
795 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) | |
796 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) | |
797 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) | |
798 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) | |
799 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) | |
800 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) | |
801 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) | |
802 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) | |
803 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) | |
804 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) | |
805 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) | |
806 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) | |
807 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) | |
808 | KMS_INVALID_IOCTL(radeon_mem_free_kms) | |
809 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) | |
810 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) | |
811 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) | |
812 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) | |
813 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) | |
814 | KMS_INVALID_IOCTL(radeon_surface_free_kms) | |
815 | ||
816 | ||
baa70943 | 817 | const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
1b2f1489 DA |
818 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
819 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
820 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
821 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
822 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), | |
823 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), | |
824 | DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), | |
825 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), | |
826 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), | |
827 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), | |
828 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), | |
829 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), | |
830 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), | |
831 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), | |
832 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
833 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), | |
834 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), | |
835 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), | |
836 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), | |
837 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), | |
838 | DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), | |
839 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
840 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), | |
841 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), | |
842 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), | |
843 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), | |
844 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), | |
771fe6b9 | 845 | /* KMS */ |
f33bcab9 CK |
846 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
847 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
848 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
849 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
1b2f1489 DA |
850 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), |
851 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
f33bcab9 CK |
852 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
853 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
854 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
855 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
856 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
857 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
858 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), | |
bda72d58 | 859 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
771fe6b9 JG |
860 | }; |
861 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |