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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "drm_sarea.h" | |
30 | #include "radeon.h" | |
31 | #include "radeon_drm.h" | |
32 | ||
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
6a9ee8af | 35 | |
cf0fe456 JG |
36 | int radeon_driver_unload_kms(struct drm_device *dev) |
37 | { | |
38 | struct radeon_device *rdev = dev->dev_private; | |
39 | ||
40 | if (rdev == NULL) | |
41 | return 0; | |
42 | radeon_modeset_fini(rdev); | |
43 | radeon_device_fini(rdev); | |
44 | kfree(rdev); | |
45 | dev->dev_private = NULL; | |
46 | return 0; | |
47 | } | |
771fe6b9 | 48 | |
771fe6b9 JG |
49 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
50 | { | |
51 | struct radeon_device *rdev; | |
d7a2952f | 52 | int r, acpi_status; |
771fe6b9 JG |
53 | |
54 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
55 | if (rdev == NULL) { | |
56 | return -ENOMEM; | |
57 | } | |
58 | dev->dev_private = (void *)rdev; | |
59 | ||
60 | /* update BUS flag */ | |
61 | if (drm_device_is_agp(dev)) { | |
62 | flags |= RADEON_IS_AGP; | |
63 | } else if (drm_device_is_pcie(dev)) { | |
64 | flags |= RADEON_IS_PCIE; | |
65 | } else { | |
66 | flags |= RADEON_IS_PCI; | |
67 | } | |
68 | ||
6cf8a3f5 JG |
69 | /* radeon_device_init should report only fatal error |
70 | * like memory allocation failure or iomapping failure, | |
71 | * or memory manager initialization failure, it must | |
72 | * properly initialize the GPU MC controller and permit | |
73 | * VRAM allocation | |
74 | */ | |
771fe6b9 JG |
75 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
76 | if (r) { | |
cf0fe456 JG |
77 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
78 | goto out; | |
6cf8a3f5 | 79 | } |
d7a2952f AM |
80 | |
81 | /* Call ACPI methods */ | |
82 | acpi_status = radeon_acpi_init(rdev); | |
83 | if (acpi_status) | |
dc77de12 | 84 | dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); |
d7a2952f | 85 | |
6cf8a3f5 JG |
86 | /* Again modeset_init should fail only on fatal error |
87 | * otherwise it should provide enough functionalities | |
88 | * for shadowfb to run | |
89 | */ | |
90 | r = radeon_modeset_init(rdev); | |
cf0fe456 JG |
91 | if (r) |
92 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); | |
93 | out: | |
94 | if (r) | |
95 | radeon_driver_unload_kms(dev); | |
96 | return r; | |
771fe6b9 JG |
97 | } |
98 | ||
9eba4a93 MO |
99 | static void radeon_set_filp_rights(struct drm_device *dev, |
100 | struct drm_file **owner, | |
101 | struct drm_file *applier, | |
102 | uint32_t *value) | |
103 | { | |
104 | mutex_lock(&dev->struct_mutex); | |
105 | if (*value == 1) { | |
106 | /* wants rights */ | |
107 | if (!*owner) | |
108 | *owner = applier; | |
109 | } else if (*value == 0) { | |
110 | /* revokes rights */ | |
111 | if (*owner == applier) | |
112 | *owner = NULL; | |
113 | } | |
114 | *value = *owner == applier ? 1 : 0; | |
115 | mutex_unlock(&dev->struct_mutex); | |
116 | } | |
771fe6b9 JG |
117 | |
118 | /* | |
9eba4a93 | 119 | * Userspace get information ioctl |
771fe6b9 JG |
120 | */ |
121 | int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
122 | { | |
123 | struct radeon_device *rdev = dev->dev_private; | |
124 | struct drm_radeon_info *info; | |
bc35afdb | 125 | struct radeon_mode_info *minfo = &rdev->mode_info; |
771fe6b9 JG |
126 | uint32_t *value_ptr; |
127 | uint32_t value; | |
bc35afdb JG |
128 | struct drm_crtc *crtc; |
129 | int i, found; | |
771fe6b9 JG |
130 | |
131 | info = data; | |
132 | value_ptr = (uint32_t *)((unsigned long)info->value); | |
d8ab3557 DDAG |
133 | if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) |
134 | return -EFAULT; | |
135 | ||
771fe6b9 JG |
136 | switch (info->request) { |
137 | case RADEON_INFO_DEVICE_ID: | |
138 | value = dev->pci_device; | |
139 | break; | |
140 | case RADEON_INFO_NUM_GB_PIPES: | |
141 | value = rdev->num_gb_pipes; | |
142 | break; | |
f779b3e5 AD |
143 | case RADEON_INFO_NUM_Z_PIPES: |
144 | value = rdev->num_z_pipes; | |
145 | break; | |
733289c2 | 146 | case RADEON_INFO_ACCEL_WORKING: |
148a03bc AD |
147 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
148 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) | |
149 | value = false; | |
150 | else | |
151 | value = rdev->accel_working; | |
733289c2 | 152 | break; |
bc35afdb JG |
153 | case RADEON_INFO_CRTC_FROM_ID: |
154 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { | |
155 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
156 | if (crtc && crtc->base.id == value) { | |
0baf2d8f AD |
157 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
158 | value = radeon_crtc->crtc_id; | |
bc35afdb JG |
159 | found = 1; |
160 | break; | |
161 | } | |
162 | } | |
163 | if (!found) { | |
d9fdaafb | 164 | DRM_DEBUG_KMS("unknown crtc id %d\n", value); |
bc35afdb JG |
165 | return -EINVAL; |
166 | } | |
167 | break; | |
148a03bc AD |
168 | case RADEON_INFO_ACCEL_WORKING2: |
169 | value = rdev->accel_working; | |
170 | break; | |
e7aeeba6 AD |
171 | case RADEON_INFO_TILING_CONFIG: |
172 | if (rdev->family >= CHIP_CEDAR) | |
173 | value = rdev->config.evergreen.tile_config; | |
174 | else if (rdev->family >= CHIP_RV770) | |
175 | value = rdev->config.rv770.tile_config; | |
176 | else if (rdev->family >= CHIP_R600) | |
177 | value = rdev->config.r600.tile_config; | |
178 | else { | |
d9fdaafb | 179 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
e7aeeba6 AD |
180 | return -EINVAL; |
181 | } | |
b824b364 | 182 | break; |
ab9e1f59 | 183 | case RADEON_INFO_WANT_HYPERZ: |
43861f71 MO |
184 | /* The "value" here is both an input and output parameter. |
185 | * If the input value is 1, filp requests hyper-z access. | |
186 | * If the input value is 0, filp revokes its hyper-z access. | |
187 | * | |
188 | * When returning, the value is 1 if filp owns hyper-z access, | |
189 | * 0 otherwise. */ | |
190 | if (value >= 2) { | |
191 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value); | |
192 | return -EINVAL; | |
193 | } | |
9eba4a93 MO |
194 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value); |
195 | break; | |
196 | case RADEON_INFO_WANT_CMASK: | |
197 | /* The same logic as Hyper-Z. */ | |
198 | if (value >= 2) { | |
199 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value); | |
200 | return -EINVAL; | |
ab9e1f59 | 201 | } |
9eba4a93 | 202 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); |
e7aeeba6 | 203 | break; |
771fe6b9 | 204 | default: |
d9fdaafb | 205 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
771fe6b9 JG |
206 | return -EINVAL; |
207 | } | |
208 | if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { | |
209 | DRM_ERROR("copy_to_user\n"); | |
210 | return -EFAULT; | |
211 | } | |
212 | return 0; | |
213 | } | |
214 | ||
215 | ||
216 | /* | |
217 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
218 | */ | |
219 | int radeon_driver_firstopen_kms(struct drm_device *dev) | |
220 | { | |
221 | return 0; | |
222 | } | |
223 | ||
224 | ||
225 | void radeon_driver_lastclose_kms(struct drm_device *dev) | |
226 | { | |
6a9ee8af | 227 | vga_switcheroo_process_delayed_switch(); |
771fe6b9 JG |
228 | } |
229 | ||
230 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
231 | { | |
232 | return 0; | |
233 | } | |
234 | ||
235 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
236 | struct drm_file *file_priv) | |
237 | { | |
238 | } | |
239 | ||
240 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
241 | struct drm_file *file_priv) | |
242 | { | |
ab9e1f59 DA |
243 | struct radeon_device *rdev = dev->dev_private; |
244 | if (rdev->hyperz_filp == file_priv) | |
245 | rdev->hyperz_filp = NULL; | |
771fe6b9 JG |
246 | } |
247 | ||
771fe6b9 JG |
248 | /* |
249 | * VBlank related functions. | |
250 | */ | |
251 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) | |
252 | { | |
7ed220d7 MD |
253 | struct radeon_device *rdev = dev->dev_private; |
254 | ||
9c950a43 | 255 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
256 | DRM_ERROR("Invalid crtc %d\n", crtc); |
257 | return -EINVAL; | |
258 | } | |
259 | ||
260 | return radeon_get_vblank_counter(rdev, crtc); | |
771fe6b9 JG |
261 | } |
262 | ||
263 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) | |
264 | { | |
7ed220d7 MD |
265 | struct radeon_device *rdev = dev->dev_private; |
266 | ||
9c950a43 | 267 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
268 | DRM_ERROR("Invalid crtc %d\n", crtc); |
269 | return -EINVAL; | |
270 | } | |
271 | ||
272 | rdev->irq.crtc_vblank_int[crtc] = true; | |
273 | ||
274 | return radeon_irq_set(rdev); | |
771fe6b9 JG |
275 | } |
276 | ||
277 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) | |
278 | { | |
7ed220d7 MD |
279 | struct radeon_device *rdev = dev->dev_private; |
280 | ||
9c950a43 | 281 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
282 | DRM_ERROR("Invalid crtc %d\n", crtc); |
283 | return; | |
284 | } | |
285 | ||
286 | rdev->irq.crtc_vblank_int[crtc] = false; | |
287 | ||
288 | radeon_irq_set(rdev); | |
771fe6b9 JG |
289 | } |
290 | ||
f5a80209 MK |
291 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
292 | int *max_error, | |
293 | struct timeval *vblank_time, | |
294 | unsigned flags) | |
295 | { | |
296 | struct drm_crtc *drmcrtc; | |
297 | struct radeon_device *rdev = dev->dev_private; | |
298 | ||
299 | if (crtc < 0 || crtc >= dev->num_crtcs) { | |
300 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
301 | return -EINVAL; | |
302 | } | |
303 | ||
304 | /* Get associated drm_crtc: */ | |
305 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; | |
306 | ||
307 | /* Helper routine in DRM core does all the work: */ | |
308 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, | |
309 | vblank_time, flags, | |
310 | drmcrtc); | |
311 | } | |
771fe6b9 | 312 | |
771fe6b9 JG |
313 | /* |
314 | * IOCTL. | |
315 | */ | |
316 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, | |
317 | struct drm_file *file_priv) | |
318 | { | |
319 | /* Not valid in KMS. */ | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | #define KMS_INVALID_IOCTL(name) \ | |
324 | int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ | |
325 | { \ | |
326 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ | |
327 | return -EINVAL; \ | |
328 | } | |
329 | ||
330 | /* | |
331 | * All these ioctls are invalid in kms world. | |
332 | */ | |
333 | KMS_INVALID_IOCTL(radeon_cp_init_kms) | |
334 | KMS_INVALID_IOCTL(radeon_cp_start_kms) | |
335 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) | |
336 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) | |
337 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) | |
338 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) | |
339 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) | |
340 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) | |
341 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) | |
342 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) | |
343 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) | |
344 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) | |
345 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) | |
346 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) | |
347 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) | |
348 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) | |
349 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) | |
350 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) | |
351 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) | |
352 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) | |
353 | KMS_INVALID_IOCTL(radeon_mem_free_kms) | |
354 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) | |
355 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) | |
356 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) | |
357 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) | |
358 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) | |
359 | KMS_INVALID_IOCTL(radeon_surface_free_kms) | |
360 | ||
361 | ||
362 | struct drm_ioctl_desc radeon_ioctls_kms[] = { | |
1b2f1489 DA |
363 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
364 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
365 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
366 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
367 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), | |
368 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), | |
369 | DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), | |
370 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), | |
371 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), | |
372 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), | |
373 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), | |
374 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), | |
375 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), | |
376 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), | |
377 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
378 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), | |
379 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), | |
380 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), | |
381 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), | |
382 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), | |
383 | DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), | |
384 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
385 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), | |
386 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), | |
387 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), | |
388 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), | |
389 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), | |
771fe6b9 | 390 | /* KMS */ |
1b2f1489 DA |
391 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), |
392 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
393 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
394 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
395 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
396 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
397 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
398 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
399 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
400 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
401 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
402 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
771fe6b9 JG |
403 | }; |
404 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |