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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "drm_sarea.h" | |
30 | #include "radeon.h" | |
31 | #include "radeon_drm.h" | |
32 | ||
33 | ||
34 | /* | |
35 | * Driver load/unload | |
36 | */ | |
37 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) | |
38 | { | |
39 | struct radeon_device *rdev; | |
40 | int r; | |
41 | ||
42 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
43 | if (rdev == NULL) { | |
44 | return -ENOMEM; | |
45 | } | |
46 | dev->dev_private = (void *)rdev; | |
47 | ||
48 | /* update BUS flag */ | |
49 | if (drm_device_is_agp(dev)) { | |
50 | flags |= RADEON_IS_AGP; | |
51 | } else if (drm_device_is_pcie(dev)) { | |
52 | flags |= RADEON_IS_PCIE; | |
53 | } else { | |
54 | flags |= RADEON_IS_PCI; | |
55 | } | |
56 | ||
57 | r = radeon_device_init(rdev, dev, dev->pdev, flags); | |
58 | if (r) { | |
59 | DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n"); | |
60 | radeon_device_fini(rdev); | |
c9b7fb54 XF |
61 | kfree(rdev); |
62 | dev->dev_private = NULL; | |
771fe6b9 JG |
63 | return r; |
64 | } | |
65 | return 0; | |
66 | } | |
67 | ||
68 | int radeon_driver_unload_kms(struct drm_device *dev) | |
69 | { | |
70 | struct radeon_device *rdev = dev->dev_private; | |
71 | ||
72 | radeon_device_fini(rdev); | |
73 | kfree(rdev); | |
74 | dev->dev_private = NULL; | |
75 | return 0; | |
76 | } | |
77 | ||
78 | ||
79 | /* | |
80 | * Userspace get informations ioctl | |
81 | */ | |
82 | int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
83 | { | |
84 | struct radeon_device *rdev = dev->dev_private; | |
85 | struct drm_radeon_info *info; | |
86 | uint32_t *value_ptr; | |
87 | uint32_t value; | |
88 | ||
89 | info = data; | |
90 | value_ptr = (uint32_t *)((unsigned long)info->value); | |
91 | switch (info->request) { | |
92 | case RADEON_INFO_DEVICE_ID: | |
93 | value = dev->pci_device; | |
94 | break; | |
95 | case RADEON_INFO_NUM_GB_PIPES: | |
96 | value = rdev->num_gb_pipes; | |
97 | break; | |
f779b3e5 AD |
98 | case RADEON_INFO_NUM_Z_PIPES: |
99 | value = rdev->num_z_pipes; | |
100 | break; | |
771fe6b9 JG |
101 | default: |
102 | DRM_DEBUG("Invalid request %d\n", info->request); | |
103 | return -EINVAL; | |
104 | } | |
105 | if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { | |
106 | DRM_ERROR("copy_to_user\n"); | |
107 | return -EFAULT; | |
108 | } | |
109 | return 0; | |
110 | } | |
111 | ||
112 | ||
113 | /* | |
114 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
115 | */ | |
116 | int radeon_driver_firstopen_kms(struct drm_device *dev) | |
117 | { | |
118 | return 0; | |
119 | } | |
120 | ||
121 | ||
122 | void radeon_driver_lastclose_kms(struct drm_device *dev) | |
123 | { | |
124 | } | |
125 | ||
126 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
127 | { | |
128 | return 0; | |
129 | } | |
130 | ||
131 | void radeon_driver_postclose_kms(struct drm_device *dev, | |
132 | struct drm_file *file_priv) | |
133 | { | |
134 | } | |
135 | ||
136 | void radeon_driver_preclose_kms(struct drm_device *dev, | |
137 | struct drm_file *file_priv) | |
138 | { | |
139 | } | |
140 | ||
141 | ||
142 | /* | |
143 | * VBlank related functions. | |
144 | */ | |
145 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) | |
146 | { | |
7ed220d7 MD |
147 | struct radeon_device *rdev = dev->dev_private; |
148 | ||
149 | if (crtc < 0 || crtc > 1) { | |
150 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
151 | return -EINVAL; | |
152 | } | |
153 | ||
154 | return radeon_get_vblank_counter(rdev, crtc); | |
771fe6b9 JG |
155 | } |
156 | ||
157 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) | |
158 | { | |
7ed220d7 MD |
159 | struct radeon_device *rdev = dev->dev_private; |
160 | ||
161 | if (crtc < 0 || crtc > 1) { | |
162 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
166 | rdev->irq.crtc_vblank_int[crtc] = true; | |
167 | ||
168 | return radeon_irq_set(rdev); | |
771fe6b9 JG |
169 | } |
170 | ||
171 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) | |
172 | { | |
7ed220d7 MD |
173 | struct radeon_device *rdev = dev->dev_private; |
174 | ||
175 | if (crtc < 0 || crtc > 1) { | |
176 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
177 | return; | |
178 | } | |
179 | ||
180 | rdev->irq.crtc_vblank_int[crtc] = false; | |
181 | ||
182 | radeon_irq_set(rdev); | |
771fe6b9 JG |
183 | } |
184 | ||
185 | ||
186 | /* | |
187 | * For multiple master (like multiple X). | |
188 | */ | |
189 | struct drm_radeon_master_private { | |
190 | drm_local_map_t *sarea; | |
191 | drm_radeon_sarea_t *sarea_priv; | |
192 | }; | |
193 | ||
194 | int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master) | |
195 | { | |
196 | struct drm_radeon_master_private *master_priv; | |
197 | unsigned long sareapage; | |
198 | int ret; | |
199 | ||
9a298b2a | 200 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
771fe6b9 JG |
201 | if (master_priv == NULL) { |
202 | return -ENOMEM; | |
203 | } | |
204 | /* prebuild the SAREA */ | |
205 | sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE); | |
206 | ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, | |
3b47883d | 207 | _DRM_CONTAINS_LOCK, |
771fe6b9 JG |
208 | &master_priv->sarea); |
209 | if (ret) { | |
210 | DRM_ERROR("SAREA setup failed\n"); | |
211 | return ret; | |
212 | } | |
213 | master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea); | |
214 | master_priv->sarea_priv->pfCurrentPage = 0; | |
215 | master->driver_priv = master_priv; | |
216 | return 0; | |
217 | } | |
218 | ||
219 | void radeon_master_destroy_kms(struct drm_device *dev, | |
220 | struct drm_master *master) | |
221 | { | |
222 | struct drm_radeon_master_private *master_priv = master->driver_priv; | |
223 | ||
224 | if (master_priv == NULL) { | |
225 | return; | |
226 | } | |
227 | if (master_priv->sarea) { | |
228 | drm_rmmap_locked(dev, master_priv->sarea); | |
229 | } | |
9a298b2a | 230 | kfree(master_priv); |
771fe6b9 JG |
231 | master->driver_priv = NULL; |
232 | } | |
233 | ||
234 | ||
235 | /* | |
236 | * IOCTL. | |
237 | */ | |
238 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, | |
239 | struct drm_file *file_priv) | |
240 | { | |
241 | /* Not valid in KMS. */ | |
242 | return -EINVAL; | |
243 | } | |
244 | ||
245 | #define KMS_INVALID_IOCTL(name) \ | |
246 | int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ | |
247 | { \ | |
248 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ | |
249 | return -EINVAL; \ | |
250 | } | |
251 | ||
252 | /* | |
253 | * All these ioctls are invalid in kms world. | |
254 | */ | |
255 | KMS_INVALID_IOCTL(radeon_cp_init_kms) | |
256 | KMS_INVALID_IOCTL(radeon_cp_start_kms) | |
257 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) | |
258 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) | |
259 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) | |
260 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) | |
261 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) | |
262 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) | |
263 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) | |
264 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) | |
265 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) | |
266 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) | |
267 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) | |
268 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) | |
269 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) | |
270 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) | |
271 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) | |
272 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) | |
273 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) | |
274 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) | |
275 | KMS_INVALID_IOCTL(radeon_mem_free_kms) | |
276 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) | |
277 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) | |
278 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) | |
279 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) | |
280 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) | |
281 | KMS_INVALID_IOCTL(radeon_surface_free_kms) | |
282 | ||
283 | ||
284 | struct drm_ioctl_desc radeon_ioctls_kms[] = { | |
285 | DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
286 | DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
287 | DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
288 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
289 | DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), | |
290 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), | |
291 | DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), | |
292 | DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), | |
293 | DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), | |
294 | DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), | |
295 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), | |
296 | DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), | |
297 | DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), | |
298 | DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), | |
299 | DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
300 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), | |
301 | DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), | |
302 | DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), | |
303 | DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), | |
304 | DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), | |
305 | DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), | |
306 | DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
307 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), | |
308 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), | |
309 | DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), | |
310 | DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), | |
311 | DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), | |
312 | /* KMS */ | |
313 | DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH), | |
314 | DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH), | |
315 | DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH), | |
316 | DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH), | |
317 | DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), | |
318 | DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), | |
319 | DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH), | |
320 | DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH), | |
321 | DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH), | |
e024e110 DA |
322 | DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH), |
323 | DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH), | |
e3b2415e | 324 | DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH), |
771fe6b9 JG |
325 | }; |
326 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |