Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 | 29 | #include "radeon.h" |
760285e7 | 30 | #include <drm/radeon_drm.h> |
6759a0a7 | 31 | #include "radeon_asic.h" |
771fe6b9 | 32 | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
10ebc0bc | 35 | #include <linux/pm_runtime.h> |
78488659 | 36 | |
e28740ec OG |
37 | #include "radeon_kfd.h" |
38 | ||
78488659 | 39 | #if defined(CONFIG_VGA_SWITCHEROO) |
90c4cde9 | 40 | bool radeon_has_atpx(void); |
78488659 | 41 | #else |
90c4cde9 | 42 | static inline bool radeon_has_atpx(void) { return false; } |
78488659 AD |
43 | #endif |
44 | ||
f482a141 AD |
45 | /** |
46 | * radeon_driver_unload_kms - Main unload function for KMS. | |
47 | * | |
48 | * @dev: drm dev pointer | |
49 | * | |
50 | * This is the main unload function for KMS (all asics). | |
51 | * It calls radeon_modeset_fini() to tear down the | |
52 | * displays, and radeon_device_fini() to tear down | |
53 | * the rest of the device (CP, writeback, etc.). | |
54 | * Returns 0 on success. | |
55 | */ | |
cf0fe456 JG |
56 | int radeon_driver_unload_kms(struct drm_device *dev) |
57 | { | |
58 | struct radeon_device *rdev = dev->dev_private; | |
59 | ||
60 | if (rdev == NULL) | |
61 | return 0; | |
10ebc0bc | 62 | |
0cd9cb76 AD |
63 | if (rdev->rmmio == NULL) |
64 | goto done_free; | |
10ebc0bc | 65 | |
19de659c LW |
66 | if (radeon_is_px(dev)) { |
67 | pm_runtime_get_sync(dev->dev); | |
8fecb6a9 | 68 | pm_runtime_forbid(dev->dev); |
19de659c | 69 | } |
10ebc0bc | 70 | |
e28740ec OG |
71 | radeon_kfd_device_fini(rdev); |
72 | ||
c4917074 | 73 | radeon_acpi_fini(rdev); |
10ebc0bc | 74 | |
cf0fe456 JG |
75 | radeon_modeset_fini(rdev); |
76 | radeon_device_fini(rdev); | |
0cd9cb76 AD |
77 | |
78 | done_free: | |
cf0fe456 JG |
79 | kfree(rdev); |
80 | dev->dev_private = NULL; | |
81 | return 0; | |
82 | } | |
771fe6b9 | 83 | |
f482a141 AD |
84 | /** |
85 | * radeon_driver_load_kms - Main load function for KMS. | |
86 | * | |
87 | * @dev: drm dev pointer | |
88 | * @flags: device flags | |
89 | * | |
90 | * This is the main load function for KMS (all asics). | |
91 | * It calls radeon_device_init() to set up the non-display | |
92 | * parts of the chip (asic init, CP, writeback, etc.), and | |
93 | * radeon_modeset_init() to set up the display parts | |
94 | * (crtcs, encoders, hotplug detect, etc.). | |
95 | * Returns 0 on success, error on failure. | |
96 | */ | |
771fe6b9 JG |
97 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
98 | { | |
99 | struct radeon_device *rdev; | |
d7a2952f | 100 | int r, acpi_status; |
771fe6b9 JG |
101 | |
102 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); | |
103 | if (rdev == NULL) { | |
104 | return -ENOMEM; | |
105 | } | |
106 | dev->dev_private = (void *)rdev; | |
107 | ||
108 | /* update BUS flag */ | |
8410ea3b | 109 | if (drm_pci_device_is_agp(dev)) { |
771fe6b9 | 110 | flags |= RADEON_IS_AGP; |
58b6542b | 111 | } else if (pci_is_pcie(dev->pdev)) { |
771fe6b9 JG |
112 | flags |= RADEON_IS_PCIE; |
113 | } else { | |
114 | flags |= RADEON_IS_PCI; | |
115 | } | |
116 | ||
73acacc7 AD |
117 | if ((radeon_runtime_pm != 0) && |
118 | radeon_has_atpx() && | |
119 | ((flags & RADEON_IS_IGP) == 0)) | |
90c4cde9 AD |
120 | flags |= RADEON_IS_PX; |
121 | ||
6cf8a3f5 JG |
122 | /* radeon_device_init should report only fatal error |
123 | * like memory allocation failure or iomapping failure, | |
124 | * or memory manager initialization failure, it must | |
125 | * properly initialize the GPU MC controller and permit | |
126 | * VRAM allocation | |
127 | */ | |
771fe6b9 JG |
128 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
129 | if (r) { | |
cf0fe456 JG |
130 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
131 | goto out; | |
6cf8a3f5 | 132 | } |
d7a2952f | 133 | |
6cf8a3f5 JG |
134 | /* Again modeset_init should fail only on fatal error |
135 | * otherwise it should provide enough functionalities | |
136 | * for shadowfb to run | |
137 | */ | |
138 | r = radeon_modeset_init(rdev); | |
cf0fe456 JG |
139 | if (r) |
140 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); | |
fda4b25c LT |
141 | |
142 | /* Call ACPI methods: require modeset init | |
143 | * but failure is not fatal | |
144 | */ | |
145 | if (!r) { | |
146 | acpi_status = radeon_acpi_init(rdev); | |
147 | if (acpi_status) | |
148 | dev_dbg(&dev->pdev->dev, | |
149 | "Error during ACPI methods call\n"); | |
150 | } | |
151 | ||
e28740ec OG |
152 | radeon_kfd_device_probe(rdev); |
153 | radeon_kfd_device_init(rdev); | |
154 | ||
90c4cde9 | 155 | if (radeon_is_px(dev)) { |
10ebc0bc DA |
156 | pm_runtime_use_autosuspend(dev->dev); |
157 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
158 | pm_runtime_set_active(dev->dev); | |
159 | pm_runtime_allow(dev->dev); | |
160 | pm_runtime_mark_last_busy(dev->dev); | |
161 | pm_runtime_put_autosuspend(dev->dev); | |
162 | } | |
163 | ||
cf0fe456 JG |
164 | out: |
165 | if (r) | |
166 | radeon_driver_unload_kms(dev); | |
10ebc0bc DA |
167 | |
168 | ||
cf0fe456 | 169 | return r; |
771fe6b9 JG |
170 | } |
171 | ||
f482a141 AD |
172 | /** |
173 | * radeon_set_filp_rights - Set filp right. | |
174 | * | |
175 | * @dev: drm dev pointer | |
176 | * @owner: drm file | |
177 | * @applier: drm file | |
178 | * @value: value | |
179 | * | |
180 | * Sets the filp rights for the device (all asics). | |
181 | */ | |
9eba4a93 MO |
182 | static void radeon_set_filp_rights(struct drm_device *dev, |
183 | struct drm_file **owner, | |
184 | struct drm_file *applier, | |
185 | uint32_t *value) | |
186 | { | |
45c1da50 DV |
187 | struct radeon_device *rdev = dev->dev_private; |
188 | ||
189 | mutex_lock(&rdev->gem.mutex); | |
9eba4a93 MO |
190 | if (*value == 1) { |
191 | /* wants rights */ | |
192 | if (!*owner) | |
193 | *owner = applier; | |
194 | } else if (*value == 0) { | |
195 | /* revokes rights */ | |
196 | if (*owner == applier) | |
197 | *owner = NULL; | |
198 | } | |
199 | *value = *owner == applier ? 1 : 0; | |
45c1da50 | 200 | mutex_unlock(&rdev->gem.mutex); |
9eba4a93 | 201 | } |
771fe6b9 JG |
202 | |
203 | /* | |
9eba4a93 | 204 | * Userspace get information ioctl |
771fe6b9 | 205 | */ |
f482a141 AD |
206 | /** |
207 | * radeon_info_ioctl - answer a device specific request. | |
208 | * | |
209 | * @rdev: radeon device pointer | |
210 | * @data: request object | |
211 | * @filp: drm filp | |
212 | * | |
213 | * This function is used to pass device specific parameters to the userspace | |
214 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
215 | * etc. (all asics). | |
216 | * Returns 0 on success, -EINVAL on failure. | |
217 | */ | |
5520345f | 218 | static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
771fe6b9 JG |
219 | { |
220 | struct radeon_device *rdev = dev->dev_private; | |
6759a0a7 | 221 | struct drm_radeon_info *info = data; |
bc35afdb | 222 | struct radeon_mode_info *minfo = &rdev->mode_info; |
64d7b8be JG |
223 | uint32_t *value, value_tmp, *value_ptr, value_size; |
224 | uint64_t value64; | |
bc35afdb JG |
225 | struct drm_crtc *crtc; |
226 | int i, found; | |
771fe6b9 | 227 | |
771fe6b9 | 228 | value_ptr = (uint32_t *)((unsigned long)info->value); |
64d7b8be JG |
229 | value = &value_tmp; |
230 | value_size = sizeof(uint32_t); | |
d8ab3557 | 231 | |
771fe6b9 JG |
232 | switch (info->request) { |
233 | case RADEON_INFO_DEVICE_ID: | |
ffbab09b | 234 | *value = dev->pdev->device; |
771fe6b9 JG |
235 | break; |
236 | case RADEON_INFO_NUM_GB_PIPES: | |
64d7b8be | 237 | *value = rdev->num_gb_pipes; |
771fe6b9 | 238 | break; |
f779b3e5 | 239 | case RADEON_INFO_NUM_Z_PIPES: |
64d7b8be | 240 | *value = rdev->num_z_pipes; |
f779b3e5 | 241 | break; |
733289c2 | 242 | case RADEON_INFO_ACCEL_WORKING: |
148a03bc AD |
243 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
244 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) | |
64d7b8be | 245 | *value = false; |
148a03bc | 246 | else |
64d7b8be | 247 | *value = rdev->accel_working; |
733289c2 | 248 | break; |
bc35afdb | 249 | case RADEON_INFO_CRTC_FROM_ID: |
1d6ac185 | 250 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
251 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
252 | return -EFAULT; | |
253 | } | |
bc35afdb JG |
254 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { |
255 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
64d7b8be | 256 | if (crtc && crtc->base.id == *value) { |
0baf2d8f | 257 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
64d7b8be | 258 | *value = radeon_crtc->crtc_id; |
bc35afdb JG |
259 | found = 1; |
260 | break; | |
261 | } | |
262 | } | |
263 | if (!found) { | |
64d7b8be | 264 | DRM_DEBUG_KMS("unknown crtc id %d\n", *value); |
bc35afdb JG |
265 | return -EINVAL; |
266 | } | |
267 | break; | |
148a03bc | 268 | case RADEON_INFO_ACCEL_WORKING2: |
3c64bd26 | 269 | if (rdev->family == CHIP_HAWAII) { |
9eb401af AB |
270 | if (rdev->accel_working) { |
271 | if (rdev->new_fw) | |
272 | *value = 3; | |
273 | else | |
274 | *value = 2; | |
275 | } else { | |
3c64bd26 | 276 | *value = 0; |
9eb401af | 277 | } |
3c64bd26 AD |
278 | } else { |
279 | *value = rdev->accel_working; | |
280 | } | |
148a03bc | 281 | break; |
e7aeeba6 | 282 | case RADEON_INFO_TILING_CONFIG: |
64f759cc AD |
283 | if (rdev->family >= CHIP_BONAIRE) |
284 | *value = rdev->config.cik.tile_config; | |
285 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 286 | *value = rdev->config.si.tile_config; |
c1b2f69f | 287 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 288 | *value = rdev->config.cayman.tile_config; |
fecf1d07 | 289 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 290 | *value = rdev->config.evergreen.tile_config; |
e7aeeba6 | 291 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 292 | *value = rdev->config.rv770.tile_config; |
e7aeeba6 | 293 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 294 | *value = rdev->config.r600.tile_config; |
e7aeeba6 | 295 | else { |
d9fdaafb | 296 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
e7aeeba6 AD |
297 | return -EINVAL; |
298 | } | |
b824b364 | 299 | break; |
ab9e1f59 | 300 | case RADEON_INFO_WANT_HYPERZ: |
43861f71 MO |
301 | /* The "value" here is both an input and output parameter. |
302 | * If the input value is 1, filp requests hyper-z access. | |
303 | * If the input value is 0, filp revokes its hyper-z access. | |
304 | * | |
305 | * When returning, the value is 1 if filp owns hyper-z access, | |
306 | * 0 otherwise. */ | |
1d6ac185 | 307 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
308 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
309 | return -EFAULT; | |
310 | } | |
311 | if (*value >= 2) { | |
312 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); | |
43861f71 MO |
313 | return -EINVAL; |
314 | } | |
64d7b8be | 315 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); |
9eba4a93 MO |
316 | break; |
317 | case RADEON_INFO_WANT_CMASK: | |
318 | /* The same logic as Hyper-Z. */ | |
1d6ac185 | 319 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
320 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
321 | return -EFAULT; | |
322 | } | |
323 | if (*value >= 2) { | |
324 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); | |
9eba4a93 | 325 | return -EINVAL; |
ab9e1f59 | 326 | } |
64d7b8be | 327 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); |
e7aeeba6 | 328 | break; |
58bbf018 AD |
329 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
330 | /* return clock value in KHz */ | |
454d2e2a | 331 | if (rdev->asic->get_xclk) |
64d7b8be | 332 | *value = radeon_get_xclk(rdev) * 10; |
454d2e2a | 333 | else |
64d7b8be | 334 | *value = rdev->clock.spll.reference_freq * 10; |
58bbf018 | 335 | break; |
486af189 | 336 | case RADEON_INFO_NUM_BACKENDS: |
64f759cc AD |
337 | if (rdev->family >= CHIP_BONAIRE) |
338 | *value = rdev->config.cik.max_backends_per_se * | |
339 | rdev->config.cik.max_shader_engines; | |
340 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 341 | *value = rdev->config.si.max_backends_per_se * |
c1b2f69f MD |
342 | rdev->config.si.max_shader_engines; |
343 | else if (rdev->family >= CHIP_CAYMAN) | |
64d7b8be | 344 | *value = rdev->config.cayman.max_backends_per_se * |
fecf1d07 AD |
345 | rdev->config.cayman.max_shader_engines; |
346 | else if (rdev->family >= CHIP_CEDAR) | |
64d7b8be | 347 | *value = rdev->config.evergreen.max_backends; |
486af189 | 348 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 349 | *value = rdev->config.rv770.max_backends; |
486af189 | 350 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 351 | *value = rdev->config.r600.max_backends; |
486af189 DA |
352 | else { |
353 | return -EINVAL; | |
354 | } | |
355 | break; | |
6565945b | 356 | case RADEON_INFO_NUM_TILE_PIPES: |
64f759cc AD |
357 | if (rdev->family >= CHIP_BONAIRE) |
358 | *value = rdev->config.cik.max_tile_pipes; | |
359 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 360 | *value = rdev->config.si.max_tile_pipes; |
c1b2f69f | 361 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 362 | *value = rdev->config.cayman.max_tile_pipes; |
6565945b | 363 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 364 | *value = rdev->config.evergreen.max_tile_pipes; |
6565945b | 365 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 366 | *value = rdev->config.rv770.max_tile_pipes; |
6565945b | 367 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 368 | *value = rdev->config.r600.max_tile_pipes; |
6565945b AD |
369 | else { |
370 | return -EINVAL; | |
371 | } | |
372 | break; | |
8aeb96f8 | 373 | case RADEON_INFO_FUSION_GART_WORKING: |
64d7b8be | 374 | *value = 1; |
8aeb96f8 | 375 | break; |
e55b9422 | 376 | case RADEON_INFO_BACKEND_MAP: |
64f759cc | 377 | if (rdev->family >= CHIP_BONAIRE) |
1ddce27d | 378 | *value = rdev->config.cik.backend_map; |
64f759cc | 379 | else if (rdev->family >= CHIP_TAHITI) |
64d7b8be | 380 | *value = rdev->config.si.backend_map; |
c1b2f69f | 381 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 382 | *value = rdev->config.cayman.backend_map; |
e55b9422 | 383 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 384 | *value = rdev->config.evergreen.backend_map; |
e55b9422 | 385 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 386 | *value = rdev->config.rv770.backend_map; |
e55b9422 | 387 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 388 | *value = rdev->config.r600.backend_map; |
e55b9422 AD |
389 | else { |
390 | return -EINVAL; | |
391 | } | |
392 | break; | |
721604a1 JG |
393 | case RADEON_INFO_VA_START: |
394 | /* this is where we report if vm is supported or not */ | |
395 | if (rdev->family < CHIP_CAYMAN) | |
396 | return -EINVAL; | |
64d7b8be | 397 | *value = RADEON_VA_RESERVED_SIZE; |
721604a1 JG |
398 | break; |
399 | case RADEON_INFO_IB_VM_MAX_SIZE: | |
400 | /* this is where we report if vm is supported or not */ | |
401 | if (rdev->family < CHIP_CAYMAN) | |
402 | return -EINVAL; | |
64d7b8be | 403 | *value = RADEON_IB_VM_MAX_SIZE; |
721604a1 | 404 | break; |
609c1e15 | 405 | case RADEON_INFO_MAX_PIPES: |
64f759cc AD |
406 | if (rdev->family >= CHIP_BONAIRE) |
407 | *value = rdev->config.cik.max_cu_per_sh; | |
408 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 409 | *value = rdev->config.si.max_cu_per_sh; |
c1b2f69f | 410 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 411 | *value = rdev->config.cayman.max_pipes_per_simd; |
609c1e15 | 412 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 413 | *value = rdev->config.evergreen.max_pipes; |
609c1e15 | 414 | else if (rdev->family >= CHIP_RV770) |
64d7b8be | 415 | *value = rdev->config.rv770.max_pipes; |
609c1e15 | 416 | else if (rdev->family >= CHIP_R600) |
64d7b8be | 417 | *value = rdev->config.r600.max_pipes; |
609c1e15 TS |
418 | else { |
419 | return -EINVAL; | |
420 | } | |
421 | break; | |
64d7b8be JG |
422 | case RADEON_INFO_TIMESTAMP: |
423 | if (rdev->family < CHIP_R600) { | |
424 | DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); | |
425 | return -EINVAL; | |
426 | } | |
427 | value = (uint32_t*)&value64; | |
428 | value_size = sizeof(uint64_t); | |
429 | value64 = radeon_get_gpu_clock_counter(rdev); | |
430 | break; | |
2e1a7674 | 431 | case RADEON_INFO_MAX_SE: |
64f759cc AD |
432 | if (rdev->family >= CHIP_BONAIRE) |
433 | *value = rdev->config.cik.max_shader_engines; | |
434 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 435 | *value = rdev->config.si.max_shader_engines; |
2e1a7674 | 436 | else if (rdev->family >= CHIP_CAYMAN) |
64d7b8be | 437 | *value = rdev->config.cayman.max_shader_engines; |
2e1a7674 | 438 | else if (rdev->family >= CHIP_CEDAR) |
64d7b8be | 439 | *value = rdev->config.evergreen.num_ses; |
2e1a7674 | 440 | else |
64d7b8be | 441 | *value = 1; |
2e1a7674 AD |
442 | break; |
443 | case RADEON_INFO_MAX_SH_PER_SE: | |
64f759cc AD |
444 | if (rdev->family >= CHIP_BONAIRE) |
445 | *value = rdev->config.cik.max_sh_per_se; | |
446 | else if (rdev->family >= CHIP_TAHITI) | |
64d7b8be | 447 | *value = rdev->config.si.max_sh_per_se; |
2e1a7674 AD |
448 | else |
449 | return -EINVAL; | |
450 | break; | |
a0a53aa8 | 451 | case RADEON_INFO_FASTFB_WORKING: |
64d7b8be | 452 | *value = rdev->fastfb_working; |
a0a53aa8 | 453 | break; |
902aaef6 | 454 | case RADEON_INFO_RING_WORKING: |
1d6ac185 | 455 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
64d7b8be JG |
456 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
457 | return -EFAULT; | |
458 | } | |
459 | switch (*value) { | |
902aaef6 CK |
460 | case RADEON_CS_RING_GFX: |
461 | case RADEON_CS_RING_COMPUTE: | |
64d7b8be | 462 | *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; |
902aaef6 CK |
463 | break; |
464 | case RADEON_CS_RING_DMA: | |
64d7b8be JG |
465 | *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; |
466 | *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; | |
902aaef6 CK |
467 | break; |
468 | case RADEON_CS_RING_UVD: | |
64d7b8be | 469 | *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; |
902aaef6 | 470 | break; |
f7ba8b04 CK |
471 | case RADEON_CS_RING_VCE: |
472 | *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; | |
473 | break; | |
902aaef6 CK |
474 | default: |
475 | return -EINVAL; | |
476 | } | |
477 | break; | |
64d7b8be | 478 | case RADEON_INFO_SI_TILE_MODE_ARRAY: |
64f759cc | 479 | if (rdev->family >= CHIP_BONAIRE) { |
39aee490 AD |
480 | value = rdev->config.cik.tile_mode_array; |
481 | value_size = sizeof(uint32_t)*32; | |
482 | } else if (rdev->family >= CHIP_TAHITI) { | |
483 | value = rdev->config.si.tile_mode_array; | |
484 | value_size = sizeof(uint32_t)*32; | |
485 | } else { | |
486 | DRM_DEBUG_KMS("tile mode array is si+ only!\n"); | |
64f759cc AD |
487 | return -EINVAL; |
488 | } | |
64d7b8be | 489 | break; |
32f79a8a MD |
490 | case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: |
491 | if (rdev->family >= CHIP_BONAIRE) { | |
492 | value = rdev->config.cik.macrotile_mode_array; | |
493 | value_size = sizeof(uint32_t)*16; | |
494 | } else { | |
495 | DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); | |
496 | return -EINVAL; | |
497 | } | |
498 | break; | |
e5b9e750 TS |
499 | case RADEON_INFO_SI_CP_DMA_COMPUTE: |
500 | *value = 1; | |
501 | break; | |
439a1cff MO |
502 | case RADEON_INFO_SI_BACKEND_ENABLED_MASK: |
503 | if (rdev->family >= CHIP_BONAIRE) { | |
504 | *value = rdev->config.cik.backend_enable_mask; | |
505 | } else if (rdev->family >= CHIP_TAHITI) { | |
506 | *value = rdev->config.si.backend_enable_mask; | |
507 | } else { | |
508 | DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); | |
509 | } | |
510 | break; | |
f5f1f897 AD |
511 | case RADEON_INFO_MAX_SCLK: |
512 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && | |
513 | rdev->pm.dpm_enabled) | |
514 | *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
515 | else | |
516 | *value = rdev->pm.default_sclk * 10; | |
517 | break; | |
98ccc291 CK |
518 | case RADEON_INFO_VCE_FW_VERSION: |
519 | *value = rdev->vce.fw_version; | |
520 | break; | |
521 | case RADEON_INFO_VCE_FB_VERSION: | |
522 | *value = rdev->vce.fb_version; | |
523 | break; | |
67e8e3f9 MO |
524 | case RADEON_INFO_NUM_BYTES_MOVED: |
525 | value = (uint32_t*)&value64; | |
526 | value_size = sizeof(uint64_t); | |
527 | value64 = atomic64_read(&rdev->num_bytes_moved); | |
528 | break; | |
529 | case RADEON_INFO_VRAM_USAGE: | |
530 | value = (uint32_t*)&value64; | |
531 | value_size = sizeof(uint64_t); | |
532 | value64 = atomic64_read(&rdev->vram_usage); | |
533 | break; | |
534 | case RADEON_INFO_GTT_USAGE: | |
535 | value = (uint32_t*)&value64; | |
536 | value_size = sizeof(uint64_t); | |
537 | value64 = atomic64_read(&rdev->gtt_usage); | |
538 | break; | |
65fcf668 AD |
539 | case RADEON_INFO_ACTIVE_CU_COUNT: |
540 | if (rdev->family >= CHIP_BONAIRE) | |
541 | *value = rdev->config.cik.active_cus; | |
542 | else if (rdev->family >= CHIP_TAHITI) | |
543 | *value = rdev->config.si.active_cus; | |
544 | else if (rdev->family >= CHIP_CAYMAN) | |
545 | *value = rdev->config.cayman.active_simds; | |
546 | else if (rdev->family >= CHIP_CEDAR) | |
547 | *value = rdev->config.evergreen.active_simds; | |
548 | else if (rdev->family >= CHIP_RV770) | |
549 | *value = rdev->config.rv770.active_simds; | |
550 | else if (rdev->family >= CHIP_R600) | |
551 | *value = rdev->config.r600.active_simds; | |
552 | else | |
553 | *value = 1; | |
554 | break; | |
d6d2a188 AD |
555 | case RADEON_INFO_CURRENT_GPU_TEMP: |
556 | /* get temperature in millidegrees C */ | |
557 | if (rdev->asic->pm.get_temperature) | |
558 | *value = radeon_get_temperature(rdev); | |
559 | else | |
560 | *value = 0; | |
561 | break; | |
5c363a86 AD |
562 | case RADEON_INFO_CURRENT_GPU_SCLK: |
563 | /* get sclk in Mhz */ | |
564 | if (rdev->pm.dpm_enabled) | |
565 | *value = radeon_dpm_get_current_sclk(rdev) / 100; | |
566 | else | |
567 | *value = rdev->pm.current_sclk / 100; | |
568 | break; | |
569 | case RADEON_INFO_CURRENT_GPU_MCLK: | |
570 | /* get mclk in Mhz */ | |
571 | if (rdev->pm.dpm_enabled) | |
572 | *value = radeon_dpm_get_current_mclk(rdev) / 100; | |
573 | else | |
574 | *value = rdev->pm.current_mclk / 100; | |
575 | break; | |
4535cb9c AD |
576 | case RADEON_INFO_READ_REG: |
577 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { | |
578 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); | |
579 | return -EFAULT; | |
580 | } | |
581 | if (radeon_get_allowed_info_register(rdev, *value, value)) | |
582 | return -EINVAL; | |
583 | break; | |
3bc980bf MD |
584 | case RADEON_INFO_VA_UNMAP_WORKING: |
585 | *value = true; | |
586 | break; | |
72b9076b MO |
587 | case RADEON_INFO_GPU_RESET_COUNTER: |
588 | *value = atomic_read(&rdev->gpu_reset_counter); | |
589 | break; | |
771fe6b9 | 590 | default: |
d9fdaafb | 591 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
771fe6b9 JG |
592 | return -EINVAL; |
593 | } | |
1d6ac185 | 594 | if (copy_to_user(value_ptr, (char*)value, value_size)) { |
6759a0a7 | 595 | DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); |
771fe6b9 JG |
596 | return -EFAULT; |
597 | } | |
598 | return 0; | |
599 | } | |
600 | ||
601 | ||
602 | /* | |
603 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
604 | */ | |
f482a141 | 605 | /** |
8c70e1cd | 606 | * radeon_driver_lastclose_kms - drm callback for last close |
f482a141 AD |
607 | * |
608 | * @dev: drm dev pointer | |
609 | * | |
8e5de1d8 | 610 | * Switch vga_switcheroo state after last close (all asics). |
f482a141 | 611 | */ |
771fe6b9 JG |
612 | void radeon_driver_lastclose_kms(struct drm_device *dev) |
613 | { | |
8c70e1cd AD |
614 | struct radeon_device *rdev = dev->dev_private; |
615 | ||
616 | radeon_fbdev_restore_mode(rdev); | |
6a9ee8af | 617 | vga_switcheroo_process_delayed_switch(); |
771fe6b9 JG |
618 | } |
619 | ||
f482a141 AD |
620 | /** |
621 | * radeon_driver_open_kms - drm callback for open | |
622 | * | |
623 | * @dev: drm dev pointer | |
624 | * @file_priv: drm file | |
625 | * | |
626 | * On device open, init vm on cayman+ (all asics). | |
627 | * Returns 0 on success, error on failure. | |
628 | */ | |
771fe6b9 JG |
629 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) |
630 | { | |
721604a1 | 631 | struct radeon_device *rdev = dev->dev_private; |
10ebc0bc | 632 | int r; |
721604a1 JG |
633 | |
634 | file_priv->driver_priv = NULL; | |
635 | ||
10ebc0bc DA |
636 | r = pm_runtime_get_sync(dev->dev); |
637 | if (r < 0) | |
638 | return r; | |
639 | ||
721604a1 JG |
640 | /* new gpu have virtual address space support */ |
641 | if (rdev->family >= CHIP_CAYMAN) { | |
642 | struct radeon_fpriv *fpriv; | |
cc9e67e3 | 643 | struct radeon_vm *vm; |
721604a1 JG |
644 | int r; |
645 | ||
646 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
647 | if (unlikely(!fpriv)) { | |
648 | return -ENOMEM; | |
649 | } | |
650 | ||
24f47acc | 651 | if (rdev->accel_working) { |
544143f9 AD |
652 | vm = &fpriv->vm; |
653 | r = radeon_vm_init(rdev, vm); | |
654 | if (r) { | |
655 | kfree(fpriv); | |
656 | return r; | |
657 | } | |
658 | ||
24f47acc JG |
659 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); |
660 | if (r) { | |
cc9e67e3 | 661 | radeon_vm_fini(rdev, vm); |
24f47acc JG |
662 | kfree(fpriv); |
663 | return r; | |
664 | } | |
f1e3dc70 | 665 | |
24f47acc JG |
666 | /* map the ib pool buffer read only into |
667 | * virtual address space */ | |
cc9e67e3 CK |
668 | vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, |
669 | rdev->ring_tmp_bo.bo); | |
670 | r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, | |
671 | RADEON_VA_IB_OFFSET, | |
24f47acc JG |
672 | RADEON_VM_PAGE_READABLE | |
673 | RADEON_VM_PAGE_SNOOPED); | |
24f47acc | 674 | if (r) { |
cc9e67e3 | 675 | radeon_vm_fini(rdev, vm); |
24f47acc JG |
676 | kfree(fpriv); |
677 | return r; | |
678 | } | |
721604a1 | 679 | } |
721604a1 JG |
680 | file_priv->driver_priv = fpriv; |
681 | } | |
10ebc0bc DA |
682 | |
683 | pm_runtime_mark_last_busy(dev->dev); | |
684 | pm_runtime_put_autosuspend(dev->dev); | |
771fe6b9 JG |
685 | return 0; |
686 | } | |
687 | ||
f482a141 AD |
688 | /** |
689 | * radeon_driver_postclose_kms - drm callback for post close | |
690 | * | |
691 | * @dev: drm dev pointer | |
692 | * @file_priv: drm file | |
693 | * | |
694 | * On device post close, tear down vm on cayman+ (all asics). | |
695 | */ | |
771fe6b9 JG |
696 | void radeon_driver_postclose_kms(struct drm_device *dev, |
697 | struct drm_file *file_priv) | |
698 | { | |
721604a1 JG |
699 | struct radeon_device *rdev = dev->dev_private; |
700 | ||
701 | /* new gpu have virtual address space support */ | |
702 | if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { | |
703 | struct radeon_fpriv *fpriv = file_priv->driver_priv; | |
cc9e67e3 | 704 | struct radeon_vm *vm = &fpriv->vm; |
d72d43cf CK |
705 | int r; |
706 | ||
24f47acc JG |
707 | if (rdev->accel_working) { |
708 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); | |
709 | if (!r) { | |
cc9e67e3 CK |
710 | if (vm->ib_bo_va) |
711 | radeon_vm_bo_rmv(rdev, vm->ib_bo_va); | |
24f47acc JG |
712 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); |
713 | } | |
544143f9 | 714 | radeon_vm_fini(rdev, vm); |
d72d43cf | 715 | } |
721604a1 | 716 | |
721604a1 JG |
717 | kfree(fpriv); |
718 | file_priv->driver_priv = NULL; | |
719 | } | |
771fe6b9 JG |
720 | } |
721 | ||
f482a141 AD |
722 | /** |
723 | * radeon_driver_preclose_kms - drm callback for pre close | |
724 | * | |
725 | * @dev: drm dev pointer | |
726 | * @file_priv: drm file | |
727 | * | |
728 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
729 | * (all asics). | |
730 | */ | |
771fe6b9 JG |
731 | void radeon_driver_preclose_kms(struct drm_device *dev, |
732 | struct drm_file *file_priv) | |
733 | { | |
ab9e1f59 | 734 | struct radeon_device *rdev = dev->dev_private; |
45c1da50 DV |
735 | |
736 | mutex_lock(&rdev->gem.mutex); | |
ab9e1f59 DA |
737 | if (rdev->hyperz_filp == file_priv) |
738 | rdev->hyperz_filp = NULL; | |
dca0d612 MO |
739 | if (rdev->cmask_filp == file_priv) |
740 | rdev->cmask_filp = NULL; | |
45c1da50 DV |
741 | mutex_unlock(&rdev->gem.mutex); |
742 | ||
f2ba57b5 | 743 | radeon_uvd_free_handles(rdev, file_priv); |
d93f7937 | 744 | radeon_vce_free_handles(rdev, file_priv); |
771fe6b9 JG |
745 | } |
746 | ||
771fe6b9 JG |
747 | /* |
748 | * VBlank related functions. | |
749 | */ | |
f482a141 AD |
750 | /** |
751 | * radeon_get_vblank_counter_kms - get frame count | |
752 | * | |
753 | * @dev: drm dev pointer | |
4e926d2d | 754 | * @pipe: crtc to get the frame count from |
f482a141 AD |
755 | * |
756 | * Gets the frame count on the requested crtc (all asics). | |
757 | * Returns frame count on success, -EINVAL on failure. | |
758 | */ | |
4e926d2d | 759 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) |
771fe6b9 | 760 | { |
c55d21ea MK |
761 | int vpos, hpos, stat; |
762 | u32 count; | |
7ed220d7 MD |
763 | struct radeon_device *rdev = dev->dev_private; |
764 | ||
85a21eaf | 765 | if (pipe >= rdev->num_crtc) { |
4e926d2d | 766 | DRM_ERROR("Invalid crtc %u\n", pipe); |
7ed220d7 MD |
767 | return -EINVAL; |
768 | } | |
769 | ||
c55d21ea MK |
770 | /* The hw increments its frame counter at start of vsync, not at start |
771 | * of vblank, as is required by DRM core vblank counter handling. | |
772 | * Cook the hw count here to make it appear to the caller as if it | |
773 | * incremented at start of vblank. We measure distance to start of | |
774 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank | |
775 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter | |
776 | * result by 1 to give the proper appearance to caller. | |
777 | */ | |
4e926d2d | 778 | if (rdev->mode_info.crtcs[pipe]) { |
c55d21ea MK |
779 | /* Repeat readout if needed to provide stable result if |
780 | * we cross start of vsync during the queries. | |
781 | */ | |
782 | do { | |
4e926d2d | 783 | count = radeon_get_vblank_counter(rdev, pipe); |
c55d21ea MK |
784 | /* Ask radeon_get_crtc_scanoutpos to return vpos as |
785 | * distance to start of vblank, instead of regular | |
786 | * vertical scanout pos. | |
787 | */ | |
788 | stat = radeon_get_crtc_scanoutpos( | |
4e926d2d | 789 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, |
c55d21ea | 790 | &vpos, &hpos, NULL, NULL, |
4e926d2d TR |
791 | &rdev->mode_info.crtcs[pipe]->base.hwmode); |
792 | } while (count != radeon_get_vblank_counter(rdev, pipe)); | |
c55d21ea MK |
793 | |
794 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
795 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { | |
796 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); | |
797 | } | |
798 | else { | |
4e926d2d TR |
799 | DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", |
800 | pipe, vpos); | |
c55d21ea MK |
801 | |
802 | /* Bump counter if we are at >= leading edge of vblank, | |
803 | * but before vsync where vpos would turn negative and | |
804 | * the hw counter really increments. | |
805 | */ | |
806 | if (vpos >= 0) | |
807 | count++; | |
808 | } | |
809 | } | |
810 | else { | |
811 | /* Fallback to use value as is. */ | |
4e926d2d | 812 | count = radeon_get_vblank_counter(rdev, pipe); |
c55d21ea MK |
813 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); |
814 | } | |
815 | ||
816 | return count; | |
771fe6b9 JG |
817 | } |
818 | ||
f482a141 AD |
819 | /** |
820 | * radeon_enable_vblank_kms - enable vblank interrupt | |
821 | * | |
822 | * @dev: drm dev pointer | |
823 | * @crtc: crtc to enable vblank interrupt for | |
824 | * | |
825 | * Enable the interrupt on the requested crtc (all asics). | |
826 | * Returns 0 on success, -EINVAL on failure. | |
827 | */ | |
771fe6b9 JG |
828 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
829 | { | |
7ed220d7 | 830 | struct radeon_device *rdev = dev->dev_private; |
fb98257a CK |
831 | unsigned long irqflags; |
832 | int r; | |
7ed220d7 | 833 | |
9c950a43 | 834 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
835 | DRM_ERROR("Invalid crtc %d\n", crtc); |
836 | return -EINVAL; | |
837 | } | |
838 | ||
fb98257a | 839 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 840 | rdev->irq.crtc_vblank_int[crtc] = true; |
fb98257a CK |
841 | r = radeon_irq_set(rdev); |
842 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); | |
843 | return r; | |
771fe6b9 JG |
844 | } |
845 | ||
f482a141 AD |
846 | /** |
847 | * radeon_disable_vblank_kms - disable vblank interrupt | |
848 | * | |
849 | * @dev: drm dev pointer | |
850 | * @crtc: crtc to disable vblank interrupt for | |
851 | * | |
852 | * Disable the interrupt on the requested crtc (all asics). | |
853 | */ | |
771fe6b9 JG |
854 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
855 | { | |
7ed220d7 | 856 | struct radeon_device *rdev = dev->dev_private; |
fb98257a | 857 | unsigned long irqflags; |
7ed220d7 | 858 | |
9c950a43 | 859 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
7ed220d7 MD |
860 | DRM_ERROR("Invalid crtc %d\n", crtc); |
861 | return; | |
862 | } | |
863 | ||
fb98257a | 864 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
7ed220d7 | 865 | rdev->irq.crtc_vblank_int[crtc] = false; |
7ed220d7 | 866 | radeon_irq_set(rdev); |
fb98257a | 867 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
771fe6b9 JG |
868 | } |
869 | ||
f482a141 AD |
870 | /** |
871 | * radeon_get_vblank_timestamp_kms - get vblank timestamp | |
872 | * | |
873 | * @dev: drm dev pointer | |
874 | * @crtc: crtc to get the timestamp for | |
875 | * @max_error: max error | |
876 | * @vblank_time: time value | |
877 | * @flags: flags passed to the driver | |
878 | * | |
879 | * Gets the timestamp on the requested crtc based on the | |
880 | * scanout position. (all asics). | |
881 | * Returns postive status flags on success, negative error on failure. | |
882 | */ | |
f5a80209 MK |
883 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
884 | int *max_error, | |
885 | struct timeval *vblank_time, | |
886 | unsigned flags) | |
887 | { | |
888 | struct drm_crtc *drmcrtc; | |
889 | struct radeon_device *rdev = dev->dev_private; | |
890 | ||
891 | if (crtc < 0 || crtc >= dev->num_crtcs) { | |
892 | DRM_ERROR("Invalid crtc %d\n", crtc); | |
893 | return -EINVAL; | |
894 | } | |
895 | ||
896 | /* Get associated drm_crtc: */ | |
897 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; | |
f5475cc4 PM |
898 | if (!drmcrtc) |
899 | return -EINVAL; | |
f5a80209 MK |
900 | |
901 | /* Helper routine in DRM core does all the work: */ | |
902 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, | |
903 | vblank_time, flags, | |
eba1f35d | 904 | &drmcrtc->hwmode); |
f5a80209 | 905 | } |
771fe6b9 | 906 | |
baa70943 | 907 | const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
4b63539b DV |
908 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
909 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
910 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
911 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
912 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), | |
913 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), | |
914 | DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), | |
915 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), | |
916 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), | |
917 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), | |
918 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), | |
919 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), | |
920 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), | |
921 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), | |
922 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
923 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), | |
924 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), | |
925 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), | |
926 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), | |
927 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), | |
928 | DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), | |
929 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
930 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), | |
931 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), | |
932 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), | |
933 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), | |
934 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), | |
771fe6b9 | 935 | /* KMS */ |
f8c47144 DV |
936 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
937 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
938 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
939 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
940 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), | |
941 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), | |
942 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
943 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
944 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
945 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
946 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
947 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
948 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
949 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
950 | DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
771fe6b9 | 951 | }; |
f95aeb17 | 952 | int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); |