Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and | |
3 | * VA Linux Systems Inc., Fremont, California. | |
4 | * Copyright 2008 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Original Authors: | |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane | |
26 | * | |
27 | * Kernel port Author: Dave Airlie | |
28 | */ | |
29 | ||
30 | #ifndef RADEON_MODE_H | |
31 | #define RADEON_MODE_H | |
32 | ||
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_edid.h> | |
35 | #include <drm/drm_dp_helper.h> | |
9843ead0 | 36 | #include <drm/drm_dp_mst_helper.h> |
760285e7 DH |
37 | #include <drm/drm_fixed.h> |
38 | #include <drm/drm_crtc_helper.h> | |
771fe6b9 | 39 | #include <linux/i2c.h> |
771fe6b9 | 40 | #include <linux/i2c-algo-bit.h> |
c93bb85b | 41 | |
38651674 | 42 | struct radeon_bo; |
c93bb85b | 43 | struct radeon_device; |
771fe6b9 JG |
44 | |
45 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) | |
46 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) | |
47 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) | |
48 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) | |
49 | ||
88f39063 SB |
50 | #define RADEON_MAX_HPD_PINS 7 |
51 | #define RADEON_MAX_CRTCS 6 | |
52 | #define RADEON_MAX_AFMT_BLOCKS 7 | |
53 | ||
771fe6b9 JG |
54 | enum radeon_rmx_type { |
55 | RMX_OFF, | |
56 | RMX_FULL, | |
57 | RMX_CENTER, | |
58 | RMX_ASPECT | |
59 | }; | |
60 | ||
61 | enum radeon_tv_std { | |
62 | TV_STD_NTSC, | |
63 | TV_STD_PAL, | |
64 | TV_STD_PAL_M, | |
65 | TV_STD_PAL_60, | |
66 | TV_STD_NTSC_J, | |
67 | TV_STD_SCART_PAL, | |
68 | TV_STD_SECAM, | |
69 | TV_STD_PAL_CN, | |
d79766fa | 70 | TV_STD_PAL_N, |
771fe6b9 JG |
71 | }; |
72 | ||
5b1714d3 AD |
73 | enum radeon_underscan_type { |
74 | UNDERSCAN_OFF, | |
75 | UNDERSCAN_ON, | |
76 | UNDERSCAN_AUTO, | |
77 | }; | |
78 | ||
8e36ed00 AD |
79 | enum radeon_hpd_id { |
80 | RADEON_HPD_1 = 0, | |
81 | RADEON_HPD_2, | |
82 | RADEON_HPD_3, | |
83 | RADEON_HPD_4, | |
84 | RADEON_HPD_5, | |
85 | RADEON_HPD_6, | |
86 | RADEON_HPD_NONE = 0xff, | |
87 | }; | |
88 | ||
67ba31d3 AD |
89 | enum radeon_output_csc { |
90 | RADEON_OUTPUT_CSC_BYPASS = 0, | |
91 | RADEON_OUTPUT_CSC_TVRGB = 1, | |
92 | RADEON_OUTPUT_CSC_YCBCR601 = 2, | |
93 | RADEON_OUTPUT_CSC_YCBCR709 = 3, | |
94 | }; | |
95 | ||
f376b94f AD |
96 | #define RADEON_MAX_I2C_BUS 16 |
97 | ||
9b9fe724 AD |
98 | /* radeon gpio-based i2c |
99 | * 1. "mask" reg and bits | |
100 | * grabs the gpio pins for software use | |
101 | * 0=not held 1=held | |
102 | * 2. "a" reg and bits | |
103 | * output pin value | |
104 | * 0=low 1=high | |
105 | * 3. "en" reg and bits | |
106 | * sets the pin direction | |
107 | * 0=input 1=output | |
108 | * 4. "y" reg and bits | |
109 | * input pin value | |
110 | * 0=low 1=high | |
111 | */ | |
771fe6b9 JG |
112 | struct radeon_i2c_bus_rec { |
113 | bool valid; | |
6a93cb25 AD |
114 | /* id used by atom */ |
115 | uint8_t i2c_id; | |
bcc1c2a1 | 116 | /* id used by atom */ |
8e36ed00 | 117 | enum radeon_hpd_id hpd; |
6a93cb25 AD |
118 | /* can be used with hw i2c engine */ |
119 | bool hw_capable; | |
120 | /* uses multi-media i2c engine */ | |
121 | bool mm_i2c; | |
122 | /* regs and bits */ | |
771fe6b9 JG |
123 | uint32_t mask_clk_reg; |
124 | uint32_t mask_data_reg; | |
125 | uint32_t a_clk_reg; | |
126 | uint32_t a_data_reg; | |
9b9fe724 AD |
127 | uint32_t en_clk_reg; |
128 | uint32_t en_data_reg; | |
129 | uint32_t y_clk_reg; | |
130 | uint32_t y_data_reg; | |
771fe6b9 JG |
131 | uint32_t mask_clk_mask; |
132 | uint32_t mask_data_mask; | |
771fe6b9 JG |
133 | uint32_t a_clk_mask; |
134 | uint32_t a_data_mask; | |
9b9fe724 AD |
135 | uint32_t en_clk_mask; |
136 | uint32_t en_data_mask; | |
137 | uint32_t y_clk_mask; | |
138 | uint32_t y_data_mask; | |
771fe6b9 JG |
139 | }; |
140 | ||
141 | struct radeon_tmds_pll { | |
142 | uint32_t freq; | |
143 | uint32_t value; | |
144 | }; | |
145 | ||
146 | #define RADEON_MAX_BIOS_CONNECTOR 16 | |
147 | ||
7c27f87d | 148 | /* pll flags */ |
771fe6b9 JG |
149 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
150 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) | |
151 | #define RADEON_PLL_USE_REF_DIV (1 << 2) | |
152 | #define RADEON_PLL_LEGACY (1 << 3) | |
153 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) | |
154 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) | |
155 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) | |
156 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) | |
157 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) | |
158 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | |
159 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | |
d0e275a9 | 160 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
fc10332b | 161 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
86cb2bbf | 162 | #define RADEON_PLL_IS_LCD (1 << 13) |
f523f74e | 163 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
771fe6b9 JG |
164 | |
165 | struct radeon_pll { | |
fc10332b AD |
166 | /* reference frequency */ |
167 | uint32_t reference_freq; | |
168 | ||
169 | /* fixed dividers */ | |
170 | uint32_t reference_div; | |
171 | uint32_t post_div; | |
172 | ||
173 | /* pll in/out limits */ | |
771fe6b9 JG |
174 | uint32_t pll_in_min; |
175 | uint32_t pll_in_max; | |
176 | uint32_t pll_out_min; | |
177 | uint32_t pll_out_max; | |
86cb2bbf AD |
178 | uint32_t lcd_pll_out_min; |
179 | uint32_t lcd_pll_out_max; | |
fc10332b | 180 | uint32_t best_vco; |
771fe6b9 | 181 | |
fc10332b | 182 | /* divider limits */ |
771fe6b9 JG |
183 | uint32_t min_ref_div; |
184 | uint32_t max_ref_div; | |
185 | uint32_t min_post_div; | |
186 | uint32_t max_post_div; | |
187 | uint32_t min_feedback_div; | |
188 | uint32_t max_feedback_div; | |
189 | uint32_t min_frac_feedback_div; | |
190 | uint32_t max_frac_feedback_div; | |
fc10332b AD |
191 | |
192 | /* flags for the current clock */ | |
193 | uint32_t flags; | |
194 | ||
195 | /* pll id */ | |
196 | uint32_t id; | |
771fe6b9 JG |
197 | }; |
198 | ||
199 | struct radeon_i2c_chan { | |
771fe6b9 | 200 | struct i2c_adapter adapter; |
746c1aa4 | 201 | struct drm_device *dev; |
379dfc25 | 202 | struct i2c_algo_bit_data bit; |
771fe6b9 | 203 | struct radeon_i2c_bus_rec rec; |
496263bf | 204 | struct drm_dp_aux aux; |
379dfc25 | 205 | bool has_aux; |
831719d6 | 206 | struct mutex mutex; |
771fe6b9 JG |
207 | }; |
208 | ||
209 | /* mostly for macs, but really any system without connector tables */ | |
210 | enum radeon_connector_table { | |
aa74fbb4 | 211 | CT_NONE = 0, |
771fe6b9 JG |
212 | CT_GENERIC, |
213 | CT_IBOOK, | |
214 | CT_POWERBOOK_EXTERNAL, | |
215 | CT_POWERBOOK_INTERNAL, | |
216 | CT_POWERBOOK_VGA, | |
217 | CT_MINI_EXTERNAL, | |
218 | CT_MINI_INTERNAL, | |
219 | CT_IMAC_G5_ISIGHT, | |
220 | CT_EMAC, | |
76a7142a | 221 | CT_RN50_POWER, |
aa74fbb4 | 222 | CT_MAC_X800, |
9fad321a | 223 | CT_MAC_G5_9600, |
cafa59b9 AD |
224 | CT_SAM440EP, |
225 | CT_MAC_G4_SILVER | |
771fe6b9 JG |
226 | }; |
227 | ||
fcec570b AD |
228 | enum radeon_dvo_chip { |
229 | DVO_SIL164, | |
230 | DVO_SIL1178, | |
231 | }; | |
232 | ||
8be48d92 | 233 | struct radeon_fbdev; |
38651674 | 234 | |
0783986a AD |
235 | struct radeon_afmt { |
236 | bool enabled; | |
237 | int offset; | |
238 | bool last_buffer_filled_status; | |
239 | int id; | |
240 | }; | |
241 | ||
771fe6b9 JG |
242 | struct radeon_mode_info { |
243 | struct atom_context *atom_context; | |
61c4b24b | 244 | struct card_info *atom_card_info; |
771fe6b9 JG |
245 | enum radeon_connector_table connector_table; |
246 | bool mode_config_initialized; | |
88f39063 SB |
247 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
248 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; | |
445282db DA |
249 | /* DVI-I properties */ |
250 | struct drm_property *coherent_mode_property; | |
251 | /* DAC enable load detect */ | |
252 | struct drm_property *load_detect_property; | |
5b1714d3 | 253 | /* TV standard */ |
445282db DA |
254 | struct drm_property *tv_std_property; |
255 | /* legacy TMDS PLL detect */ | |
256 | struct drm_property *tmds_pll_property; | |
5b1714d3 AD |
257 | /* underscan */ |
258 | struct drm_property *underscan_property; | |
5bccf5e3 MG |
259 | struct drm_property *underscan_hborder_property; |
260 | struct drm_property *underscan_vborder_property; | |
8666c076 AD |
261 | /* audio */ |
262 | struct drm_property *audio_property; | |
6214bb74 AD |
263 | /* FMT dithering */ |
264 | struct drm_property *dither_property; | |
67ba31d3 AD |
265 | /* Output CSC */ |
266 | struct drm_property *output_csc_property; | |
3c537889 AD |
267 | /* hardcoded DFP edid from BIOS */ |
268 | struct edid *bios_hardcoded_edid; | |
fafcf94e | 269 | int bios_hardcoded_edid_size; |
38651674 DA |
270 | |
271 | /* pointer to fbdev info structure */ | |
8be48d92 | 272 | struct radeon_fbdev *rfbdev; |
af7912e5 AD |
273 | /* firmware flags */ |
274 | u16 firmware_flags; | |
bced76f2 AD |
275 | /* pointer to backlight encoder */ |
276 | struct radeon_encoder *bl_encoder; | |
8f0fc088 DA |
277 | |
278 | /* bitmask for active encoder frontends */ | |
279 | uint32_t active_encoders; | |
c93bb85b JG |
280 | }; |
281 | ||
91030880 AD |
282 | #define RADEON_MAX_BL_LEVEL 0xFF |
283 | ||
bced76f2 AD |
284 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
285 | ||
91030880 AD |
286 | struct radeon_backlight_privdata { |
287 | struct radeon_encoder *encoder; | |
288 | uint8_t negative; | |
289 | }; | |
290 | ||
291 | #endif | |
292 | ||
4ce001ab DA |
293 | #define MAX_H_CODE_TIMING_LEN 32 |
294 | #define MAX_V_CODE_TIMING_LEN 32 | |
295 | ||
296 | /* need to store these as reading | |
297 | back code tables is excessive */ | |
298 | struct radeon_tv_regs { | |
299 | uint32_t tv_uv_adr; | |
300 | uint32_t timing_cntl; | |
301 | uint32_t hrestart; | |
302 | uint32_t vrestart; | |
303 | uint32_t frestart; | |
304 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; | |
305 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; | |
306 | }; | |
307 | ||
19eca43e AD |
308 | struct radeon_atom_ss { |
309 | uint16_t percentage; | |
18f8f52b | 310 | uint16_t percentage_divider; |
19eca43e AD |
311 | uint8_t type; |
312 | uint16_t step; | |
313 | uint8_t delay; | |
314 | uint8_t range; | |
315 | uint8_t refdiv; | |
316 | /* asic_ss */ | |
317 | uint16_t rate; | |
318 | uint16_t amount; | |
319 | }; | |
320 | ||
a2b6d3b3 MD |
321 | enum radeon_flip_status { |
322 | RADEON_FLIP_NONE, | |
323 | RADEON_FLIP_PENDING, | |
324 | RADEON_FLIP_SUBMITTED | |
325 | }; | |
326 | ||
771fe6b9 JG |
327 | struct radeon_crtc { |
328 | struct drm_crtc base; | |
329 | int crtc_id; | |
330 | u16 lut_r[256], lut_g[256], lut_b[256]; | |
331 | bool enabled; | |
332 | bool can_tile; | |
333 | uint32_t crtc_offset; | |
771fe6b9 JG |
334 | struct drm_gem_object *cursor_bo; |
335 | uint64_t cursor_addr; | |
78b1a601 MD |
336 | int cursor_x; |
337 | int cursor_y; | |
338 | int cursor_hot_x; | |
339 | int cursor_hot_y; | |
771fe6b9 JG |
340 | int cursor_width; |
341 | int cursor_height; | |
9e05fa1d AD |
342 | int max_cursor_width; |
343 | int max_cursor_height; | |
4162338a | 344 | uint32_t legacy_display_base_addr; |
c93bb85b | 345 | enum radeon_rmx_type rmx_type; |
5b1714d3 AD |
346 | u8 h_border; |
347 | u8 v_border; | |
c93bb85b JG |
348 | fixed20_12 vsc; |
349 | fixed20_12 hsc; | |
de2103e4 | 350 | struct drm_display_mode native_mode; |
bcc1c2a1 | 351 | int pll_id; |
6f34be50 | 352 | /* page flipping */ |
fa7f517c CK |
353 | struct workqueue_struct *flip_queue; |
354 | struct radeon_flip_work *flip_work; | |
a2b6d3b3 | 355 | enum radeon_flip_status flip_status; |
19eca43e AD |
356 | /* pll sharing */ |
357 | struct radeon_atom_ss ss; | |
358 | bool ss_enabled; | |
359 | u32 adjusted_clock; | |
360 | int bpc; | |
361 | u32 pll_reference_div; | |
362 | u32 pll_post_div; | |
363 | u32 pll_flags; | |
5df3196b | 364 | struct drm_encoder *encoder; |
57b35e29 | 365 | struct drm_connector *connector; |
7178d2a6 AD |
366 | /* for dpm */ |
367 | u32 line_time; | |
368 | u32 wm_low; | |
369 | u32 wm_high; | |
5b5561b3 | 370 | u32 lb_vblank_lead_lines; |
66edc1c9 | 371 | struct drm_display_mode hw_mode; |
643b1f56 | 372 | enum radeon_output_csc output_csc; |
771fe6b9 JG |
373 | }; |
374 | ||
375 | struct radeon_encoder_primary_dac { | |
376 | /* legacy primary dac */ | |
377 | uint32_t ps2_pdac_adj; | |
378 | }; | |
379 | ||
380 | struct radeon_encoder_lvds { | |
381 | /* legacy lvds */ | |
382 | uint16_t panel_vcc_delay; | |
383 | uint8_t panel_pwr_delay; | |
384 | uint8_t panel_digon_delay; | |
385 | uint8_t panel_blon_delay; | |
386 | uint16_t panel_ref_divider; | |
387 | uint8_t panel_post_divider; | |
388 | uint16_t panel_fb_divider; | |
389 | bool use_bios_dividers; | |
390 | uint32_t lvds_gen_cntl; | |
391 | /* panel mode */ | |
de2103e4 | 392 | struct drm_display_mode native_mode; |
63ec0119 MD |
393 | struct backlight_device *bl_dev; |
394 | int dpms_mode; | |
395 | uint8_t backlight_level; | |
771fe6b9 JG |
396 | }; |
397 | ||
398 | struct radeon_encoder_tv_dac { | |
399 | /* legacy tv dac */ | |
400 | uint32_t ps2_tvdac_adj; | |
401 | uint32_t ntsc_tvdac_adj; | |
402 | uint32_t pal_tvdac_adj; | |
403 | ||
4ce001ab DA |
404 | int h_pos; |
405 | int v_pos; | |
406 | int h_size; | |
407 | int supported_tv_stds; | |
408 | bool tv_on; | |
771fe6b9 | 409 | enum radeon_tv_std tv_std; |
4ce001ab | 410 | struct radeon_tv_regs tv; |
771fe6b9 JG |
411 | }; |
412 | ||
413 | struct radeon_encoder_int_tmds { | |
414 | /* legacy int tmds */ | |
415 | struct radeon_tmds_pll tmds_pll[4]; | |
416 | }; | |
417 | ||
fcec570b AD |
418 | struct radeon_encoder_ext_tmds { |
419 | /* tmds over dvo */ | |
420 | struct radeon_i2c_chan *i2c_bus; | |
421 | uint8_t slave_addr; | |
422 | enum radeon_dvo_chip dvo_chip; | |
423 | }; | |
424 | ||
ebbe1cb9 | 425 | /* spread spectrum */ |
771fe6b9 | 426 | struct radeon_encoder_atom_dig { |
5137ee94 | 427 | bool linkb; |
771fe6b9 JG |
428 | /* atom dig */ |
429 | bool coherent_mode; | |
ba032a58 AD |
430 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
431 | /* atom lvds/edp */ | |
432 | uint32_t lcd_misc; | |
771fe6b9 | 433 | uint16_t panel_pwr_delay; |
ba032a58 | 434 | uint32_t lcd_ss_id; |
771fe6b9 | 435 | /* panel mode */ |
de2103e4 | 436 | struct drm_display_mode native_mode; |
63ec0119 MD |
437 | struct backlight_device *bl_dev; |
438 | int dpms_mode; | |
439 | uint8_t backlight_level; | |
386d4d75 | 440 | int panel_mode; |
0783986a | 441 | struct radeon_afmt *afmt; |
d0ea397e | 442 | struct r600_audio_pin *pin; |
9843ead0 | 443 | int active_mst_links; |
771fe6b9 JG |
444 | }; |
445 | ||
4ce001ab DA |
446 | struct radeon_encoder_atom_dac { |
447 | enum radeon_tv_std tv_std; | |
448 | }; | |
449 | ||
9843ead0 DA |
450 | struct radeon_encoder_mst { |
451 | int crtc; | |
452 | struct radeon_encoder *primary; | |
453 | struct radeon_connector *connector; | |
454 | struct drm_dp_mst_port *port; | |
455 | int pbn; | |
456 | int fe; | |
457 | bool fe_from_be; | |
458 | bool enc_active; | |
459 | }; | |
460 | ||
771fe6b9 JG |
461 | struct radeon_encoder { |
462 | struct drm_encoder base; | |
5137ee94 | 463 | uint32_t encoder_enum; |
771fe6b9 JG |
464 | uint32_t encoder_id; |
465 | uint32_t devices; | |
4ce001ab | 466 | uint32_t active_device; |
771fe6b9 JG |
467 | uint32_t flags; |
468 | uint32_t pixel_clock; | |
469 | enum radeon_rmx_type rmx_type; | |
5b1714d3 | 470 | enum radeon_underscan_type underscan_type; |
5bccf5e3 MG |
471 | uint32_t underscan_hborder; |
472 | uint32_t underscan_vborder; | |
de2103e4 | 473 | struct drm_display_mode native_mode; |
771fe6b9 | 474 | void *enc_priv; |
58bd0863 | 475 | int audio_polling_active; |
3e4b9982 | 476 | bool is_ext_encoder; |
36868bda | 477 | u16 caps; |
1a626b68 | 478 | struct radeon_audio_funcs *audio; |
643b1f56 | 479 | enum radeon_output_csc output_csc; |
9843ead0 DA |
480 | bool can_mst; |
481 | uint32_t offset; | |
482 | bool is_mst_encoder; | |
483 | /* front end for this mst encoder */ | |
771fe6b9 JG |
484 | }; |
485 | ||
486 | struct radeon_connector_atom_dig { | |
487 | uint32_t igp_lane_info; | |
4143e919 | 488 | /* displayport */ |
1a644cd4 | 489 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
4143e919 | 490 | u8 dp_sink_type; |
5801ead6 AD |
491 | int dp_clock; |
492 | int dp_lane_count; | |
8b834852 | 493 | bool edp_on; |
9843ead0 | 494 | bool is_mst; |
771fe6b9 JG |
495 | }; |
496 | ||
eed45b30 AD |
497 | struct radeon_gpio_rec { |
498 | bool valid; | |
499 | u8 id; | |
500 | u32 reg; | |
501 | u32 mask; | |
727b3d25 | 502 | u32 shift; |
eed45b30 AD |
503 | }; |
504 | ||
eed45b30 AD |
505 | struct radeon_hpd { |
506 | enum radeon_hpd_id hpd; | |
507 | u8 plugged_state; | |
508 | struct radeon_gpio_rec gpio; | |
509 | }; | |
510 | ||
26b5bc98 | 511 | struct radeon_router { |
26b5bc98 AD |
512 | u32 router_id; |
513 | struct radeon_i2c_bus_rec i2c_info; | |
514 | u8 i2c_addr; | |
fb939dfc AD |
515 | /* i2c mux */ |
516 | bool ddc_valid; | |
517 | u8 ddc_mux_type; | |
518 | u8 ddc_mux_control_pin; | |
519 | u8 ddc_mux_state; | |
520 | /* clock/data mux */ | |
521 | bool cd_valid; | |
522 | u8 cd_mux_type; | |
523 | u8 cd_mux_control_pin; | |
524 | u8 cd_mux_state; | |
26b5bc98 AD |
525 | }; |
526 | ||
8666c076 AD |
527 | enum radeon_connector_audio { |
528 | RADEON_AUDIO_DISABLE = 0, | |
529 | RADEON_AUDIO_ENABLE = 1, | |
530 | RADEON_AUDIO_AUTO = 2 | |
531 | }; | |
532 | ||
6214bb74 AD |
533 | enum radeon_connector_dither { |
534 | RADEON_FMT_DITHER_DISABLE = 0, | |
535 | RADEON_FMT_DITHER_ENABLE = 1, | |
536 | }; | |
537 | ||
9843ead0 DA |
538 | struct stream_attribs { |
539 | uint16_t fe; | |
540 | uint16_t slots; | |
541 | }; | |
542 | ||
771fe6b9 JG |
543 | struct radeon_connector { |
544 | struct drm_connector base; | |
545 | uint32_t connector_id; | |
546 | uint32_t devices; | |
547 | struct radeon_i2c_chan *ddc_bus; | |
5b1714d3 | 548 | /* some systems have an hdmi and vga port with a shared ddc line */ |
0294cf4f | 549 | bool shared_ddc; |
4ce001ab DA |
550 | bool use_digital; |
551 | /* we need to mind the EDID between detect | |
552 | and get modes due to analog/digital/tvencoder */ | |
553 | struct edid *edid; | |
771fe6b9 | 554 | void *con_priv; |
445282db | 555 | bool dac_load_detect; |
d0d0a225 | 556 | bool detected_by_load; /* if the connection status was determined by load */ |
cb5d4166 | 557 | bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ |
b75fad06 | 558 | uint16_t connector_object_id; |
eed45b30 | 559 | struct radeon_hpd hpd; |
26b5bc98 AD |
560 | struct radeon_router router; |
561 | struct radeon_i2c_chan *router_bus; | |
8666c076 | 562 | enum radeon_connector_audio audio; |
6214bb74 | 563 | enum radeon_connector_dither dither; |
ea292861 | 564 | int pixelclock_for_modeset; |
9843ead0 DA |
565 | bool is_mst_connector; |
566 | struct radeon_connector *mst_port; | |
567 | struct drm_dp_mst_port *port; | |
568 | struct drm_dp_mst_topology_mgr mst_mgr; | |
569 | ||
570 | struct radeon_encoder *mst_encoder; | |
571 | struct stream_attribs cur_stream_attribs[6]; | |
572 | int enabled_attribs; | |
771fe6b9 JG |
573 | }; |
574 | ||
575 | struct radeon_framebuffer { | |
576 | struct drm_framebuffer base; | |
577 | struct drm_gem_object *obj; | |
578 | }; | |
579 | ||
996d5c59 AD |
580 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
581 | ((em) == ATOM_ENCODER_MODE_DP_MST)) | |
6383cf7d | 582 | |
7062ab67 CK |
583 | struct atom_clock_dividers { |
584 | u32 post_div; | |
585 | union { | |
586 | struct { | |
587 | #ifdef __BIG_ENDIAN | |
588 | u32 reserved : 6; | |
589 | u32 whole_fb_div : 12; | |
590 | u32 frac_fb_div : 14; | |
591 | #else | |
592 | u32 frac_fb_div : 14; | |
593 | u32 whole_fb_div : 12; | |
594 | u32 reserved : 6; | |
595 | #endif | |
596 | }; | |
597 | u32 fb_div; | |
598 | }; | |
599 | u32 ref_div; | |
600 | bool enable_post_div; | |
601 | bool enable_dithen; | |
602 | u32 vco_mode; | |
603 | u32 real_clock; | |
9219ed65 AD |
604 | /* added for CI */ |
605 | u32 post_divider; | |
606 | u32 flags; | |
7062ab67 CK |
607 | }; |
608 | ||
eaa778af AD |
609 | struct atom_mpll_param { |
610 | union { | |
611 | struct { | |
612 | #ifdef __BIG_ENDIAN | |
613 | u32 reserved : 8; | |
614 | u32 clkfrac : 12; | |
615 | u32 clkf : 12; | |
616 | #else | |
617 | u32 clkf : 12; | |
618 | u32 clkfrac : 12; | |
619 | u32 reserved : 8; | |
620 | #endif | |
621 | }; | |
622 | u32 fb_div; | |
623 | }; | |
624 | u32 post_div; | |
625 | u32 bwcntl; | |
626 | u32 dll_speed; | |
627 | u32 vco_mode; | |
628 | u32 yclk_sel; | |
629 | u32 qdr; | |
630 | u32 half_rate; | |
631 | }; | |
632 | ||
ae5b0abb AD |
633 | #define MEM_TYPE_GDDR5 0x50 |
634 | #define MEM_TYPE_GDDR4 0x40 | |
635 | #define MEM_TYPE_GDDR3 0x30 | |
636 | #define MEM_TYPE_DDR2 0x20 | |
637 | #define MEM_TYPE_GDDR1 0x10 | |
638 | #define MEM_TYPE_DDR3 0xb0 | |
639 | #define MEM_TYPE_MASK 0xf0 | |
640 | ||
641 | struct atom_memory_info { | |
642 | u8 mem_vendor; | |
643 | u8 mem_type; | |
644 | }; | |
645 | ||
646 | #define MAX_AC_TIMING_ENTRIES 16 | |
647 | ||
648 | struct atom_memory_clock_range_table | |
649 | { | |
650 | u8 num_entries; | |
651 | u8 rsv[3]; | |
652 | u32 mclk[MAX_AC_TIMING_ENTRIES]; | |
653 | }; | |
654 | ||
655 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 | |
656 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 | |
657 | ||
658 | struct atom_mc_reg_entry { | |
659 | u32 mclk_max; | |
660 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
661 | }; | |
662 | ||
663 | struct atom_mc_register_address { | |
664 | u16 s1; | |
665 | u8 pre_reg_data; | |
666 | }; | |
667 | ||
668 | struct atom_mc_reg_table { | |
669 | u8 last; | |
670 | u8 num_entries; | |
671 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; | |
672 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; | |
673 | }; | |
674 | ||
675 | #define MAX_VOLTAGE_ENTRIES 32 | |
676 | ||
677 | struct atom_voltage_table_entry | |
678 | { | |
679 | u16 value; | |
680 | u32 smio_low; | |
681 | }; | |
682 | ||
683 | struct atom_voltage_table | |
684 | { | |
685 | u32 count; | |
686 | u32 mask_low; | |
65171944 | 687 | u32 phase_delay; |
ae5b0abb AD |
688 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
689 | }; | |
690 | ||
5b5561b3 MK |
691 | /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ |
692 | #define USE_REAL_VBLANKSTART (1 << 30) | |
693 | #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) | |
a38eab52 RK |
694 | |
695 | extern void | |
696 | radeon_add_atom_connector(struct drm_device *dev, | |
697 | uint32_t connector_id, | |
698 | uint32_t supported_device, | |
699 | int connector_type, | |
700 | struct radeon_i2c_bus_rec *i2c_bus, | |
701 | uint32_t igp_lane_info, | |
702 | uint16_t connector_object_id, | |
703 | struct radeon_hpd *hpd, | |
704 | struct radeon_router *router); | |
705 | extern void | |
706 | radeon_add_legacy_connector(struct drm_device *dev, | |
707 | uint32_t connector_id, | |
708 | uint32_t supported_device, | |
709 | int connector_type, | |
710 | struct radeon_i2c_bus_rec *i2c_bus, | |
711 | uint16_t connector_object_id, | |
712 | struct radeon_hpd *hpd); | |
0091fc13 RK |
713 | extern uint32_t |
714 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, | |
715 | uint8_t dac); | |
716 | extern void radeon_link_encoder_connector(struct drm_device *dev); | |
a38eab52 | 717 | |
d79766fa AD |
718 | extern enum radeon_tv_std |
719 | radeon_combios_get_tv_info(struct radeon_device *rdev); | |
720 | extern enum radeon_tv_std | |
721 | radeon_atombios_get_tv_info(struct radeon_device *rdev); | |
4a6369e9 | 722 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
2abba66e | 723 | u16 *vddc, u16 *vddci, u16 *mvdd); |
d79766fa | 724 | |
84ac68e0 AD |
725 | extern void |
726 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |
727 | struct drm_encoder *encoder, | |
728 | bool connected); | |
729 | extern void | |
730 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |
731 | struct drm_encoder *encoder, | |
732 | bool connected); | |
733 | ||
5b1714d3 AD |
734 | extern struct drm_connector * |
735 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); | |
9aa59993 AD |
736 | extern struct drm_connector * |
737 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); | |
738 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, | |
739 | u32 pixel_clock); | |
5b1714d3 | 740 | |
1d33e1fc AD |
741 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
742 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); | |
d7fa8bb3 | 743 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
eccea792 | 744 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
d7fa8bb3 | 745 | |
377bd8a9 AD |
746 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
747 | ||
d4877cf2 | 748 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
224d94b1 | 749 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
750 | struct drm_display_mode *mode); |
751 | extern void radeon_dp_set_link_config(struct drm_connector *connector, | |
e811f5ae | 752 | const struct drm_display_mode *mode); |
224d94b1 AD |
753 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
754 | struct drm_connector *connector); | |
d5811e87 | 755 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
4143e919 | 756 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
9fa05c98 | 757 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
386d4d75 AD |
758 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
759 | struct drm_connector *connector); | |
092c96a8 AD |
760 | extern int radeon_dp_get_dp_link_config(struct drm_connector *connector, |
761 | const u8 *dpcd, | |
762 | unsigned pix_clock, | |
763 | unsigned *dp_lanes, unsigned *dp_rate); | |
2953da15 AD |
764 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
765 | u8 power_state); | |
496263bf | 766 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
875711f0 DA |
767 | extern ssize_t |
768 | radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); | |
769 | ||
558e27db | 770 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
bf071900 | 771 | extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); |
ac89af1e | 772 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
f3f1f03e | 773 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
5801ead6 AD |
774 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
775 | int action, uint8_t lane_num, | |
776 | uint8_t lane_set); | |
bf071900 DA |
777 | extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, |
778 | int action, uint8_t lane_num, | |
779 | uint8_t lane_set, int fe); | |
9843ead0 DA |
780 | extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, |
781 | int fe); | |
591a10e1 | 782 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
3f03ced8 | 783 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
4cf3b494 | 784 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
746c1aa4 | 785 | |
f376b94f AD |
786 | extern void radeon_i2c_init(struct radeon_device *rdev); |
787 | extern void radeon_i2c_fini(struct radeon_device *rdev); | |
788 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); | |
789 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); | |
790 | extern void radeon_i2c_add(struct radeon_device *rdev, | |
791 | struct radeon_i2c_bus_rec *rec, | |
792 | const char *name); | |
793 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |
794 | struct radeon_i2c_bus_rec *i2c_bus); | |
771fe6b9 JG |
795 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
796 | struct radeon_i2c_bus_rec *rec, | |
797 | const char *name); | |
798 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); | |
5a6f98f5 AD |
799 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
800 | u8 slave_addr, | |
801 | u8 addr, | |
802 | u8 *val); | |
803 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, | |
804 | u8 slave_addr, | |
805 | u8 addr, | |
806 | u8 val); | |
fb939dfc AD |
807 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
808 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); | |
0a9069d3 | 809 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
771fe6b9 | 810 | |
ba032a58 AD |
811 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
812 | struct radeon_atom_ss *ss, | |
813 | int id); | |
814 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, | |
815 | struct radeon_atom_ss *ss, | |
816 | int id, u32 clock); | |
09e619c0 AD |
817 | extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, |
818 | u8 id); | |
ba032a58 | 819 | |
f523f74e AD |
820 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
821 | uint64_t freq, | |
822 | uint32_t *dot_clock_p, | |
823 | uint32_t *fb_div_p, | |
824 | uint32_t *frac_fb_div_p, | |
825 | uint32_t *ref_div_p, | |
826 | uint32_t *post_div_p); | |
827 | ||
828 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | |
829 | u32 freq, | |
830 | u32 *dot_clock_p, | |
831 | u32 *fb_div_p, | |
832 | u32 *frac_fb_div_p, | |
833 | u32 *ref_div_p, | |
834 | u32 *post_div_p); | |
771fe6b9 | 835 | |
1f3b6a45 DA |
836 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
837 | ||
771fe6b9 JG |
838 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
839 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
840 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
841 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); | |
842 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); | |
99999aaa | 843 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
32f48ffe | 844 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
771fe6b9 | 845 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
2dafb74d | 846 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
4ce001ab | 847 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
d740a933 | 848 | extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); |
771fe6b9 JG |
849 | |
850 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); | |
851 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
852 | struct drm_framebuffer *old_fb); | |
4dd19b0d CB |
853 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
854 | struct drm_framebuffer *fb, | |
21c74a8e JW |
855 | int x, int y, |
856 | enum mode_set_atomic state); | |
771fe6b9 JG |
857 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
858 | struct drm_display_mode *mode, | |
859 | struct drm_display_mode *adjusted_mode, | |
860 | int x, int y, | |
861 | struct drm_framebuffer *old_fb); | |
862 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); | |
863 | ||
864 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
865 | struct drm_framebuffer *old_fb); | |
4dd19b0d CB |
866 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
867 | struct drm_framebuffer *fb, | |
21c74a8e JW |
868 | int x, int y, |
869 | enum mode_set_atomic state); | |
4dd19b0d CB |
870 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
871 | struct drm_framebuffer *fb, | |
872 | int x, int y, int atomic); | |
78b1a601 MD |
873 | extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, |
874 | struct drm_file *file_priv, | |
875 | uint32_t handle, | |
876 | uint32_t width, | |
877 | uint32_t height, | |
878 | int32_t hot_x, | |
879 | int32_t hot_y); | |
771fe6b9 JG |
880 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
881 | int x, int y); | |
6d3759fa | 882 | extern void radeon_cursor_reset(struct drm_crtc *crtc); |
771fe6b9 | 883 | |
88e72717 TR |
884 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
885 | unsigned int flags, int *vpos, int *hpos, | |
3bb403bf VS |
886 | ktime_t *stime, ktime_t *etime, |
887 | const struct drm_display_mode *mode); | |
6383cf7d | 888 | |
3c537889 AD |
889 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
890 | extern struct edid * | |
c324acd5 | 891 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
771fe6b9 JG |
892 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
893 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); | |
894 | extern struct radeon_encoder_atom_dig * | |
895 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); | |
fcec570b AD |
896 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
897 | struct radeon_encoder_int_tmds *tmds); | |
898 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |
899 | struct radeon_encoder_int_tmds *tmds); | |
900 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, | |
901 | struct radeon_encoder_int_tmds *tmds); | |
902 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, | |
903 | struct radeon_encoder_ext_tmds *tmds); | |
904 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, | |
905 | struct radeon_encoder_ext_tmds *tmds); | |
6fe7ac3f AD |
906 | extern struct radeon_encoder_primary_dac * |
907 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); | |
908 | extern struct radeon_encoder_tv_dac * | |
909 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
910 | extern struct radeon_encoder_lvds * |
911 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
912 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
913 | extern struct radeon_encoder_tv_dac * | |
914 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); | |
915 | extern struct radeon_encoder_primary_dac * | |
916 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); | |
fcec570b AD |
917 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
918 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); | |
771fe6b9 JG |
919 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
920 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); | |
921 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); | |
922 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); | |
f657c2a7 YZ |
923 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
924 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); | |
771fe6b9 JG |
925 | extern void |
926 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
927 | extern void | |
928 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
929 | extern void | |
930 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
931 | extern void | |
932 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
933 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
934 | u16 blue, int regno); | |
b8c00ac5 DA |
935 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
936 | u16 *blue, int regno); | |
aaefcd42 | 937 | int radeon_framebuffer_init(struct drm_device *dev, |
38651674 | 938 | struct radeon_framebuffer *rfb, |
1eb83451 | 939 | const struct drm_mode_fb_cmd2 *mode_cmd, |
38651674 | 940 | struct drm_gem_object *obj); |
771fe6b9 JG |
941 | |
942 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); | |
943 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); | |
944 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); | |
945 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
946 | struct radeon_crtc *radeon_crtc); | |
947 | void radeon_legacy_init_crtc(struct drm_device *dev, | |
948 | struct radeon_crtc *radeon_crtc); | |
771fe6b9 JG |
949 | |
950 | void radeon_get_clock_info(struct drm_device *dev); | |
951 | ||
952 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); | |
953 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); | |
954 | ||
771fe6b9 JG |
955 | void radeon_enc_destroy(struct drm_encoder *encoder); |
956 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); | |
957 | void radeon_combios_asic_init(struct drm_device *dev); | |
c93bb85b | 958 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
e811f5ae | 959 | const struct drm_display_mode *mode, |
c93bb85b | 960 | struct drm_display_mode *adjusted_mode); |
3515387b AD |
961 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
962 | struct drm_display_mode *adjusted_mode); | |
4ce001ab DA |
963 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
964 | ||
965 | /* legacy tv */ | |
966 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, | |
967 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, | |
968 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); | |
969 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, | |
970 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, | |
971 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); | |
972 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, | |
973 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, | |
974 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); | |
975 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, | |
976 | struct drm_display_mode *mode, | |
977 | struct drm_display_mode *adjusted_mode); | |
38651674 | 978 | |
134b480f AD |
979 | /* fmt blocks */ |
980 | void avivo_program_fmt(struct drm_encoder *encoder); | |
981 | void dce3_program_fmt(struct drm_encoder *encoder); | |
982 | void dce4_program_fmt(struct drm_encoder *encoder); | |
983 | void dce8_program_fmt(struct drm_encoder *encoder); | |
984 | ||
38651674 DA |
985 | /* fbdev layer */ |
986 | int radeon_fbdev_init(struct radeon_device *rdev); | |
987 | void radeon_fbdev_fini(struct radeon_device *rdev); | |
988 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); | |
38651674 | 989 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
8c70e1cd | 990 | void radeon_fbdev_restore_mode(struct radeon_device *rdev); |
eb1f8e4f DA |
991 | |
992 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); | |
6f34be50 | 993 | |
1a0e7918 | 994 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
bb26270e DA |
995 | |
996 | void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); | |
997 | void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); | |
998 | ||
6f34be50 AD |
999 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
1000 | ||
ff72145b | 1001 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
8f0fc088 | 1002 | |
9843ead0 DA |
1003 | /* mst */ |
1004 | int radeon_dp_mst_init(struct radeon_connector *radeon_connector); | |
1005 | int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); | |
1006 | int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); | |
1007 | int radeon_mst_debugfs_init(struct radeon_device *rdev); | |
1008 | void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); | |
1009 | ||
1010 | void radeon_setup_mst_connector(struct drm_device *dev); | |
1011 | ||
8f0fc088 DA |
1012 | int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); |
1013 | void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); | |
771fe6b9 | 1014 | #endif |