projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: allow PPLL sharing on non-DP displays
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
68adac5e 37#include <drm_fixed.h>
21c74a8e 38#include <drm_crtc_helper.h>
771fe6b9 39#include <linux/i2c.h>
771fe6b9 40#include <linux/i2c-algo-bit.h>
c93bb85b 41
38651674 42struct radeon_bo;
c93bb85b 43struct radeon_device;
771fe6b9
JG		 44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
771fe6b9
JG		 50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
d79766fa 66 TV_STD_PAL_N,
771fe6b9
JG		 67};
68
5b1714d3
AD		 69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
8e36ed00
AD		 75enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
f376b94f
AD		 85#define RADEON_MAX_I2C_BUS 16
86
9b9fe724
AD		 87/* radeon gpio-based i2c
88 * 1. "mask" reg and bits
89 * grabs the gpio pins for software use
90 * 0=not held 1=held
91 * 2. "a" reg and bits
92 * output pin value
93 * 0=low 1=high
94 * 3. "en" reg and bits
95 * sets the pin direction
96 * 0=input 1=output
97 * 4. "y" reg and bits
98 * input pin value
99 * 0=low 1=high
100 */
771fe6b9
JG		 101struct radeon_i2c_bus_rec {
102 bool valid;
6a93cb25
AD		 103 /* id used by atom */
104 uint8_t i2c_id;
bcc1c2a1 105 /* id used by atom */
8e36ed00 106 enum radeon_hpd_id hpd;
6a93cb25
AD		 107 /* can be used with hw i2c engine */
108 bool hw_capable;
109 /* uses multi-media i2c engine */
110 bool mm_i2c;
111 /* regs and bits */
771fe6b9
JG		 112 uint32_t mask_clk_reg;
113 uint32_t mask_data_reg;
114 uint32_t a_clk_reg;
115 uint32_t a_data_reg;
9b9fe724
AD		 116 uint32_t en_clk_reg;
117 uint32_t en_data_reg;
118 uint32_t y_clk_reg;
119 uint32_t y_data_reg;
771fe6b9
JG		 120 uint32_t mask_clk_mask;
121 uint32_t mask_data_mask;
771fe6b9
JG		 122 uint32_t a_clk_mask;
123 uint32_t a_data_mask;
9b9fe724
AD		 124 uint32_t en_clk_mask;
125 uint32_t en_data_mask;
126 uint32_t y_clk_mask;
127 uint32_t y_data_mask;
771fe6b9
JG		 128};
129
130struct radeon_tmds_pll {
131 uint32_t freq;
132 uint32_t value;
133};
134
135#define RADEON_MAX_BIOS_CONNECTOR 16
136
7c27f87d 137/* pll flags */
771fe6b9
JG		 138#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3)
142#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
143#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
144#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
145#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
146#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
147#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
148#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 150#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 151#define RADEON_PLL_IS_LCD (1 << 13)
f523f74e 152#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
771fe6b9
JG		 153
154struct radeon_pll {
fc10332b
AD		 155 /* reference frequency */
156 uint32_t reference_freq;
157
158 /* fixed dividers */
159 uint32_t reference_div;
160 uint32_t post_div;
161
162 /* pll in/out limits */
771fe6b9
JG		 163 uint32_t pll_in_min;
164 uint32_t pll_in_max;
165 uint32_t pll_out_min;
166 uint32_t pll_out_max;
86cb2bbf
AD		 167 uint32_t lcd_pll_out_min;
168 uint32_t lcd_pll_out_max;
fc10332b 169 uint32_t best_vco;
771fe6b9 170
fc10332b 171 /* divider limits */
771fe6b9
JG		 172 uint32_t min_ref_div;
173 uint32_t max_ref_div;
174 uint32_t min_post_div;
175 uint32_t max_post_div;
176 uint32_t min_feedback_div;
177 uint32_t max_feedback_div;
178 uint32_t min_frac_feedback_div;
179 uint32_t max_frac_feedback_div;
fc10332b
AD		 180
181 /* flags for the current clock */
182 uint32_t flags;
183
184 /* pll id */
185 uint32_t id;
771fe6b9
JG		 186};
187
188struct radeon_i2c_chan {
771fe6b9 189 struct i2c_adapter adapter;
746c1aa4
DA		 190 struct drm_device *dev;
191 union {
ac1aade6 192 struct i2c_algo_bit_data bit;
746c1aa4 193 struct i2c_algo_dp_aux_data dp;
746c1aa4 194 } algo;
771fe6b9
JG		 195 struct radeon_i2c_bus_rec rec;
196};
197
198/* mostly for macs, but really any system without connector tables */
199enum radeon_connector_table {
aa74fbb4 200 CT_NONE = 0,
771fe6b9
JG		 201 CT_GENERIC,
202 CT_IBOOK,
203 CT_POWERBOOK_EXTERNAL,
204 CT_POWERBOOK_INTERNAL,
205 CT_POWERBOOK_VGA,
206 CT_MINI_EXTERNAL,
207 CT_MINI_INTERNAL,
208 CT_IMAC_G5_ISIGHT,
209 CT_EMAC,
76a7142a 210 CT_RN50_POWER,
aa74fbb4 211 CT_MAC_X800,
9fad321a 212 CT_MAC_G5_9600,
6a556039 213 CT_SAM440EP
771fe6b9
JG		 214};
215
fcec570b
AD		 216enum radeon_dvo_chip {
217 DVO_SIL164,
218 DVO_SIL1178,
219};
220
8be48d92 221struct radeon_fbdev;
38651674 222
0783986a
AD		 223struct radeon_afmt {
224 bool enabled;
225 int offset;
226 bool last_buffer_filled_status;
227 int id;
228};
229
771fe6b9
JG		 230struct radeon_mode_info {
231 struct atom_context *atom_context;
61c4b24b 232 struct card_info *atom_card_info;
771fe6b9
JG		 233 enum radeon_connector_table connector_table;
234 bool mode_config_initialized;
bcc1c2a1 235 struct radeon_crtc *crtcs[6];
0783986a 236 struct radeon_afmt *afmt[6];
445282db
DA		 237 /* DVI-I properties */
238 struct drm_property *coherent_mode_property;
239 /* DAC enable load detect */
240 struct drm_property *load_detect_property;
5b1714d3 241 /* TV standard */
445282db
DA		 242 struct drm_property *tv_std_property;
243 /* legacy TMDS PLL detect */
244 struct drm_property *tmds_pll_property;
5b1714d3
AD		 245 /* underscan */
246 struct drm_property *underscan_property;
5bccf5e3
MG		 247 struct drm_property *underscan_hborder_property;
248 struct drm_property *underscan_vborder_property;
3c537889
AD		 249 /* hardcoded DFP edid from BIOS */
250 struct edid *bios_hardcoded_edid;
fafcf94e 251 int bios_hardcoded_edid_size;
38651674
DA		 252
253 /* pointer to fbdev info structure */
8be48d92 254 struct radeon_fbdev *rfbdev;
af7912e5
AD		 255 /* firmware flags */
256 u16 firmware_flags;
c93bb85b
JG		 257};
258
91030880
AD		 259#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
260
261#define RADEON_MAX_BL_LEVEL 0xFF
262
263struct radeon_backlight_privdata {
264 struct radeon_encoder *encoder;
265 uint8_t negative;
266};
267
268#endif
269
4ce001ab
DA		 270#define MAX_H_CODE_TIMING_LEN 32
271#define MAX_V_CODE_TIMING_LEN 32
272
273/* need to store these as reading
274 back code tables is excessive */
275struct radeon_tv_regs {
276 uint32_t tv_uv_adr;
277 uint32_t timing_cntl;
278 uint32_t hrestart;
279 uint32_t vrestart;
280 uint32_t frestart;
281 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
282 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
283};
284
771fe6b9
JG		 285struct radeon_crtc {
286 struct drm_crtc base;
287 int crtc_id;
288 u16 lut_r[256], lut_g[256], lut_b[256];
289 bool enabled;
290 bool can_tile;
6c0ae2ab 291 bool in_mode_set;
771fe6b9 292 uint32_t crtc_offset;
771fe6b9
JG		 293 struct drm_gem_object *cursor_bo;
294 uint64_t cursor_addr;
295 int cursor_width;
296 int cursor_height;
4162338a 297 uint32_t legacy_display_base_addr;
c836e862 298 uint32_t legacy_cursor_offset;
c93bb85b 299 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 300 u8 h_border;
301 u8 v_border;
c93bb85b
JG		 302 fixed20_12 vsc;
303 fixed20_12 hsc;
de2103e4 304 struct drm_display_mode native_mode;
bcc1c2a1 305 int pll_id;
6f34be50
AD		 306 /* page flipping */
307 struct radeon_unpin_work *unpin_work;
308 int deferred_flip_completion;
771fe6b9
JG		 309};
310
311struct radeon_encoder_primary_dac {
312 /* legacy primary dac */
313 uint32_t ps2_pdac_adj;
314};
315
316struct radeon_encoder_lvds {
317 /* legacy lvds */
318 uint16_t panel_vcc_delay;
319 uint8_t panel_pwr_delay;
320 uint8_t panel_digon_delay;
321 uint8_t panel_blon_delay;
322 uint16_t panel_ref_divider;
323 uint8_t panel_post_divider;
324 uint16_t panel_fb_divider;
325 bool use_bios_dividers;
326 uint32_t lvds_gen_cntl;
327 /* panel mode */
de2103e4 328 struct drm_display_mode native_mode;
63ec0119
MD		 329 struct backlight_device *bl_dev;
330 int dpms_mode;
331 uint8_t backlight_level;
771fe6b9
JG		 332};
333
334struct radeon_encoder_tv_dac {
335 /* legacy tv dac */
336 uint32_t ps2_tvdac_adj;
337 uint32_t ntsc_tvdac_adj;
338 uint32_t pal_tvdac_adj;
339
4ce001ab
DA		 340 int h_pos;
341 int v_pos;
342 int h_size;
343 int supported_tv_stds;
344 bool tv_on;
771fe6b9 345 enum radeon_tv_std tv_std;
4ce001ab 346 struct radeon_tv_regs tv;
771fe6b9
JG		 347};
348
349struct radeon_encoder_int_tmds {
350 /* legacy int tmds */
351 struct radeon_tmds_pll tmds_pll[4];
352};
353
fcec570b
AD		 354struct radeon_encoder_ext_tmds {
355 /* tmds over dvo */
356 struct radeon_i2c_chan *i2c_bus;
357 uint8_t slave_addr;
358 enum radeon_dvo_chip dvo_chip;
359};
360
ebbe1cb9
AD		 361/* spread spectrum */
362struct radeon_atom_ss {
363 uint16_t percentage;
364 uint8_t type;
ba032a58 365 uint16_t step;
ebbe1cb9
AD		 366 uint8_t delay;
367 uint8_t range;
368 uint8_t refdiv;
ba032a58
AD		 369 /* asic_ss */
370 uint16_t rate;
371 uint16_t amount;
ebbe1cb9
AD		 372};
373
771fe6b9 374struct radeon_encoder_atom_dig {
5137ee94 375 bool linkb;
771fe6b9
JG		 376 /* atom dig */
377 bool coherent_mode;
ba032a58
AD		 378 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
379 /* atom lvds/edp */
380 uint32_t lcd_misc;
771fe6b9 381 uint16_t panel_pwr_delay;
ba032a58 382 uint32_t lcd_ss_id;
771fe6b9 383 /* panel mode */
de2103e4 384 struct drm_display_mode native_mode;
63ec0119
MD		 385 struct backlight_device *bl_dev;
386 int dpms_mode;
387 uint8_t backlight_level;
386d4d75 388 int panel_mode;
0783986a 389 struct radeon_afmt *afmt;
771fe6b9
JG		 390};
391
4ce001ab
DA		 392struct radeon_encoder_atom_dac {
393 enum radeon_tv_std tv_std;
394};
395
771fe6b9
JG		 396struct radeon_encoder {
397 struct drm_encoder base;
5137ee94 398 uint32_t encoder_enum;
771fe6b9
JG		 399 uint32_t encoder_id;
400 uint32_t devices;
4ce001ab 401 uint32_t active_device;
771fe6b9
JG		 402 uint32_t flags;
403 uint32_t pixel_clock;
404 enum radeon_rmx_type rmx_type;
5b1714d3 405 enum radeon_underscan_type underscan_type;
5bccf5e3
MG		 406 uint32_t underscan_hborder;
407 uint32_t underscan_vborder;
de2103e4 408 struct drm_display_mode native_mode;
771fe6b9 409 void *enc_priv;
58bd0863 410 int audio_polling_active;
3e4b9982 411 bool is_ext_encoder;
36868bda 412 u16 caps;
771fe6b9
JG		 413};
414
415struct radeon_connector_atom_dig {
416 uint32_t igp_lane_info;
4143e919 417 /* displayport */
746c1aa4 418 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 419 u8 dpcd[8];
4143e919 420 u8 dp_sink_type;
5801ead6
AD		 421 int dp_clock;
422 int dp_lane_count;
8b834852 423 bool edp_on;
771fe6b9
JG		 424};
425
eed45b30
AD		 426struct radeon_gpio_rec {
427 bool valid;
428 u8 id;
429 u32 reg;
430 u32 mask;
431};
432
eed45b30
AD		 433struct radeon_hpd {
434 enum radeon_hpd_id hpd;
435 u8 plugged_state;
436 struct radeon_gpio_rec gpio;
437};
438
26b5bc98 439struct radeon_router {
26b5bc98
AD		 440 u32 router_id;
441 struct radeon_i2c_bus_rec i2c_info;
442 u8 i2c_addr;
fb939dfc
AD		 443 /* i2c mux */
444 bool ddc_valid;
445 u8 ddc_mux_type;
446 u8 ddc_mux_control_pin;
447 u8 ddc_mux_state;
448 /* clock/data mux */
449 bool cd_valid;
450 u8 cd_mux_type;
451 u8 cd_mux_control_pin;
452 u8 cd_mux_state;
26b5bc98
AD		 453};
454
771fe6b9
JG		 455struct radeon_connector {
456 struct drm_connector base;
457 uint32_t connector_id;
458 uint32_t devices;
459 struct radeon_i2c_chan *ddc_bus;
5b1714d3 460 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 461 bool shared_ddc;
4ce001ab
DA		 462 bool use_digital;
463 /* we need to mind the EDID between detect
464 and get modes due to analog/digital/tvencoder */
465 struct edid *edid;
771fe6b9 466 void *con_priv;
445282db 467 bool dac_load_detect;
d0d0a225 468 bool detected_by_load; /* if the connection status was determined by load */
b75fad06 469 uint16_t connector_object_id;
eed45b30 470 struct radeon_hpd hpd;
26b5bc98
AD		 471 struct radeon_router router;
472 struct radeon_i2c_chan *router_bus;
771fe6b9
JG		 473};
474
475struct radeon_framebuffer {
476 struct drm_framebuffer base;
477 struct drm_gem_object *obj;
478};
479
996d5c59
AD		 480#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
481 ((em) == ATOM_ENCODER_MODE_DP_MST))
6383cf7d 482
d79766fa
AD		 483extern enum radeon_tv_std
484radeon_combios_get_tv_info(struct radeon_device *rdev);
485extern enum radeon_tv_std
486radeon_atombios_get_tv_info(struct radeon_device *rdev);
487
5b1714d3
AD		 488extern struct drm_connector *
489radeon_get_connector_for_encoder(struct drm_encoder *encoder);
9aa59993
AD		 490extern struct drm_connector *
491radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
492extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
493 u32 pixel_clock);
5b1714d3 494
1d33e1fc
AD		 495extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
496extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
d7fa8bb3
AD		 497extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
498extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
eccea792 499extern int radeon_get_monitor_bpc(struct drm_connector *connector);
d7fa8bb3 500
d4877cf2 501extern void radeon_connector_hotplug(struct drm_connector *connector);
224d94b1 502extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 503 struct drm_display_mode *mode);
504extern void radeon_dp_set_link_config(struct drm_connector *connector,
e811f5ae 505 const struct drm_display_mode *mode);
224d94b1
AD		 506extern void radeon_dp_link_train(struct drm_encoder *encoder,
507 struct drm_connector *connector);
d5811e87 508extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4143e919 509extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 510extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
386d4d75
AD		 511extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
512 struct drm_connector *connector);
558e27db 513extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
ac89af1e 514extern void radeon_atom_encoder_init(struct radeon_device *rdev);
f3f1f03e 515extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
5801ead6
AD		 516extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
517 int action, uint8_t lane_num,
518 uint8_t lane_set);
591a10e1 519extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
3f03ced8 520extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
746c1aa4 521extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
834b2904 522 u8 write_byte, u8 *read_byte);
746c1aa4 523
f376b94f
AD		 524extern void radeon_i2c_init(struct radeon_device *rdev);
525extern void radeon_i2c_fini(struct radeon_device *rdev);
526extern void radeon_combios_i2c_init(struct radeon_device *rdev);
527extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
528extern void radeon_i2c_add(struct radeon_device *rdev,
529 struct radeon_i2c_bus_rec *rec,
530 const char *name);
531extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
532 struct radeon_i2c_bus_rec *i2c_bus);
746c1aa4 533extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 534 struct radeon_i2c_bus_rec *rec,
535 const char *name);
771fe6b9
JG		 536extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
537 struct radeon_i2c_bus_rec *rec,
538 const char *name);
539extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 540extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
541 u8 slave_addr,
542 u8 addr,
543 u8 *val);
544extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
545 u8 slave_addr,
546 u8 addr,
547 u8 val);
fb939dfc
AD		 548extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
549extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
bc1c4dc3 550extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
771fe6b9
JG		 551extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
552
553extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
554
ba032a58
AD		 555extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
556 struct radeon_atom_ss *ss,
557 int id);
558extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
559 struct radeon_atom_ss *ss,
560 int id, u32 clock);
561
f523f74e
AD		 562extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
563 uint64_t freq,
564 uint32_t *dot_clock_p,
565 uint32_t *fb_div_p,
566 uint32_t *frac_fb_div_p,
567 uint32_t *ref_div_p,
568 uint32_t *post_div_p);
569
570extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
571 u32 freq,
572 u32 *dot_clock_p,
573 u32 *fb_div_p,
574 u32 *frac_fb_div_p,
575 u32 *ref_div_p,
576 u32 *post_div_p);
771fe6b9 577
1f3b6a45
DA		 578extern void radeon_setup_encoder_clones(struct drm_device *dev);
579
771fe6b9
JG		 580struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
581struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
582struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
583struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
584struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
99999aaa 585extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
32f48ffe 586extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 587extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
2dafb74d 588extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
4ce001ab 589extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 590
591extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
592extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
593 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 594extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
595 struct drm_framebuffer *fb,
21c74a8e
JW		 596 int x, int y,
597 enum mode_set_atomic state);
771fe6b9
JG		 598extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
599 struct drm_display_mode *mode,
600 struct drm_display_mode *adjusted_mode,
601 int x, int y,
602 struct drm_framebuffer *old_fb);
603extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
604
605extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
606 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 607extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
608 struct drm_framebuffer *fb,
21c74a8e
JW		 609 int x, int y,
610 enum mode_set_atomic state);
4dd19b0d
CB		 611extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
612 struct drm_framebuffer *fb,
613 int x, int y, int atomic);
771fe6b9
JG		 614extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
615 struct drm_file *file_priv,
616 uint32_t handle,
617 uint32_t width,
618 uint32_t height);
619extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
620 int x, int y);
621
f5a80209
MK		 622extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
623 int *vpos, int *hpos);
6383cf7d 624
3c537889
AD		 625extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
626extern struct edid *
c324acd5 627radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 628extern bool radeon_atom_get_clock_info(struct drm_device *dev);
629extern bool radeon_combios_get_clock_info(struct drm_device *dev);
630extern struct radeon_encoder_atom_dig *
631radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 632extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
633 struct radeon_encoder_int_tmds *tmds);
634extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
635 struct radeon_encoder_int_tmds *tmds);
636extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
637 struct radeon_encoder_int_tmds *tmds);
638extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
639 struct radeon_encoder_ext_tmds *tmds);
640extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
641 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 642extern struct radeon_encoder_primary_dac *
643radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
644extern struct radeon_encoder_tv_dac *
645radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 646extern struct radeon_encoder_lvds *
647radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 648extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
649extern struct radeon_encoder_tv_dac *
650radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
651extern struct radeon_encoder_primary_dac *
652radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 653extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
654extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 655extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
656extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
657extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
658extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 659extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
660extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 661extern void
662radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
663extern void
664radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
665extern void
666radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
667extern void
668radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
669extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
670 u16 blue, int regno);
b8c00ac5
DA		 671extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
672 u16 *blue, int regno);
aaefcd42 673int radeon_framebuffer_init(struct drm_device *dev,
38651674 674 struct radeon_framebuffer *rfb,
308e5bcb 675 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 676 struct drm_gem_object *obj);
771fe6b9
JG		 677
678int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
679bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
680bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
681void radeon_atombios_init_crtc(struct drm_device *dev,
682 struct radeon_crtc *radeon_crtc);
683void radeon_legacy_init_crtc(struct drm_device *dev,
684 struct radeon_crtc *radeon_crtc);
771fe6b9
JG		 685
686void radeon_get_clock_info(struct drm_device *dev);
687
688extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
689extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
690
771fe6b9
JG		 691void radeon_enc_destroy(struct drm_encoder *encoder);
692void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
693void radeon_combios_asic_init(struct drm_device *dev);
c93bb85b 694bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 695 const struct drm_display_mode *mode,
c93bb85b 696 struct drm_display_mode *adjusted_mode);
3515387b
AD		 697void radeon_panel_mode_fixup(struct drm_encoder *encoder,
698 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 699void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
700
701/* legacy tv */
702void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
703 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
704 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
705void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
706 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
707 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
708void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
709 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
710 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
711void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
712 struct drm_display_mode *mode,
713 struct drm_display_mode *adjusted_mode);
38651674
DA		 714
715/* fbdev layer */
716int radeon_fbdev_init(struct radeon_device *rdev);
717void radeon_fbdev_fini(struct radeon_device *rdev);
718void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
719int radeon_fbdev_total_size(struct radeon_device *rdev);
720bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
eb1f8e4f
DA		 721
722void radeon_fb_output_poll_changed(struct radeon_device *rdev);
6f34be50
AD		 723
724void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
725
ff72145b 726int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
771fe6b9 727#endif
Linux kernel - Deliverables
This page took 0.251258 seconds and 5 git commands to generate.