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drm/radeon/kms: parse DCE5 encoder caps when setting up encoders
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
68adac5e 37#include <drm_fixed.h>
21c74a8e 38#include <drm_crtc_helper.h>
771fe6b9 39#include <linux/i2c.h>
771fe6b9 40#include <linux/i2c-algo-bit.h>
c93bb85b 41
38651674 42struct radeon_bo;
c93bb85b 43struct radeon_device;
771fe6b9
JG		 44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
771fe6b9
JG		 50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
d79766fa 66 TV_STD_PAL_N,
771fe6b9
JG		 67};
68
5b1714d3
AD		 69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
8e36ed00
AD		 75enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
f376b94f
AD		 85#define RADEON_MAX_I2C_BUS 16
86
9b9fe724
AD		 87/* radeon gpio-based i2c
88 * 1. "mask" reg and bits
89 * grabs the gpio pins for software use
90 * 0=not held 1=held
91 * 2. "a" reg and bits
92 * output pin value
93 * 0=low 1=high
94 * 3. "en" reg and bits
95 * sets the pin direction
96 * 0=input 1=output
97 * 4. "y" reg and bits
98 * input pin value
99 * 0=low 1=high
100 */
771fe6b9
JG		 101struct radeon_i2c_bus_rec {
102 bool valid;
6a93cb25
AD		 103 /* id used by atom */
104 uint8_t i2c_id;
bcc1c2a1 105 /* id used by atom */
8e36ed00 106 enum radeon_hpd_id hpd;
6a93cb25
AD		 107 /* can be used with hw i2c engine */
108 bool hw_capable;
109 /* uses multi-media i2c engine */
110 bool mm_i2c;
111 /* regs and bits */
771fe6b9
JG		 112 uint32_t mask_clk_reg;
113 uint32_t mask_data_reg;
114 uint32_t a_clk_reg;
115 uint32_t a_data_reg;
9b9fe724
AD		 116 uint32_t en_clk_reg;
117 uint32_t en_data_reg;
118 uint32_t y_clk_reg;
119 uint32_t y_data_reg;
771fe6b9
JG		 120 uint32_t mask_clk_mask;
121 uint32_t mask_data_mask;
771fe6b9
JG		 122 uint32_t a_clk_mask;
123 uint32_t a_data_mask;
9b9fe724
AD		 124 uint32_t en_clk_mask;
125 uint32_t en_data_mask;
126 uint32_t y_clk_mask;
127 uint32_t y_data_mask;
771fe6b9
JG		 128};
129
130struct radeon_tmds_pll {
131 uint32_t freq;
132 uint32_t value;
133};
134
135#define RADEON_MAX_BIOS_CONNECTOR 16
136
7c27f87d 137/* pll flags */
771fe6b9
JG		 138#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3)
142#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
143#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
144#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
145#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
146#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
147#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
148#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 150#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 151#define RADEON_PLL_IS_LCD (1 << 13)
771fe6b9
JG		 152
153struct radeon_pll {
fc10332b
AD		 154 /* reference frequency */
155 uint32_t reference_freq;
156
157 /* fixed dividers */
158 uint32_t reference_div;
159 uint32_t post_div;
160
161 /* pll in/out limits */
771fe6b9
JG		 162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
86cb2bbf
AD		 166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
fc10332b 168 uint32_t best_vco;
771fe6b9 169
fc10332b 170 /* divider limits */
771fe6b9
JG		 171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
fc10332b
AD		 179
180 /* flags for the current clock */
181 uint32_t flags;
182
183 /* pll id */
184 uint32_t id;
771fe6b9
JG		 185};
186
187struct radeon_i2c_chan {
771fe6b9 188 struct i2c_adapter adapter;
746c1aa4
DA		 189 struct drm_device *dev;
190 union {
ac1aade6 191 struct i2c_algo_bit_data bit;
746c1aa4 192 struct i2c_algo_dp_aux_data dp;
746c1aa4 193 } algo;
771fe6b9
JG		 194 struct radeon_i2c_bus_rec rec;
195};
196
197/* mostly for macs, but really any system without connector tables */
198enum radeon_connector_table {
aa74fbb4 199 CT_NONE = 0,
771fe6b9
JG		 200 CT_GENERIC,
201 CT_IBOOK,
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
204 CT_POWERBOOK_VGA,
205 CT_MINI_EXTERNAL,
206 CT_MINI_INTERNAL,
207 CT_IMAC_G5_ISIGHT,
208 CT_EMAC,
76a7142a 209 CT_RN50_POWER,
aa74fbb4 210 CT_MAC_X800,
771fe6b9
JG		 211};
212
fcec570b
AD		 213enum radeon_dvo_chip {
214 DVO_SIL164,
215 DVO_SIL1178,
216};
217
8be48d92 218struct radeon_fbdev;
38651674 219
771fe6b9
JG		 220struct radeon_mode_info {
221 struct atom_context *atom_context;
61c4b24b 222 struct card_info *atom_card_info;
771fe6b9
JG		 223 enum radeon_connector_table connector_table;
224 bool mode_config_initialized;
bcc1c2a1 225 struct radeon_crtc *crtcs[6];
445282db
DA		 226 /* DVI-I properties */
227 struct drm_property *coherent_mode_property;
228 /* DAC enable load detect */
229 struct drm_property *load_detect_property;
5b1714d3 230 /* TV standard */
445282db
DA		 231 struct drm_property *tv_std_property;
232 /* legacy TMDS PLL detect */
233 struct drm_property *tmds_pll_property;
5b1714d3
AD		 234 /* underscan */
235 struct drm_property *underscan_property;
5bccf5e3
MG		 236 struct drm_property *underscan_hborder_property;
237 struct drm_property *underscan_vborder_property;
3c537889
AD		 238 /* hardcoded DFP edid from BIOS */
239 struct edid *bios_hardcoded_edid;
38651674
DA		 240
241 /* pointer to fbdev info structure */
8be48d92 242 struct radeon_fbdev *rfbdev;
c93bb85b
JG		 243};
244
4ce001ab
DA		 245#define MAX_H_CODE_TIMING_LEN 32
246#define MAX_V_CODE_TIMING_LEN 32
247
248/* need to store these as reading
249 back code tables is excessive */
250struct radeon_tv_regs {
251 uint32_t tv_uv_adr;
252 uint32_t timing_cntl;
253 uint32_t hrestart;
254 uint32_t vrestart;
255 uint32_t frestart;
256 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
257 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
258};
259
771fe6b9
JG		 260struct radeon_crtc {
261 struct drm_crtc base;
262 int crtc_id;
263 u16 lut_r[256], lut_g[256], lut_b[256];
264 bool enabled;
265 bool can_tile;
266 uint32_t crtc_offset;
771fe6b9
JG		 267 struct drm_gem_object *cursor_bo;
268 uint64_t cursor_addr;
269 int cursor_width;
270 int cursor_height;
4162338a 271 uint32_t legacy_display_base_addr;
c836e862 272 uint32_t legacy_cursor_offset;
c93bb85b 273 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 274 u8 h_border;
275 u8 v_border;
c93bb85b
JG		 276 fixed20_12 vsc;
277 fixed20_12 hsc;
de2103e4 278 struct drm_display_mode native_mode;
bcc1c2a1 279 int pll_id;
6f34be50
AD		 280 /* page flipping */
281 struct radeon_unpin_work *unpin_work;
282 int deferred_flip_completion;
771fe6b9
JG		 283};
284
285struct radeon_encoder_primary_dac {
286 /* legacy primary dac */
287 uint32_t ps2_pdac_adj;
288};
289
290struct radeon_encoder_lvds {
291 /* legacy lvds */
292 uint16_t panel_vcc_delay;
293 uint8_t panel_pwr_delay;
294 uint8_t panel_digon_delay;
295 uint8_t panel_blon_delay;
296 uint16_t panel_ref_divider;
297 uint8_t panel_post_divider;
298 uint16_t panel_fb_divider;
299 bool use_bios_dividers;
300 uint32_t lvds_gen_cntl;
301 /* panel mode */
de2103e4 302 struct drm_display_mode native_mode;
771fe6b9
JG		 303};
304
305struct radeon_encoder_tv_dac {
306 /* legacy tv dac */
307 uint32_t ps2_tvdac_adj;
308 uint32_t ntsc_tvdac_adj;
309 uint32_t pal_tvdac_adj;
310
4ce001ab
DA		 311 int h_pos;
312 int v_pos;
313 int h_size;
314 int supported_tv_stds;
315 bool tv_on;
771fe6b9 316 enum radeon_tv_std tv_std;
4ce001ab 317 struct radeon_tv_regs tv;
771fe6b9
JG		 318};
319
320struct radeon_encoder_int_tmds {
321 /* legacy int tmds */
322 struct radeon_tmds_pll tmds_pll[4];
323};
324
fcec570b
AD		 325struct radeon_encoder_ext_tmds {
326 /* tmds over dvo */
327 struct radeon_i2c_chan *i2c_bus;
328 uint8_t slave_addr;
329 enum radeon_dvo_chip dvo_chip;
330};
331
ebbe1cb9
AD		 332/* spread spectrum */
333struct radeon_atom_ss {
334 uint16_t percentage;
335 uint8_t type;
ba032a58 336 uint16_t step;
ebbe1cb9
AD		 337 uint8_t delay;
338 uint8_t range;
339 uint8_t refdiv;
ba032a58
AD		 340 /* asic_ss */
341 uint16_t rate;
342 uint16_t amount;
ebbe1cb9
AD		 343};
344
771fe6b9 345struct radeon_encoder_atom_dig {
5137ee94 346 bool linkb;
771fe6b9
JG		 347 /* atom dig */
348 bool coherent_mode;
ba032a58
AD		 349 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
350 /* atom lvds/edp */
351 uint32_t lcd_misc;
771fe6b9 352 uint16_t panel_pwr_delay;
ba032a58 353 uint32_t lcd_ss_id;
771fe6b9 354 /* panel mode */
de2103e4 355 struct drm_display_mode native_mode;
771fe6b9
JG		 356};
357
4ce001ab
DA		 358struct radeon_encoder_atom_dac {
359 enum radeon_tv_std tv_std;
360};
361
771fe6b9
JG		 362struct radeon_encoder {
363 struct drm_encoder base;
5137ee94 364 uint32_t encoder_enum;
771fe6b9
JG		 365 uint32_t encoder_id;
366 uint32_t devices;
4ce001ab 367 uint32_t active_device;
771fe6b9
JG		 368 uint32_t flags;
369 uint32_t pixel_clock;
370 enum radeon_rmx_type rmx_type;
5b1714d3 371 enum radeon_underscan_type underscan_type;
5bccf5e3
MG		 372 uint32_t underscan_hborder;
373 uint32_t underscan_vborder;
de2103e4 374 struct drm_display_mode native_mode;
771fe6b9 375 void *enc_priv;
58bd0863 376 int audio_polling_active;
dafc3bd5 377 int hdmi_offset;
808032ee 378 int hdmi_config_offset;
dafc3bd5
CK		 379 int hdmi_audio_workaround;
380 int hdmi_buffer_status;
3e4b9982 381 bool is_ext_encoder;
36868bda 382 u16 caps;
771fe6b9
JG		 383};
384
385struct radeon_connector_atom_dig {
386 uint32_t igp_lane_info;
4143e919 387 /* displayport */
746c1aa4 388 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 389 u8 dpcd[8];
4143e919 390 u8 dp_sink_type;
5801ead6
AD		 391 int dp_clock;
392 int dp_lane_count;
8b834852 393 bool edp_on;
771fe6b9
JG		 394};
395
eed45b30
AD		 396struct radeon_gpio_rec {
397 bool valid;
398 u8 id;
399 u32 reg;
400 u32 mask;
401};
402
eed45b30
AD		 403struct radeon_hpd {
404 enum radeon_hpd_id hpd;
405 u8 plugged_state;
406 struct radeon_gpio_rec gpio;
407};
408
26b5bc98 409struct radeon_router {
26b5bc98
AD		 410 u32 router_id;
411 struct radeon_i2c_bus_rec i2c_info;
412 u8 i2c_addr;
fb939dfc
AD		 413 /* i2c mux */
414 bool ddc_valid;
415 u8 ddc_mux_type;
416 u8 ddc_mux_control_pin;
417 u8 ddc_mux_state;
418 /* clock/data mux */
419 bool cd_valid;
420 u8 cd_mux_type;
421 u8 cd_mux_control_pin;
422 u8 cd_mux_state;
26b5bc98
AD		 423};
424
771fe6b9
JG		 425struct radeon_connector {
426 struct drm_connector base;
427 uint32_t connector_id;
428 uint32_t devices;
429 struct radeon_i2c_chan *ddc_bus;
5b1714d3 430 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 431 bool shared_ddc;
4ce001ab
DA		 432 bool use_digital;
433 /* we need to mind the EDID between detect
434 and get modes due to analog/digital/tvencoder */
435 struct edid *edid;
771fe6b9 436 void *con_priv;
445282db 437 bool dac_load_detect;
b75fad06 438 uint16_t connector_object_id;
eed45b30 439 struct radeon_hpd hpd;
26b5bc98
AD		 440 struct radeon_router router;
441 struct radeon_i2c_chan *router_bus;
771fe6b9
JG		 442};
443
444struct radeon_framebuffer {
445 struct drm_framebuffer base;
446 struct drm_gem_object *obj;
447};
448
6383cf7d 449
d79766fa
AD		 450extern enum radeon_tv_std
451radeon_combios_get_tv_info(struct radeon_device *rdev);
452extern enum radeon_tv_std
453radeon_atombios_get_tv_info(struct radeon_device *rdev);
454
5b1714d3
AD		 455extern struct drm_connector *
456radeon_get_connector_for_encoder(struct drm_encoder *encoder);
457
d4877cf2
AD		 458extern void radeon_connector_hotplug(struct drm_connector *connector);
459extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 460extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
461 struct drm_display_mode *mode);
462extern void radeon_dp_set_link_config(struct drm_connector *connector,
463 struct drm_display_mode *mode);
464extern void dp_link_train(struct drm_encoder *encoder,
465 struct drm_connector *connector);
4143e919 466extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 467extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
bcc1c2a1 468extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
5801ead6
AD		 469extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
470 int action, uint8_t lane_num,
471 uint8_t lane_set);
746c1aa4
DA		 472extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
473 uint8_t write_byte, uint8_t *read_byte);
474
f376b94f
AD		 475extern void radeon_i2c_init(struct radeon_device *rdev);
476extern void radeon_i2c_fini(struct radeon_device *rdev);
477extern void radeon_combios_i2c_init(struct radeon_device *rdev);
478extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
479extern void radeon_i2c_add(struct radeon_device *rdev,
480 struct radeon_i2c_bus_rec *rec,
481 const char *name);
482extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
483 struct radeon_i2c_bus_rec *i2c_bus);
746c1aa4 484extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 485 struct radeon_i2c_bus_rec *rec,
486 const char *name);
771fe6b9
JG		 487extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
488 struct radeon_i2c_bus_rec *rec,
489 const char *name);
490extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 491extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
492 u8 slave_addr,
493 u8 addr,
494 u8 *val);
495extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
496 u8 slave_addr,
497 u8 addr,
498 u8 val);
fb939dfc
AD		 499extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
500extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
771fe6b9
JG		 501extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
502extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
503
504extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
505
ba032a58
AD		 506extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
507 struct radeon_atom_ss *ss,
508 int id);
509extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
510 struct radeon_atom_ss *ss,
511 int id, u32 clock);
512
771fe6b9
JG		 513extern void radeon_compute_pll(struct radeon_pll *pll,
514 uint64_t freq,
515 uint32_t *dot_clock_p,
516 uint32_t *fb_div_p,
517 uint32_t *frac_fb_div_p,
518 uint32_t *ref_div_p,
fc10332b 519 uint32_t *post_div_p);
771fe6b9 520
1f3b6a45
DA		 521extern void radeon_setup_encoder_clones(struct drm_device *dev);
522
771fe6b9
JG		 523struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
524struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
525struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
526struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
527struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
99999aaa 528extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
32f48ffe 529extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 530extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
8b834852 531extern void atombios_set_edp_panel_power(struct drm_connector *connector, int action);
4ce001ab 532extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 533
534extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
535extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
536 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 537extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
538 struct drm_framebuffer *fb,
21c74a8e
JW		 539 int x, int y,
540 enum mode_set_atomic state);
771fe6b9
JG		 541extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
542 struct drm_display_mode *mode,
543 struct drm_display_mode *adjusted_mode,
544 int x, int y,
545 struct drm_framebuffer *old_fb);
546extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
547
548extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
549 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 550extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
551 struct drm_framebuffer *fb,
21c74a8e
JW		 552 int x, int y,
553 enum mode_set_atomic state);
4dd19b0d
CB		 554extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
555 struct drm_framebuffer *fb,
556 int x, int y, int atomic);
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JG		 557extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
558 struct drm_file *file_priv,
559 uint32_t handle,
560 uint32_t width,
561 uint32_t height);
562extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
563 int x, int y);
564
f5a80209
MK		 565extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
566 int *vpos, int *hpos);
6383cf7d 567
3c537889
AD		 568extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
569extern struct edid *
c324acd5 570radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
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JG		 571extern bool radeon_atom_get_clock_info(struct drm_device *dev);
572extern bool radeon_combios_get_clock_info(struct drm_device *dev);
573extern struct radeon_encoder_atom_dig *
574radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 575extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
576 struct radeon_encoder_int_tmds *tmds);
577extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
578 struct radeon_encoder_int_tmds *tmds);
579extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
580 struct radeon_encoder_int_tmds *tmds);
581extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
582 struct radeon_encoder_ext_tmds *tmds);
583extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
584 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 585extern struct radeon_encoder_primary_dac *
586radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
587extern struct radeon_encoder_tv_dac *
588radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 589extern struct radeon_encoder_lvds *
590radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 591extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
592extern struct radeon_encoder_tv_dac *
593radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
594extern struct radeon_encoder_primary_dac *
595radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 596extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
597extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
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JG		 598extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
599extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
600extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
601extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 602extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
603extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 604extern void
605radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
606extern void
607radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
608extern void
609radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
610extern void
611radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
612extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
613 u16 blue, int regno);
b8c00ac5
DA		 614extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
615 u16 *blue, int regno);
38651674
DA		 616void radeon_framebuffer_init(struct drm_device *dev,
617 struct radeon_framebuffer *rfb,
618 struct drm_mode_fb_cmd *mode_cmd,
619 struct drm_gem_object *obj);
771fe6b9
JG		 620
621int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
622bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
623bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
624void radeon_atombios_init_crtc(struct drm_device *dev,
625 struct radeon_crtc *radeon_crtc);
626void radeon_legacy_init_crtc(struct drm_device *dev,
627 struct radeon_crtc *radeon_crtc);
771fe6b9
JG		 628
629void radeon_get_clock_info(struct drm_device *dev);
630
631extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
632extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
633
771fe6b9
JG		 634void radeon_enc_destroy(struct drm_encoder *encoder);
635void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
636void radeon_combios_asic_init(struct drm_device *dev);
c93bb85b
JG		 637bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
638 struct drm_display_mode *mode,
639 struct drm_display_mode *adjusted_mode);
3515387b
AD		 640void radeon_panel_mode_fixup(struct drm_encoder *encoder,
641 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 642void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
643
644/* legacy tv */
645void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
646 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
647 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
648void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
649 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
650 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
651void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
652 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
653 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
654void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
655 struct drm_display_mode *mode,
656 struct drm_display_mode *adjusted_mode);
38651674
DA		 657
658/* fbdev layer */
659int radeon_fbdev_init(struct radeon_device *rdev);
660void radeon_fbdev_fini(struct radeon_device *rdev);
661void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
662int radeon_fbdev_total_size(struct radeon_device *rdev);
663bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
eb1f8e4f
DA		 664
665void radeon_fb_output_poll_changed(struct radeon_device *rdev);
6f34be50
AD		 666
667void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
668
771fe6b9 669#endif
Linux kernel - Deliverables
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