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Merge tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
760285e7
DH		 33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
771fe6b9 38#include <linux/i2c.h>
771fe6b9 39#include <linux/i2c-algo-bit.h>
c93bb85b 40
38651674 41struct radeon_bo;
c93bb85b 42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
771fe6b9
JG		 49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
d79766fa 65 TV_STD_PAL_N,
771fe6b9
JG		 66};
67
5b1714d3
AD		 68enum radeon_underscan_type {
69 UNDERSCAN_OFF,
70 UNDERSCAN_ON,
71 UNDERSCAN_AUTO,
72};
73
8e36ed00
AD		 74enum radeon_hpd_id {
75 RADEON_HPD_1 = 0,
76 RADEON_HPD_2,
77 RADEON_HPD_3,
78 RADEON_HPD_4,
79 RADEON_HPD_5,
80 RADEON_HPD_6,
81 RADEON_HPD_NONE = 0xff,
82};
83
f376b94f
AD		 84#define RADEON_MAX_I2C_BUS 16
85
9b9fe724
AD		 86/* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
89 * 0=not held 1=held
90 * 2. "a" reg and bits
91 * output pin value
92 * 0=low 1=high
93 * 3. "en" reg and bits
94 * sets the pin direction
95 * 0=input 1=output
96 * 4. "y" reg and bits
97 * input pin value
98 * 0=low 1=high
99 */
771fe6b9
JG		 100struct radeon_i2c_bus_rec {
101 bool valid;
6a93cb25
AD		 102 /* id used by atom */
103 uint8_t i2c_id;
bcc1c2a1 104 /* id used by atom */
8e36ed00 105 enum radeon_hpd_id hpd;
6a93cb25
AD		 106 /* can be used with hw i2c engine */
107 bool hw_capable;
108 /* uses multi-media i2c engine */
109 bool mm_i2c;
110 /* regs and bits */
771fe6b9
JG		 111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
113 uint32_t a_clk_reg;
114 uint32_t a_data_reg;
9b9fe724
AD		 115 uint32_t en_clk_reg;
116 uint32_t en_data_reg;
117 uint32_t y_clk_reg;
118 uint32_t y_data_reg;
771fe6b9
JG		 119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
771fe6b9
JG		 121 uint32_t a_clk_mask;
122 uint32_t a_data_mask;
9b9fe724
AD		 123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
125 uint32_t y_clk_mask;
126 uint32_t y_data_mask;
771fe6b9
JG		 127};
128
129struct radeon_tmds_pll {
130 uint32_t freq;
131 uint32_t value;
132};
133
134#define RADEON_MAX_BIOS_CONNECTOR 16
135
7c27f87d 136/* pll flags */
771fe6b9
JG		 137#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139#define RADEON_PLL_USE_REF_DIV (1 << 2)
140#define RADEON_PLL_LEGACY (1 << 3)
141#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 148#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 149#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 150#define RADEON_PLL_IS_LCD (1 << 13)
f523f74e 151#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
771fe6b9
JG		 152
153struct radeon_pll {
fc10332b
AD		 154 /* reference frequency */
155 uint32_t reference_freq;
156
157 /* fixed dividers */
158 uint32_t reference_div;
159 uint32_t post_div;
160
161 /* pll in/out limits */
771fe6b9
JG		 162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
86cb2bbf
AD		 166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
fc10332b 168 uint32_t best_vco;
771fe6b9 169
fc10332b 170 /* divider limits */
771fe6b9
JG		 171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
fc10332b
AD		 179
180 /* flags for the current clock */
181 uint32_t flags;
182
183 /* pll id */
184 uint32_t id;
771fe6b9
JG		 185};
186
187struct radeon_i2c_chan {
771fe6b9 188 struct i2c_adapter adapter;
746c1aa4 189 struct drm_device *dev;
379dfc25 190 struct i2c_algo_bit_data bit;
771fe6b9 191 struct radeon_i2c_bus_rec rec;
496263bf 192 struct drm_dp_aux aux;
379dfc25 193 bool has_aux;
771fe6b9
JG		 194};
195
196/* mostly for macs, but really any system without connector tables */
197enum radeon_connector_table {
aa74fbb4 198 CT_NONE = 0,
771fe6b9
JG		 199 CT_GENERIC,
200 CT_IBOOK,
201 CT_POWERBOOK_EXTERNAL,
202 CT_POWERBOOK_INTERNAL,
203 CT_POWERBOOK_VGA,
204 CT_MINI_EXTERNAL,
205 CT_MINI_INTERNAL,
206 CT_IMAC_G5_ISIGHT,
207 CT_EMAC,
76a7142a 208 CT_RN50_POWER,
aa74fbb4 209 CT_MAC_X800,
9fad321a 210 CT_MAC_G5_9600,
cafa59b9
AD		 211 CT_SAM440EP,
212 CT_MAC_G4_SILVER
771fe6b9
JG		 213};
214
fcec570b
AD		 215enum radeon_dvo_chip {
216 DVO_SIL164,
217 DVO_SIL1178,
218};
219
8be48d92 220struct radeon_fbdev;
38651674 221
0783986a
AD		 222struct radeon_afmt {
223 bool enabled;
224 int offset;
225 bool last_buffer_filled_status;
226 int id;
b530602f 227 struct r600_audio_pin *pin;
0783986a
AD		 228};
229
771fe6b9
JG		 230struct radeon_mode_info {
231 struct atom_context *atom_context;
61c4b24b 232 struct card_info *atom_card_info;
771fe6b9
JG		 233 enum radeon_connector_table connector_table;
234 bool mode_config_initialized;
bcc1c2a1 235 struct radeon_crtc *crtcs[6];
b530602f 236 struct radeon_afmt *afmt[7];
445282db
DA		 237 /* DVI-I properties */
238 struct drm_property *coherent_mode_property;
239 /* DAC enable load detect */
240 struct drm_property *load_detect_property;
5b1714d3 241 /* TV standard */
445282db
DA		 242 struct drm_property *tv_std_property;
243 /* legacy TMDS PLL detect */
244 struct drm_property *tmds_pll_property;
5b1714d3
AD		 245 /* underscan */
246 struct drm_property *underscan_property;
5bccf5e3
MG		 247 struct drm_property *underscan_hborder_property;
248 struct drm_property *underscan_vborder_property;
8666c076
AD		 249 /* audio */
250 struct drm_property *audio_property;
6214bb74
AD		 251 /* FMT dithering */
252 struct drm_property *dither_property;
3c537889
AD		 253 /* hardcoded DFP edid from BIOS */
254 struct edid *bios_hardcoded_edid;
fafcf94e 255 int bios_hardcoded_edid_size;
38651674
DA		 256
257 /* pointer to fbdev info structure */
8be48d92 258 struct radeon_fbdev *rfbdev;
af7912e5
AD		 259 /* firmware flags */
260 u16 firmware_flags;
bced76f2
AD		 261 /* pointer to backlight encoder */
262 struct radeon_encoder *bl_encoder;
c93bb85b
JG		 263};
264
91030880
AD		 265#define RADEON_MAX_BL_LEVEL 0xFF
266
bced76f2
AD		 267#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
268
91030880
AD		 269struct radeon_backlight_privdata {
270 struct radeon_encoder *encoder;
271 uint8_t negative;
272};
273
274#endif
275
4ce001ab
DA		 276#define MAX_H_CODE_TIMING_LEN 32
277#define MAX_V_CODE_TIMING_LEN 32
278
279/* need to store these as reading
280 back code tables is excessive */
281struct radeon_tv_regs {
282 uint32_t tv_uv_adr;
283 uint32_t timing_cntl;
284 uint32_t hrestart;
285 uint32_t vrestart;
286 uint32_t frestart;
287 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
288 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
289};
290
19eca43e
AD		 291struct radeon_atom_ss {
292 uint16_t percentage;
18f8f52b 293 uint16_t percentage_divider;
19eca43e
AD		 294 uint8_t type;
295 uint16_t step;
296 uint8_t delay;
297 uint8_t range;
298 uint8_t refdiv;
299 /* asic_ss */
300 uint16_t rate;
301 uint16_t amount;
302};
303
771fe6b9
JG		 304struct radeon_crtc {
305 struct drm_crtc base;
306 int crtc_id;
307 u16 lut_r[256], lut_g[256], lut_b[256];
308 bool enabled;
309 bool can_tile;
310 uint32_t crtc_offset;
771fe6b9
JG		 311 struct drm_gem_object *cursor_bo;
312 uint64_t cursor_addr;
313 int cursor_width;
314 int cursor_height;
9e05fa1d
AD		 315 int max_cursor_width;
316 int max_cursor_height;
4162338a 317 uint32_t legacy_display_base_addr;
c836e862 318 uint32_t legacy_cursor_offset;
c93bb85b 319 enum radeon_rmx_type rmx_type;
5b1714d3
AD		 320 u8 h_border;
321 u8 v_border;
c93bb85b
JG		 322 fixed20_12 vsc;
323 fixed20_12 hsc;
de2103e4 324 struct drm_display_mode native_mode;
bcc1c2a1 325 int pll_id;
6f34be50
AD		 326 /* page flipping */
327 struct radeon_unpin_work *unpin_work;
328 int deferred_flip_completion;
19eca43e
AD		 329 /* pll sharing */
330 struct radeon_atom_ss ss;
331 bool ss_enabled;
332 u32 adjusted_clock;
333 int bpc;
334 u32 pll_reference_div;
335 u32 pll_post_div;
336 u32 pll_flags;
5df3196b 337 struct drm_encoder *encoder;
57b35e29 338 struct drm_connector *connector;
7178d2a6
AD		 339 /* for dpm */
340 u32 line_time;
341 u32 wm_low;
342 u32 wm_high;
66edc1c9 343 struct drm_display_mode hw_mode;
771fe6b9
JG		 344};
345
346struct radeon_encoder_primary_dac {
347 /* legacy primary dac */
348 uint32_t ps2_pdac_adj;
349};
350
351struct radeon_encoder_lvds {
352 /* legacy lvds */
353 uint16_t panel_vcc_delay;
354 uint8_t panel_pwr_delay;
355 uint8_t panel_digon_delay;
356 uint8_t panel_blon_delay;
357 uint16_t panel_ref_divider;
358 uint8_t panel_post_divider;
359 uint16_t panel_fb_divider;
360 bool use_bios_dividers;
361 uint32_t lvds_gen_cntl;
362 /* panel mode */
de2103e4 363 struct drm_display_mode native_mode;
63ec0119
MD		 364 struct backlight_device *bl_dev;
365 int dpms_mode;
366 uint8_t backlight_level;
771fe6b9
JG		 367};
368
369struct radeon_encoder_tv_dac {
370 /* legacy tv dac */
371 uint32_t ps2_tvdac_adj;
372 uint32_t ntsc_tvdac_adj;
373 uint32_t pal_tvdac_adj;
374
4ce001ab
DA		 375 int h_pos;
376 int v_pos;
377 int h_size;
378 int supported_tv_stds;
379 bool tv_on;
771fe6b9 380 enum radeon_tv_std tv_std;
4ce001ab 381 struct radeon_tv_regs tv;
771fe6b9
JG		 382};
383
384struct radeon_encoder_int_tmds {
385 /* legacy int tmds */
386 struct radeon_tmds_pll tmds_pll[4];
387};
388
fcec570b
AD		 389struct radeon_encoder_ext_tmds {
390 /* tmds over dvo */
391 struct radeon_i2c_chan *i2c_bus;
392 uint8_t slave_addr;
393 enum radeon_dvo_chip dvo_chip;
394};
395
ebbe1cb9 396/* spread spectrum */
771fe6b9 397struct radeon_encoder_atom_dig {
5137ee94 398 bool linkb;
771fe6b9
JG		 399 /* atom dig */
400 bool coherent_mode;
ba032a58
AD		 401 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
402 /* atom lvds/edp */
403 uint32_t lcd_misc;
771fe6b9 404 uint16_t panel_pwr_delay;
ba032a58 405 uint32_t lcd_ss_id;
771fe6b9 406 /* panel mode */
de2103e4 407 struct drm_display_mode native_mode;
63ec0119
MD		 408 struct backlight_device *bl_dev;
409 int dpms_mode;
410 uint8_t backlight_level;
386d4d75 411 int panel_mode;
0783986a 412 struct radeon_afmt *afmt;
771fe6b9
JG		 413};
414
4ce001ab
DA		 415struct radeon_encoder_atom_dac {
416 enum radeon_tv_std tv_std;
417};
418
771fe6b9
JG		 419struct radeon_encoder {
420 struct drm_encoder base;
5137ee94 421 uint32_t encoder_enum;
771fe6b9
JG		 422 uint32_t encoder_id;
423 uint32_t devices;
4ce001ab 424 uint32_t active_device;
771fe6b9
JG		 425 uint32_t flags;
426 uint32_t pixel_clock;
427 enum radeon_rmx_type rmx_type;
5b1714d3 428 enum radeon_underscan_type underscan_type;
5bccf5e3
MG		 429 uint32_t underscan_hborder;
430 uint32_t underscan_vborder;
de2103e4 431 struct drm_display_mode native_mode;
771fe6b9 432 void *enc_priv;
58bd0863 433 int audio_polling_active;
3e4b9982 434 bool is_ext_encoder;
36868bda 435 u16 caps;
771fe6b9
JG		 436};
437
438struct radeon_connector_atom_dig {
439 uint32_t igp_lane_info;
4143e919 440 /* displayport */
1a644cd4 441 u8 dpcd[DP_RECEIVER_CAP_SIZE];
4143e919 442 u8 dp_sink_type;
5801ead6
AD		 443 int dp_clock;
444 int dp_lane_count;
8b834852 445 bool edp_on;
771fe6b9
JG		 446};
447
eed45b30
AD		 448struct radeon_gpio_rec {
449 bool valid;
450 u8 id;
451 u32 reg;
452 u32 mask;
453};
454
eed45b30
AD		 455struct radeon_hpd {
456 enum radeon_hpd_id hpd;
457 u8 plugged_state;
458 struct radeon_gpio_rec gpio;
459};
460
26b5bc98 461struct radeon_router {
26b5bc98
AD		 462 u32 router_id;
463 struct radeon_i2c_bus_rec i2c_info;
464 u8 i2c_addr;
fb939dfc
AD		 465 /* i2c mux */
466 bool ddc_valid;
467 u8 ddc_mux_type;
468 u8 ddc_mux_control_pin;
469 u8 ddc_mux_state;
470 /* clock/data mux */
471 bool cd_valid;
472 u8 cd_mux_type;
473 u8 cd_mux_control_pin;
474 u8 cd_mux_state;
26b5bc98
AD		 475};
476
8666c076
AD		 477enum radeon_connector_audio {
478 RADEON_AUDIO_DISABLE = 0,
479 RADEON_AUDIO_ENABLE = 1,
480 RADEON_AUDIO_AUTO = 2
481};
482
6214bb74
AD		 483enum radeon_connector_dither {
484 RADEON_FMT_DITHER_DISABLE = 0,
485 RADEON_FMT_DITHER_ENABLE = 1,
486};
487
771fe6b9
JG		 488struct radeon_connector {
489 struct drm_connector base;
490 uint32_t connector_id;
491 uint32_t devices;
492 struct radeon_i2c_chan *ddc_bus;
5b1714d3 493 /* some systems have an hdmi and vga port with a shared ddc line */
0294cf4f 494 bool shared_ddc;
4ce001ab
DA		 495 bool use_digital;
496 /* we need to mind the EDID between detect
497 and get modes due to analog/digital/tvencoder */
498 struct edid *edid;
771fe6b9 499 void *con_priv;
445282db 500 bool dac_load_detect;
d0d0a225 501 bool detected_by_load; /* if the connection status was determined by load */
b75fad06 502 uint16_t connector_object_id;
eed45b30 503 struct radeon_hpd hpd;
26b5bc98
AD		 504 struct radeon_router router;
505 struct radeon_i2c_chan *router_bus;
8666c076 506 enum radeon_connector_audio audio;
6214bb74 507 enum radeon_connector_dither dither;
771fe6b9
JG		 508};
509
510struct radeon_framebuffer {
511 struct drm_framebuffer base;
512 struct drm_gem_object *obj;
513};
514
996d5c59
AD		 515#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
516 ((em) == ATOM_ENCODER_MODE_DP_MST))
6383cf7d 517
7062ab67
CK		 518struct atom_clock_dividers {
519 u32 post_div;
520 union {
521 struct {
522#ifdef __BIG_ENDIAN
523 u32 reserved : 6;
524 u32 whole_fb_div : 12;
525 u32 frac_fb_div : 14;
526#else
527 u32 frac_fb_div : 14;
528 u32 whole_fb_div : 12;
529 u32 reserved : 6;
530#endif
531 };
532 u32 fb_div;
533 };
534 u32 ref_div;
535 bool enable_post_div;
536 bool enable_dithen;
537 u32 vco_mode;
538 u32 real_clock;
9219ed65
AD		 539 /* added for CI */
540 u32 post_divider;
541 u32 flags;
7062ab67
CK		 542};
543
eaa778af
AD		 544struct atom_mpll_param {
545 union {
546 struct {
547#ifdef __BIG_ENDIAN
548 u32 reserved : 8;
549 u32 clkfrac : 12;
550 u32 clkf : 12;
551#else
552 u32 clkf : 12;
553 u32 clkfrac : 12;
554 u32 reserved : 8;
555#endif
556 };
557 u32 fb_div;
558 };
559 u32 post_div;
560 u32 bwcntl;
561 u32 dll_speed;
562 u32 vco_mode;
563 u32 yclk_sel;
564 u32 qdr;
565 u32 half_rate;
566};
567
ae5b0abb
AD		 568#define MEM_TYPE_GDDR5 0x50
569#define MEM_TYPE_GDDR4 0x40
570#define MEM_TYPE_GDDR3 0x30
571#define MEM_TYPE_DDR2 0x20
572#define MEM_TYPE_GDDR1 0x10
573#define MEM_TYPE_DDR3 0xb0
574#define MEM_TYPE_MASK 0xf0
575
576struct atom_memory_info {
577 u8 mem_vendor;
578 u8 mem_type;
579};
580
581#define MAX_AC_TIMING_ENTRIES 16
582
583struct atom_memory_clock_range_table
584{
585 u8 num_entries;
586 u8 rsv[3];
587 u32 mclk[MAX_AC_TIMING_ENTRIES];
588};
589
590#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
591#define VBIOS_MAX_AC_TIMING_ENTRIES 20
592
593struct atom_mc_reg_entry {
594 u32 mclk_max;
595 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
596};
597
598struct atom_mc_register_address {
599 u16 s1;
600 u8 pre_reg_data;
601};
602
603struct atom_mc_reg_table {
604 u8 last;
605 u8 num_entries;
606 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
607 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
608};
609
610#define MAX_VOLTAGE_ENTRIES 32
611
612struct atom_voltage_table_entry
613{
614 u16 value;
615 u32 smio_low;
616};
617
618struct atom_voltage_table
619{
620 u32 count;
621 u32 mask_low;
65171944 622 u32 phase_delay;
ae5b0abb
AD		 623 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
624};
625
a38eab52
RK		 626
627extern void
628radeon_add_atom_connector(struct drm_device *dev,
629 uint32_t connector_id,
630 uint32_t supported_device,
631 int connector_type,
632 struct radeon_i2c_bus_rec *i2c_bus,
633 uint32_t igp_lane_info,
634 uint16_t connector_object_id,
635 struct radeon_hpd *hpd,
636 struct radeon_router *router);
637extern void
638radeon_add_legacy_connector(struct drm_device *dev,
639 uint32_t connector_id,
640 uint32_t supported_device,
641 int connector_type,
642 struct radeon_i2c_bus_rec *i2c_bus,
643 uint16_t connector_object_id,
644 struct radeon_hpd *hpd);
0091fc13
RK		 645extern uint32_t
646radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
647 uint8_t dac);
648extern void radeon_link_encoder_connector(struct drm_device *dev);
a38eab52 649
d79766fa
AD		 650extern enum radeon_tv_std
651radeon_combios_get_tv_info(struct radeon_device *rdev);
652extern enum radeon_tv_std
653radeon_atombios_get_tv_info(struct radeon_device *rdev);
4a6369e9 654extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2abba66e 655 u16 *vddc, u16 *vddci, u16 *mvdd);
d79766fa 656
84ac68e0
AD		 657extern void
658radeon_combios_connected_scratch_regs(struct drm_connector *connector,
659 struct drm_encoder *encoder,
660 bool connected);
661extern void
662radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
663 struct drm_encoder *encoder,
664 bool connected);
665
5b1714d3
AD		 666extern struct drm_connector *
667radeon_get_connector_for_encoder(struct drm_encoder *encoder);
9aa59993
AD		 668extern struct drm_connector *
669radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
670extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
671 u32 pixel_clock);
5b1714d3 672
1d33e1fc
AD		 673extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
674extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
d7fa8bb3
AD		 675extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
676extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
eccea792 677extern int radeon_get_monitor_bpc(struct drm_connector *connector);
d7fa8bb3 678
d4877cf2 679extern void radeon_connector_hotplug(struct drm_connector *connector);
224d94b1 680extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 681 struct drm_display_mode *mode);
682extern void radeon_dp_set_link_config(struct drm_connector *connector,
e811f5ae 683 const struct drm_display_mode *mode);
224d94b1
AD		 684extern void radeon_dp_link_train(struct drm_encoder *encoder,
685 struct drm_connector *connector);
d5811e87 686extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4143e919 687extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 688extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
386d4d75
AD		 689extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
690 struct drm_connector *connector);
2953da15
AD		 691extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
692 u8 power_state);
496263bf 693extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
558e27db 694extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
ac89af1e 695extern void radeon_atom_encoder_init(struct radeon_device *rdev);
f3f1f03e 696extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
5801ead6
AD		 697extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
698 int action, uint8_t lane_num,
699 uint8_t lane_set);
591a10e1 700extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
3f03ced8 701extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
4cf3b494 702void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
746c1aa4 703
f376b94f
AD		 704extern void radeon_i2c_init(struct radeon_device *rdev);
705extern void radeon_i2c_fini(struct radeon_device *rdev);
706extern void radeon_combios_i2c_init(struct radeon_device *rdev);
707extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
708extern void radeon_i2c_add(struct radeon_device *rdev,
709 struct radeon_i2c_bus_rec *rec,
710 const char *name);
711extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
712 struct radeon_i2c_bus_rec *i2c_bus);
771fe6b9
JG		 713extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
714 struct radeon_i2c_bus_rec *rec,
715 const char *name);
716extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 717extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
718 u8 slave_addr,
719 u8 addr,
720 u8 *val);
721extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
722 u8 slave_addr,
723 u8 addr,
724 u8 val);
fb939dfc
AD		 725extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
726extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
0a9069d3 727extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
771fe6b9
JG		 728extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
729
730extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
731
ba032a58
AD		 732extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
733 struct radeon_atom_ss *ss,
734 int id);
735extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
736 struct radeon_atom_ss *ss,
737 int id, u32 clock);
738
f523f74e
AD		 739extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
740 uint64_t freq,
741 uint32_t *dot_clock_p,
742 uint32_t *fb_div_p,
743 uint32_t *frac_fb_div_p,
744 uint32_t *ref_div_p,
745 uint32_t *post_div_p);
746
747extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
748 u32 freq,
749 u32 *dot_clock_p,
750 u32 *fb_div_p,
751 u32 *frac_fb_div_p,
752 u32 *ref_div_p,
753 u32 *post_div_p);
771fe6b9 754
1f3b6a45
DA		 755extern void radeon_setup_encoder_clones(struct drm_device *dev);
756
771fe6b9
JG		 757struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
758struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
759struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
760struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
761struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
99999aaa 762extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
32f48ffe 763extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 764extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
2dafb74d 765extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
4ce001ab 766extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 767
768extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
769extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
770 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 771extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
772 struct drm_framebuffer *fb,
21c74a8e
JW		 773 int x, int y,
774 enum mode_set_atomic state);
771fe6b9
JG		 775extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
776 struct drm_display_mode *mode,
777 struct drm_display_mode *adjusted_mode,
778 int x, int y,
779 struct drm_framebuffer *old_fb);
780extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
781
782extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
783 struct drm_framebuffer *old_fb);
4dd19b0d
CB		 784extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
785 struct drm_framebuffer *fb,
21c74a8e
JW		 786 int x, int y,
787 enum mode_set_atomic state);
4dd19b0d
CB		 788extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
789 struct drm_framebuffer *fb,
790 int x, int y, int atomic);
771fe6b9
JG		 791extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
792 struct drm_file *file_priv,
793 uint32_t handle,
794 uint32_t width,
795 uint32_t height);
796extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
797 int x, int y);
798
f5a80209 799extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
abca9e45 800 unsigned int flags,
d47abc58
MK		 801 int *vpos, int *hpos, ktime_t *stime,
802 ktime_t *etime);
6383cf7d 803
3c537889
AD		 804extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
805extern struct edid *
c324acd5 806radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 807extern bool radeon_atom_get_clock_info(struct drm_device *dev);
808extern bool radeon_combios_get_clock_info(struct drm_device *dev);
809extern struct radeon_encoder_atom_dig *
810radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 811extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
812 struct radeon_encoder_int_tmds *tmds);
813extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
814 struct radeon_encoder_int_tmds *tmds);
815extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
816 struct radeon_encoder_int_tmds *tmds);
817extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
818 struct radeon_encoder_ext_tmds *tmds);
819extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
820 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 821extern struct radeon_encoder_primary_dac *
822radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
823extern struct radeon_encoder_tv_dac *
824radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 825extern struct radeon_encoder_lvds *
826radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 827extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
828extern struct radeon_encoder_tv_dac *
829radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
830extern struct radeon_encoder_primary_dac *
831radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 832extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
833extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 834extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
835extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
836extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
837extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 838extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
839extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 840extern void
841radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
842extern void
843radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
844extern void
845radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
846extern void
847radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
848extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
849 u16 blue, int regno);
b8c00ac5
DA		 850extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
851 u16 *blue, int regno);
aaefcd42 852int radeon_framebuffer_init(struct drm_device *dev,
38651674 853 struct radeon_framebuffer *rfb,
308e5bcb 854 struct drm_mode_fb_cmd2 *mode_cmd,
38651674 855 struct drm_gem_object *obj);
771fe6b9
JG		 856
857int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
858bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
859bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
860void radeon_atombios_init_crtc(struct drm_device *dev,
861 struct radeon_crtc *radeon_crtc);
862void radeon_legacy_init_crtc(struct drm_device *dev,
863 struct radeon_crtc *radeon_crtc);
771fe6b9
JG		 864
865void radeon_get_clock_info(struct drm_device *dev);
866
867extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
868extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
869
771fe6b9
JG		 870void radeon_enc_destroy(struct drm_encoder *encoder);
871void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
872void radeon_combios_asic_init(struct drm_device *dev);
c93bb85b 873bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
e811f5ae 874 const struct drm_display_mode *mode,
c93bb85b 875 struct drm_display_mode *adjusted_mode);
3515387b
AD		 876void radeon_panel_mode_fixup(struct drm_encoder *encoder,
877 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 878void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
879
880/* legacy tv */
881void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
882 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
883 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
884void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
885 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
886 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
887void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
888 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
889 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
890void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
891 struct drm_display_mode *mode,
892 struct drm_display_mode *adjusted_mode);
38651674 893
134b480f
AD		 894/* fmt blocks */
895void avivo_program_fmt(struct drm_encoder *encoder);
896void dce3_program_fmt(struct drm_encoder *encoder);
897void dce4_program_fmt(struct drm_encoder *encoder);
898void dce8_program_fmt(struct drm_encoder *encoder);
899
38651674
DA		 900/* fbdev layer */
901int radeon_fbdev_init(struct radeon_device *rdev);
902void radeon_fbdev_fini(struct radeon_device *rdev);
903void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
904int radeon_fbdev_total_size(struct radeon_device *rdev);
905bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
eb1f8e4f
DA		 906
907void radeon_fb_output_poll_changed(struct radeon_device *rdev);
6f34be50
AD		 908
909void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
910
ff72145b 911int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
771fe6b9 912#endif
Linux kernel - Deliverables
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