Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and | |
3 | * VA Linux Systems Inc., Fremont, California. | |
4 | * Copyright 2008 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Original Authors: | |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane | |
26 | * | |
27 | * Kernel port Author: Dave Airlie | |
28 | */ | |
29 | ||
30 | #ifndef RADEON_MODE_H | |
31 | #define RADEON_MODE_H | |
32 | ||
33 | #include <drm_crtc.h> | |
34 | #include <drm_mode.h> | |
35 | #include <drm_edid.h> | |
746c1aa4 | 36 | #include <drm_dp_helper.h> |
771fe6b9 JG |
37 | #include <linux/i2c.h> |
38 | #include <linux/i2c-id.h> | |
39 | #include <linux/i2c-algo-bit.h> | |
c93bb85b JG |
40 | #include "radeon_fixed.h" |
41 | ||
42 | struct radeon_device; | |
771fe6b9 JG |
43 | |
44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) | |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) | |
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) | |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) | |
48 | ||
49 | enum radeon_connector_type { | |
50 | CONNECTOR_NONE, | |
51 | CONNECTOR_VGA, | |
52 | CONNECTOR_DVI_I, | |
53 | CONNECTOR_DVI_D, | |
54 | CONNECTOR_DVI_A, | |
55 | CONNECTOR_STV, | |
56 | CONNECTOR_CTV, | |
57 | CONNECTOR_LVDS, | |
58 | CONNECTOR_DIGITAL, | |
59 | CONNECTOR_SCART, | |
60 | CONNECTOR_HDMI_TYPE_A, | |
61 | CONNECTOR_HDMI_TYPE_B, | |
62 | CONNECTOR_0XC, | |
63 | CONNECTOR_0XD, | |
64 | CONNECTOR_DIN, | |
65 | CONNECTOR_DISPLAY_PORT, | |
66 | CONNECTOR_UNSUPPORTED | |
67 | }; | |
68 | ||
69 | enum radeon_dvi_type { | |
70 | DVI_AUTO, | |
71 | DVI_DIGITAL, | |
72 | DVI_ANALOG | |
73 | }; | |
74 | ||
75 | enum radeon_rmx_type { | |
76 | RMX_OFF, | |
77 | RMX_FULL, | |
78 | RMX_CENTER, | |
79 | RMX_ASPECT | |
80 | }; | |
81 | ||
82 | enum radeon_tv_std { | |
83 | TV_STD_NTSC, | |
84 | TV_STD_PAL, | |
85 | TV_STD_PAL_M, | |
86 | TV_STD_PAL_60, | |
87 | TV_STD_NTSC_J, | |
88 | TV_STD_SCART_PAL, | |
89 | TV_STD_SECAM, | |
90 | TV_STD_PAL_CN, | |
91 | }; | |
92 | ||
9b9fe724 AD |
93 | /* radeon gpio-based i2c |
94 | * 1. "mask" reg and bits | |
95 | * grabs the gpio pins for software use | |
96 | * 0=not held 1=held | |
97 | * 2. "a" reg and bits | |
98 | * output pin value | |
99 | * 0=low 1=high | |
100 | * 3. "en" reg and bits | |
101 | * sets the pin direction | |
102 | * 0=input 1=output | |
103 | * 4. "y" reg and bits | |
104 | * input pin value | |
105 | * 0=low 1=high | |
106 | */ | |
771fe6b9 JG |
107 | struct radeon_i2c_bus_rec { |
108 | bool valid; | |
6a93cb25 AD |
109 | /* id used by atom */ |
110 | uint8_t i2c_id; | |
111 | /* can be used with hw i2c engine */ | |
112 | bool hw_capable; | |
113 | /* uses multi-media i2c engine */ | |
114 | bool mm_i2c; | |
115 | /* regs and bits */ | |
771fe6b9 JG |
116 | uint32_t mask_clk_reg; |
117 | uint32_t mask_data_reg; | |
118 | uint32_t a_clk_reg; | |
119 | uint32_t a_data_reg; | |
9b9fe724 AD |
120 | uint32_t en_clk_reg; |
121 | uint32_t en_data_reg; | |
122 | uint32_t y_clk_reg; | |
123 | uint32_t y_data_reg; | |
771fe6b9 JG |
124 | uint32_t mask_clk_mask; |
125 | uint32_t mask_data_mask; | |
771fe6b9 JG |
126 | uint32_t a_clk_mask; |
127 | uint32_t a_data_mask; | |
9b9fe724 AD |
128 | uint32_t en_clk_mask; |
129 | uint32_t en_data_mask; | |
130 | uint32_t y_clk_mask; | |
131 | uint32_t y_data_mask; | |
771fe6b9 JG |
132 | }; |
133 | ||
134 | struct radeon_tmds_pll { | |
135 | uint32_t freq; | |
136 | uint32_t value; | |
137 | }; | |
138 | ||
139 | #define RADEON_MAX_BIOS_CONNECTOR 16 | |
140 | ||
141 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) | |
142 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) | |
143 | #define RADEON_PLL_USE_REF_DIV (1 << 2) | |
144 | #define RADEON_PLL_LEGACY (1 << 3) | |
145 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) | |
146 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) | |
147 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) | |
148 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) | |
149 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) | |
150 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | |
151 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | |
d0e275a9 | 152 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
771fe6b9 JG |
153 | |
154 | struct radeon_pll { | |
155 | uint16_t reference_freq; | |
156 | uint16_t reference_div; | |
157 | uint32_t pll_in_min; | |
158 | uint32_t pll_in_max; | |
159 | uint32_t pll_out_min; | |
160 | uint32_t pll_out_max; | |
161 | uint16_t xclk; | |
162 | ||
163 | uint32_t min_ref_div; | |
164 | uint32_t max_ref_div; | |
165 | uint32_t min_post_div; | |
166 | uint32_t max_post_div; | |
167 | uint32_t min_feedback_div; | |
168 | uint32_t max_feedback_div; | |
169 | uint32_t min_frac_feedback_div; | |
170 | uint32_t max_frac_feedback_div; | |
171 | uint32_t best_vco; | |
172 | }; | |
173 | ||
174 | struct radeon_i2c_chan { | |
771fe6b9 | 175 | struct i2c_adapter adapter; |
746c1aa4 DA |
176 | struct drm_device *dev; |
177 | union { | |
178 | struct i2c_algo_dp_aux_data dp; | |
179 | struct i2c_algo_bit_data bit; | |
180 | } algo; | |
771fe6b9 JG |
181 | struct radeon_i2c_bus_rec rec; |
182 | }; | |
183 | ||
184 | /* mostly for macs, but really any system without connector tables */ | |
185 | enum radeon_connector_table { | |
186 | CT_NONE, | |
187 | CT_GENERIC, | |
188 | CT_IBOOK, | |
189 | CT_POWERBOOK_EXTERNAL, | |
190 | CT_POWERBOOK_INTERNAL, | |
191 | CT_POWERBOOK_VGA, | |
192 | CT_MINI_EXTERNAL, | |
193 | CT_MINI_INTERNAL, | |
194 | CT_IMAC_G5_ISIGHT, | |
195 | CT_EMAC, | |
196 | }; | |
197 | ||
fcec570b AD |
198 | enum radeon_dvo_chip { |
199 | DVO_SIL164, | |
200 | DVO_SIL1178, | |
201 | }; | |
202 | ||
771fe6b9 JG |
203 | struct radeon_mode_info { |
204 | struct atom_context *atom_context; | |
61c4b24b | 205 | struct card_info *atom_card_info; |
771fe6b9 JG |
206 | enum radeon_connector_table connector_table; |
207 | bool mode_config_initialized; | |
c93bb85b | 208 | struct radeon_crtc *crtcs[2]; |
445282db DA |
209 | /* DVI-I properties */ |
210 | struct drm_property *coherent_mode_property; | |
211 | /* DAC enable load detect */ | |
212 | struct drm_property *load_detect_property; | |
213 | /* TV standard load detect */ | |
214 | struct drm_property *tv_std_property; | |
215 | /* legacy TMDS PLL detect */ | |
216 | struct drm_property *tmds_pll_property; | |
217 | ||
c93bb85b JG |
218 | }; |
219 | ||
4ce001ab DA |
220 | #define MAX_H_CODE_TIMING_LEN 32 |
221 | #define MAX_V_CODE_TIMING_LEN 32 | |
222 | ||
223 | /* need to store these as reading | |
224 | back code tables is excessive */ | |
225 | struct radeon_tv_regs { | |
226 | uint32_t tv_uv_adr; | |
227 | uint32_t timing_cntl; | |
228 | uint32_t hrestart; | |
229 | uint32_t vrestart; | |
230 | uint32_t frestart; | |
231 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; | |
232 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; | |
233 | }; | |
234 | ||
771fe6b9 JG |
235 | struct radeon_crtc { |
236 | struct drm_crtc base; | |
237 | int crtc_id; | |
238 | u16 lut_r[256], lut_g[256], lut_b[256]; | |
239 | bool enabled; | |
240 | bool can_tile; | |
241 | uint32_t crtc_offset; | |
771fe6b9 JG |
242 | struct drm_gem_object *cursor_bo; |
243 | uint64_t cursor_addr; | |
244 | int cursor_width; | |
245 | int cursor_height; | |
4162338a | 246 | uint32_t legacy_display_base_addr; |
c836e862 | 247 | uint32_t legacy_cursor_offset; |
c93bb85b | 248 | enum radeon_rmx_type rmx_type; |
c93bb85b JG |
249 | fixed20_12 vsc; |
250 | fixed20_12 hsc; | |
de2103e4 | 251 | struct drm_display_mode native_mode; |
771fe6b9 JG |
252 | }; |
253 | ||
254 | struct radeon_encoder_primary_dac { | |
255 | /* legacy primary dac */ | |
256 | uint32_t ps2_pdac_adj; | |
257 | }; | |
258 | ||
259 | struct radeon_encoder_lvds { | |
260 | /* legacy lvds */ | |
261 | uint16_t panel_vcc_delay; | |
262 | uint8_t panel_pwr_delay; | |
263 | uint8_t panel_digon_delay; | |
264 | uint8_t panel_blon_delay; | |
265 | uint16_t panel_ref_divider; | |
266 | uint8_t panel_post_divider; | |
267 | uint16_t panel_fb_divider; | |
268 | bool use_bios_dividers; | |
269 | uint32_t lvds_gen_cntl; | |
270 | /* panel mode */ | |
de2103e4 | 271 | struct drm_display_mode native_mode; |
771fe6b9 JG |
272 | }; |
273 | ||
274 | struct radeon_encoder_tv_dac { | |
275 | /* legacy tv dac */ | |
276 | uint32_t ps2_tvdac_adj; | |
277 | uint32_t ntsc_tvdac_adj; | |
278 | uint32_t pal_tvdac_adj; | |
279 | ||
4ce001ab DA |
280 | int h_pos; |
281 | int v_pos; | |
282 | int h_size; | |
283 | int supported_tv_stds; | |
284 | bool tv_on; | |
771fe6b9 | 285 | enum radeon_tv_std tv_std; |
4ce001ab | 286 | struct radeon_tv_regs tv; |
771fe6b9 JG |
287 | }; |
288 | ||
289 | struct radeon_encoder_int_tmds { | |
290 | /* legacy int tmds */ | |
291 | struct radeon_tmds_pll tmds_pll[4]; | |
292 | }; | |
293 | ||
fcec570b AD |
294 | struct radeon_encoder_ext_tmds { |
295 | /* tmds over dvo */ | |
296 | struct radeon_i2c_chan *i2c_bus; | |
297 | uint8_t slave_addr; | |
298 | enum radeon_dvo_chip dvo_chip; | |
299 | }; | |
300 | ||
ebbe1cb9 AD |
301 | /* spread spectrum */ |
302 | struct radeon_atom_ss { | |
303 | uint16_t percentage; | |
304 | uint8_t type; | |
305 | uint8_t step; | |
306 | uint8_t delay; | |
307 | uint8_t range; | |
308 | uint8_t refdiv; | |
309 | }; | |
310 | ||
771fe6b9 JG |
311 | struct radeon_encoder_atom_dig { |
312 | /* atom dig */ | |
313 | bool coherent_mode; | |
314 | int dig_block; | |
315 | /* atom lvds */ | |
316 | uint32_t lvds_misc; | |
317 | uint16_t panel_pwr_delay; | |
ebbe1cb9 | 318 | struct radeon_atom_ss *ss; |
771fe6b9 | 319 | /* panel mode */ |
de2103e4 | 320 | struct drm_display_mode native_mode; |
771fe6b9 JG |
321 | }; |
322 | ||
4ce001ab DA |
323 | struct radeon_encoder_atom_dac { |
324 | enum radeon_tv_std tv_std; | |
325 | }; | |
326 | ||
771fe6b9 JG |
327 | struct radeon_encoder { |
328 | struct drm_encoder base; | |
329 | uint32_t encoder_id; | |
330 | uint32_t devices; | |
4ce001ab | 331 | uint32_t active_device; |
771fe6b9 JG |
332 | uint32_t flags; |
333 | uint32_t pixel_clock; | |
334 | enum radeon_rmx_type rmx_type; | |
de2103e4 | 335 | struct drm_display_mode native_mode; |
771fe6b9 JG |
336 | void *enc_priv; |
337 | }; | |
338 | ||
339 | struct radeon_connector_atom_dig { | |
340 | uint32_t igp_lane_info; | |
341 | bool linkb; | |
4143e919 | 342 | /* displayport */ |
746c1aa4 | 343 | struct radeon_i2c_chan *dp_i2c_bus; |
1a66c95a | 344 | u8 dpcd[8]; |
4143e919 | 345 | u8 dp_sink_type; |
5801ead6 AD |
346 | int dp_clock; |
347 | int dp_lane_count; | |
771fe6b9 JG |
348 | }; |
349 | ||
350 | struct radeon_connector { | |
351 | struct drm_connector base; | |
352 | uint32_t connector_id; | |
353 | uint32_t devices; | |
354 | struct radeon_i2c_chan *ddc_bus; | |
0294cf4f AD |
355 | /* some systems have a an hdmi and vga port with a shared ddc line */ |
356 | bool shared_ddc; | |
4ce001ab DA |
357 | bool use_digital; |
358 | /* we need to mind the EDID between detect | |
359 | and get modes due to analog/digital/tvencoder */ | |
360 | struct edid *edid; | |
771fe6b9 | 361 | void *con_priv; |
445282db | 362 | bool dac_load_detect; |
b75fad06 | 363 | uint16_t connector_object_id; |
771fe6b9 JG |
364 | }; |
365 | ||
366 | struct radeon_framebuffer { | |
367 | struct drm_framebuffer base; | |
368 | struct drm_gem_object *obj; | |
369 | }; | |
370 | ||
5801ead6 AD |
371 | extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, |
372 | struct drm_display_mode *mode); | |
373 | extern void radeon_dp_set_link_config(struct drm_connector *connector, | |
374 | struct drm_display_mode *mode); | |
375 | extern void dp_link_train(struct drm_encoder *encoder, | |
376 | struct drm_connector *connector); | |
4143e919 | 377 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
6a93cb25 | 378 | extern void radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
5801ead6 AD |
379 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
380 | int action, uint8_t lane_num, | |
381 | uint8_t lane_set); | |
746c1aa4 DA |
382 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
383 | uint8_t write_byte, uint8_t *read_byte); | |
384 | ||
385 | extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, | |
6a93cb25 AD |
386 | struct radeon_i2c_bus_rec *rec, |
387 | const char *name); | |
771fe6b9 JG |
388 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
389 | struct radeon_i2c_bus_rec *rec, | |
390 | const char *name); | |
391 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); | |
fcec570b AD |
392 | extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, |
393 | u8 slave_addr, | |
394 | u8 addr, | |
395 | u8 *val); | |
396 | extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c, | |
397 | u8 slave_addr, | |
398 | u8 addr, | |
399 | u8 val); | |
771fe6b9 JG |
400 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
401 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); | |
402 | ||
403 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); | |
404 | ||
405 | extern void radeon_compute_pll(struct radeon_pll *pll, | |
406 | uint64_t freq, | |
407 | uint32_t *dot_clock_p, | |
408 | uint32_t *fb_div_p, | |
409 | uint32_t *frac_fb_div_p, | |
410 | uint32_t *ref_div_p, | |
411 | uint32_t *post_div_p, | |
412 | int flags); | |
413 | ||
1f3b6a45 DA |
414 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
415 | ||
771fe6b9 JG |
416 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
417 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
418 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); | |
419 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); | |
420 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); | |
421 | extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); | |
32f48ffe | 422 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
771fe6b9 | 423 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
4ce001ab | 424 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
771fe6b9 JG |
425 | |
426 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); | |
427 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
428 | struct drm_framebuffer *old_fb); | |
429 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, | |
430 | struct drm_display_mode *mode, | |
431 | struct drm_display_mode *adjusted_mode, | |
432 | int x, int y, | |
433 | struct drm_framebuffer *old_fb); | |
434 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); | |
435 | ||
436 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
437 | struct drm_framebuffer *old_fb); | |
438 | extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); | |
439 | ||
440 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, | |
441 | struct drm_file *file_priv, | |
442 | uint32_t handle, | |
443 | uint32_t width, | |
444 | uint32_t height); | |
445 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, | |
446 | int x, int y); | |
447 | ||
448 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); | |
449 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); | |
450 | extern struct radeon_encoder_atom_dig * | |
451 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); | |
fcec570b AD |
452 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
453 | struct radeon_encoder_int_tmds *tmds); | |
454 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |
455 | struct radeon_encoder_int_tmds *tmds); | |
456 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, | |
457 | struct radeon_encoder_int_tmds *tmds); | |
458 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, | |
459 | struct radeon_encoder_ext_tmds *tmds); | |
460 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, | |
461 | struct radeon_encoder_ext_tmds *tmds); | |
6fe7ac3f AD |
462 | extern struct radeon_encoder_primary_dac * |
463 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); | |
464 | extern struct radeon_encoder_tv_dac * | |
465 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
466 | extern struct radeon_encoder_lvds * |
467 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); | |
771fe6b9 JG |
468 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
469 | extern struct radeon_encoder_tv_dac * | |
470 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); | |
471 | extern struct radeon_encoder_primary_dac * | |
472 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); | |
fcec570b AD |
473 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
474 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); | |
771fe6b9 JG |
475 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
476 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); | |
477 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); | |
478 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); | |
f657c2a7 YZ |
479 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
480 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); | |
771fe6b9 JG |
481 | extern void |
482 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
483 | extern void | |
484 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
485 | extern void | |
486 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); | |
487 | extern void | |
488 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); | |
489 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
490 | u16 blue, int regno); | |
b8c00ac5 DA |
491 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
492 | u16 *blue, int regno); | |
771fe6b9 JG |
493 | struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
494 | struct drm_mode_fb_cmd *mode_cmd, | |
495 | struct drm_gem_object *obj); | |
496 | ||
497 | int radeonfb_probe(struct drm_device *dev); | |
498 | ||
499 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); | |
500 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); | |
501 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); | |
502 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
503 | struct radeon_crtc *radeon_crtc); | |
504 | void radeon_legacy_init_crtc(struct drm_device *dev, | |
505 | struct radeon_crtc *radeon_crtc); | |
ab1e9ea0 | 506 | extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state); |
771fe6b9 JG |
507 | |
508 | void radeon_get_clock_info(struct drm_device *dev); | |
509 | ||
510 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); | |
511 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); | |
512 | ||
771fe6b9 JG |
513 | void radeon_enc_destroy(struct drm_encoder *encoder); |
514 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); | |
515 | void radeon_combios_asic_init(struct drm_device *dev); | |
516 | extern int radeon_static_clocks_init(struct drm_device *dev); | |
c93bb85b JG |
517 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
518 | struct drm_display_mode *mode, | |
519 | struct drm_display_mode *adjusted_mode); | |
4ce001ab DA |
520 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
521 | ||
522 | /* legacy tv */ | |
523 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, | |
524 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, | |
525 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); | |
526 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, | |
527 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, | |
528 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); | |
529 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, | |
530 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, | |
531 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); | |
532 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, | |
533 | struct drm_display_mode *mode, | |
534 | struct drm_display_mode *adjusted_mode); | |
771fe6b9 | 535 | #endif |