[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef RADEON_MODE_H
#define RADEON_MODE_H

#include <drm_crtc.h>
#include <drm_mode.h>
#include <drm_edid.h>
#include <drm_dp_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
#include <linux/i2c-algo-bit.h>
#include "radeon_fixed.h"

struct radeon_device;

#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)

enum radeon_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum radeon_tv_std {
	TV_STD_NTSC,
	TV_STD_PAL,
	TV_STD_PAL_M,
	TV_STD_PAL_60,
	TV_STD_NTSC_J,
	TV_STD_SCART_PAL,
	TV_STD_SECAM,
	TV_STD_PAL_CN,
	TV_STD_PAL_N,
};

/* radeon gpio-based i2c
 * 1. "mask" reg and bits
 *    grabs the gpio pins for software use
 *    0=not held  1=held
 * 2. "a" reg and bits
 *    output pin value
 *    0=low 1=high
 * 3. "en" reg and bits
 *    sets the pin direction
 *    0=input 1=output
 * 4. "y" reg and bits
 *    input pin value
 *    0=low 1=high
 */
struct radeon_i2c_bus_rec {
	bool valid;
	/* id used by atom */
	uint8_t i2c_id;
	/* can be used with hw i2c engine */
	bool hw_capable;
	/* uses multi-media i2c engine */
	bool mm_i2c;
	/* regs and bits */
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t en_clk_reg;
	uint32_t en_data_reg;
	uint32_t y_clk_reg;
	uint32_t y_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
	uint32_t en_clk_mask;
	uint32_t en_data_mask;
	uint32_t y_clk_mask;
	uint32_t y_data_mask;
};

struct radeon_tmds_pll {
    uint32_t freq;
    uint32_t value;
};

#define RADEON_MAX_BIOS_CONNECTOR 16

/* pll flags */
#define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
#define RADEON_PLL_USE_REF_DIV          (1 << 2)
#define RADEON_PLL_LEGACY               (1 << 3)
#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
#define RADEON_PLL_USE_POST_DIV         (1 << 12)

/* pll algo */
enum radeon_pll_algo {
	PLL_ALGO_LEGACY,
	PLL_ALGO_AVIVO
};

struct radeon_pll {
	/* reference frequency */
	uint32_t reference_freq;

	/* fixed dividers */
	uint32_t reference_div;
	uint32_t post_div;

	/* pll in/out limits */
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint32_t best_vco;

	/* divider limits */
	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;

	/* flags for the current clock */
	uint32_t flags;

	/* pll id */
	uint32_t id;
	/* pll algo */
	enum radeon_pll_algo algo;
};

struct i2c_algo_radeon_data {
	struct i2c_adapter bit_adapter;
	struct i2c_algo_bit_data bit_data;
};

struct radeon_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	union {
		struct i2c_algo_dp_aux_data dp;
		struct i2c_algo_radeon_data radeon;
	} algo;
	struct radeon_i2c_bus_rec rec;
};

/* mostly for macs, but really any system without connector tables */
enum radeon_connector_table {
	CT_NONE,
	CT_GENERIC,
	CT_IBOOK,
	CT_POWERBOOK_EXTERNAL,
	CT_POWERBOOK_INTERNAL,
	CT_POWERBOOK_VGA,
	CT_MINI_EXTERNAL,
	CT_MINI_INTERNAL,
	CT_IMAC_G5_ISIGHT,
	CT_EMAC,
};

enum radeon_dvo_chip {
	DVO_SIL164,
	DVO_SIL1178,
};

struct radeon_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	enum radeon_connector_table connector_table;
	bool mode_config_initialized;
	struct radeon_crtc *crtcs[2];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* TV standard load detect */
	struct drm_property *tv_std_property;
	/* legacy TMDS PLL detect */
	struct drm_property *tmds_pll_property;
	/* hardcoded DFP edid from BIOS */
	struct edid *bios_hardcoded_edid;
};

#define MAX_H_CODE_TIMING_LEN 32
#define MAX_V_CODE_TIMING_LEN 32

/* need to store these as reading
   back code tables is excessive */
struct radeon_tv_regs {
	uint32_t tv_uv_adr;
	uint32_t timing_cntl;
	uint32_t hrestart;
	uint32_t vrestart;
	uint32_t frestart;
	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
};

struct radeon_crtc {
	struct drm_crtc base;
	int crtc_id;
	u16 lut_r[256], lut_g[256], lut_b[256];
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_width;
	int cursor_height;
	uint32_t legacy_display_base_addr;
	uint32_t legacy_cursor_offset;
	enum radeon_rmx_type rmx_type;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
};

struct radeon_encoder_primary_dac {
	/* legacy primary dac */
	uint32_t ps2_pdac_adj;
};

struct radeon_encoder_lvds {
	/* legacy lvds */
	uint16_t panel_vcc_delay;
	uint8_t  panel_pwr_delay;
	uint8_t  panel_digon_delay;
	uint8_t  panel_blon_delay;
	uint16_t panel_ref_divider;
	uint8_t  panel_post_divider;
	uint16_t panel_fb_divider;
	bool     use_bios_dividers;
	uint32_t lvds_gen_cntl;
	/* panel mode */
	struct drm_display_mode native_mode;
};

struct radeon_encoder_tv_dac {
	/* legacy tv dac */
	uint32_t ps2_tvdac_adj;
	uint32_t ntsc_tvdac_adj;
	uint32_t pal_tvdac_adj;

	int               h_pos;
	int               v_pos;
	int               h_size;
	int               supported_tv_stds;
	bool              tv_on;
	enum radeon_tv_std tv_std;
	struct radeon_tv_regs tv;
};

struct radeon_encoder_int_tmds {
	/* legacy int tmds */
	struct radeon_tmds_pll tmds_pll[4];
};

struct radeon_encoder_ext_tmds {
	/* tmds over dvo */
	struct radeon_i2c_chan *i2c_bus;
	uint8_t slave_addr;
	enum radeon_dvo_chip dvo_chip;
};

/* spread spectrum */
struct radeon_atom_ss {
	uint16_t percentage;
	uint8_t type;
	uint8_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
};

struct radeon_encoder_atom_dig {
	/* atom dig */
	bool coherent_mode;
	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
	/* atom lvds */
	uint32_t lvds_misc;
	uint16_t panel_pwr_delay;
	enum radeon_pll_algo pll_algo;
	struct radeon_atom_ss *ss;
	/* panel mode */
	struct drm_display_mode native_mode;
};

struct radeon_encoder_atom_dac {
	enum radeon_tv_std tv_std;
};

struct radeon_encoder {
	struct drm_encoder base;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum radeon_rmx_type rmx_type;
	struct drm_display_mode native_mode;
	void *enc_priv;
	int hdmi_offset;
	int hdmi_audio_workaround;
	int hdmi_buffer_status;
};

struct radeon_connector_atom_dig {
	uint32_t igp_lane_info;
	bool linkb;
	/* displayport */
	struct radeon_i2c_chan *dp_i2c_bus;
	u8 dpcd[8];
	u8 dp_sink_type;
	int dp_clock;
	int dp_lane_count;
};

struct radeon_gpio_rec {
	bool valid;
	u8 id;
	u32 reg;
	u32 mask;
};

enum radeon_hpd_id {
	RADEON_HPD_NONE = 0,
	RADEON_HPD_1,
	RADEON_HPD_2,
	RADEON_HPD_3,
	RADEON_HPD_4,
	RADEON_HPD_5,
	RADEON_HPD_6,
};

struct radeon_hpd {
	enum radeon_hpd_id hpd;
	u8 plugged_state;
	struct radeon_gpio_rec gpio;
};

struct radeon_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct radeon_i2c_chan *ddc_bus;
	/* some systems have a an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	void *con_priv;
	bool dac_load_detect;
	uint16_t connector_object_id;
	struct radeon_hpd hpd;
};

struct radeon_framebuffer {
	struct drm_framebuffer base;
	struct drm_gem_object *obj;
};

extern enum radeon_tv_std
radeon_combios_get_tv_info(struct radeon_device *rdev);
extern enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device *rdev);

extern void radeon_connector_hotplug(struct drm_connector *connector);
extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
				       struct drm_display_mode *mode);
extern void radeon_dp_set_link_config(struct drm_connector *connector,
				      struct drm_display_mode *mode);
extern void dp_link_train(struct drm_encoder *encoder,
			  struct drm_connector *connector);
extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
					   int action, uint8_t lane_num,
					   uint8_t lane_set);
extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
				uint8_t write_byte, uint8_t *read_byte);

extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
						    struct radeon_i2c_bus_rec *rec,
						    const char *name);
extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
						 struct radeon_i2c_bus_rec *rec,
						 const char *name);
extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c);
extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
				u8 slave_addr,
				u8 addr,
				u8 *val);
extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
				u8 slave_addr,
				u8 addr,
				u8 val);
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);

extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);

extern void radeon_compute_pll(struct radeon_pll *pll,
			       uint64_t freq,
			       uint32_t *dot_clock_p,
			       uint32_t *fb_div_p,
			       uint32_t *frac_fb_div_p,
			       uint32_t *ref_div_p,
			       uint32_t *post_div_p);

extern void radeon_setup_encoder_clones(struct drm_device *dev);

struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);

extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
				   struct drm_framebuffer *old_fb);
extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode,
				   int x, int y,
				   struct drm_framebuffer *old_fb);
extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);

extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
				 struct drm_framebuffer *old_fb);

extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
				  struct drm_file *file_priv,
				  uint32_t handle,
				  uint32_t width,
				  uint32_t height);
extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
				   int x, int y);

extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
extern struct edid *
radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
extern bool radeon_atom_get_clock_info(struct drm_device *dev);
extern bool radeon_combios_get_clock_info(struct drm_device *dev);
extern struct radeon_encoder_atom_dig *
radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
					  struct radeon_encoder_int_tmds *tmds);
extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
						     struct radeon_encoder_int_tmds *tmds);
extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
						   struct radeon_encoder_int_tmds *tmds);
extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
							 struct radeon_encoder_ext_tmds *tmds);
extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
						       struct radeon_encoder_ext_tmds *tmds);
extern struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_lvds *
radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_tv_dac *
radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
extern struct radeon_encoder_primary_dac *
radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
extern void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
extern void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
extern void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				     u16 blue, int regno);
extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
				     u16 *blue, int regno);
struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
						  struct drm_mode_fb_cmd *mode_cmd,
						  struct drm_gem_object *obj);

int radeonfb_probe(struct drm_device *dev);

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
void radeon_atombios_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc);
void radeon_legacy_init_crtc(struct drm_device *dev,
			     struct radeon_crtc *radeon_crtc);

void radeon_get_clock_info(struct drm_device *dev);

extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);

void radeon_enc_destroy(struct drm_encoder *encoder);
void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
void radeon_combios_asic_init(struct drm_device *dev);
extern int radeon_static_clocks_init(struct drm_device *dev);
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
					struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode);
void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);

/* legacy tv */
void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode);
#endif
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef RADEON_MODE_H
	31	#define RADEON_MODE_H
	32
	33	#include <drm_crtc.h>
	34	#include <drm_mode.h>
	35	#include <drm_edid.h>
746c1aa4	36	#include <drm_dp_helper.h>
771fe6b9 JG	37	#include <linux/i2c.h>
	38	#include <linux/i2c-id.h>
	39	#include <linux/i2c-algo-bit.h>
c93bb85b JG	40	#include "radeon_fixed.h"
	41
	42	struct radeon_device;
771fe6b9 JG	43
	44	#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
	45	#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
	46	#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
	47	#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
	48
771fe6b9 JG	49	enum radeon_rmx_type {
	50	RMX_OFF,
	51	RMX_FULL,
	52	RMX_CENTER,
	53	RMX_ASPECT
	54	};
	55
	56	enum radeon_tv_std {
	57	TV_STD_NTSC,
	58	TV_STD_PAL,
	59	TV_STD_PAL_M,
	60	TV_STD_PAL_60,
	61	TV_STD_NTSC_J,
	62	TV_STD_SCART_PAL,
	63	TV_STD_SECAM,
	64	TV_STD_PAL_CN,
d79766fa	65	TV_STD_PAL_N,
771fe6b9 JG	66	};
771fe6b9 JG	67
9b9fe724 AD	68	/* radeon gpio-based i2c
	69	* 1. "mask" reg and bits
	70	* grabs the gpio pins for software use
	71	* 0=not held 1=held
	72	* 2. "a" reg and bits
	73	* output pin value
	74	* 0=low 1=high
	75	* 3. "en" reg and bits
	76	* sets the pin direction
	77	* 0=input 1=output
	78	* 4. "y" reg and bits
	79	* input pin value
	80	* 0=low 1=high
	81	*/
771fe6b9 JG	82	struct radeon_i2c_bus_rec {
771fe6b9 JG	83	bool valid;
6a93cb25 AD	84	/* id used by atom */
	85	uint8_t i2c_id;
	86	/* can be used with hw i2c engine */
	87	bool hw_capable;
	88	/* uses multi-media i2c engine */
	89	bool mm_i2c;
	90	/* regs and bits */
771fe6b9 JG	91	uint32_t mask_clk_reg;
	92	uint32_t mask_data_reg;
	93	uint32_t a_clk_reg;
	94	uint32_t a_data_reg;
9b9fe724 AD	95	uint32_t en_clk_reg;
	96	uint32_t en_data_reg;
	97	uint32_t y_clk_reg;
	98	uint32_t y_data_reg;
771fe6b9 JG	99	uint32_t mask_clk_mask;
771fe6b9 JG	100	uint32_t mask_data_mask;
771fe6b9 JG	101	uint32_t a_clk_mask;
771fe6b9 JG	102	uint32_t a_data_mask;
9b9fe724 AD	103	uint32_t en_clk_mask;
	104	uint32_t en_data_mask;
	105	uint32_t y_clk_mask;
	106	uint32_t y_data_mask;
771fe6b9 JG	107	};
	108
	109	struct radeon_tmds_pll {
	110	uint32_t freq;
	111	uint32_t value;
	112	};
	113
	114	#define RADEON_MAX_BIOS_CONNECTOR 16
	115
7c27f87d	116	/* pll flags */
771fe6b9 JG	117	#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
	118	#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
	119	#define RADEON_PLL_USE_REF_DIV (1 << 2)
	120	#define RADEON_PLL_LEGACY (1 << 3)
	121	#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
	122	#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
	123	#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
	124	#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
	125	#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
	126	#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
	127	#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9	128	#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b	129	#define RADEON_PLL_USE_POST_DIV (1 << 12)
771fe6b9	130
7c27f87d AD	131	/* pll algo */
	132	enum radeon_pll_algo {
	133	PLL_ALGO_LEGACY,
	134	PLL_ALGO_AVIVO
	135	};
	136
771fe6b9	137	struct radeon_pll {
fc10332b AD	138	/* reference frequency */
	139	uint32_t reference_freq;
	140
	141	/* fixed dividers */
	142	uint32_t reference_div;
	143	uint32_t post_div;
	144
	145	/* pll in/out limits */
771fe6b9 JG	146	uint32_t pll_in_min;
	147	uint32_t pll_in_max;
	148	uint32_t pll_out_min;
	149	uint32_t pll_out_max;
fc10332b	150	uint32_t best_vco;
771fe6b9	151
fc10332b	152	/* divider limits */
771fe6b9 JG	153	uint32_t min_ref_div;
	154	uint32_t max_ref_div;
	155	uint32_t min_post_div;
	156	uint32_t max_post_div;
	157	uint32_t min_feedback_div;
	158	uint32_t max_feedback_div;
	159	uint32_t min_frac_feedback_div;
	160	uint32_t max_frac_feedback_div;
fc10332b AD	161
	162	/* flags for the current clock */
	163	uint32_t flags;
	164
	165	/* pll id */
	166	uint32_t id;
7c27f87d AD	167	/* pll algo */
7c27f87d AD	168	enum radeon_pll_algo algo;
771fe6b9 JG	169	};
771fe6b9 JG	170
5a6f98f5 AD	171	struct i2c_algo_radeon_data {
	172	struct i2c_adapter bit_adapter;
	173	struct i2c_algo_bit_data bit_data;
	174	};
	175
771fe6b9	176	struct radeon_i2c_chan {
771fe6b9	177	struct i2c_adapter adapter;
746c1aa4 DA	178	struct drm_device *dev;
	179	union {
	180	struct i2c_algo_dp_aux_data dp;
5a6f98f5	181	struct i2c_algo_radeon_data radeon;
746c1aa4	182	} algo;
771fe6b9 JG	183	struct radeon_i2c_bus_rec rec;
	184	};
	185
	186	/* mostly for macs, but really any system without connector tables */
	187	enum radeon_connector_table {
	188	CT_NONE,
	189	CT_GENERIC,
	190	CT_IBOOK,
	191	CT_POWERBOOK_EXTERNAL,
	192	CT_POWERBOOK_INTERNAL,
	193	CT_POWERBOOK_VGA,
	194	CT_MINI_EXTERNAL,
	195	CT_MINI_INTERNAL,
	196	CT_IMAC_G5_ISIGHT,
	197	CT_EMAC,
	198	};
	199
fcec570b AD	200	enum radeon_dvo_chip {
	201	DVO_SIL164,
	202	DVO_SIL1178,
	203	};
	204
771fe6b9 JG	205	struct radeon_mode_info {
771fe6b9 JG	206	struct atom_context *atom_context;
61c4b24b	207	struct card_info *atom_card_info;
771fe6b9 JG	208	enum radeon_connector_table connector_table;
771fe6b9 JG	209	bool mode_config_initialized;
c93bb85b	210	struct radeon_crtc *crtcs[2];
445282db DA	211	/* DVI-I properties */
	212	struct drm_property *coherent_mode_property;
	213	/* DAC enable load detect */
	214	struct drm_property *load_detect_property;
	215	/* TV standard load detect */
	216	struct drm_property *tv_std_property;
	217	/* legacy TMDS PLL detect */
	218	struct drm_property *tmds_pll_property;
3c537889 AD	219	/* hardcoded DFP edid from BIOS */
3c537889 AD	220	struct edid *bios_hardcoded_edid;
c93bb85b JG	221	};
c93bb85b JG	222
4ce001ab DA	223	#define MAX_H_CODE_TIMING_LEN 32
	224	#define MAX_V_CODE_TIMING_LEN 32
	225
	226	/* need to store these as reading
	227	back code tables is excessive */
	228	struct radeon_tv_regs {
	229	uint32_t tv_uv_adr;
	230	uint32_t timing_cntl;
	231	uint32_t hrestart;
	232	uint32_t vrestart;
	233	uint32_t frestart;
	234	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
	235	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
	236	};
	237
771fe6b9 JG	238	struct radeon_crtc {
	239	struct drm_crtc base;
	240	int crtc_id;
	241	u16 lut_r[256], lut_g[256], lut_b[256];
	242	bool enabled;
	243	bool can_tile;
	244	uint32_t crtc_offset;
771fe6b9 JG	245	struct drm_gem_object *cursor_bo;
	246	uint64_t cursor_addr;
	247	int cursor_width;
	248	int cursor_height;
4162338a	249	uint32_t legacy_display_base_addr;
c836e862	250	uint32_t legacy_cursor_offset;
c93bb85b	251	enum radeon_rmx_type rmx_type;
c93bb85b JG	252	fixed20_12 vsc;
c93bb85b JG	253	fixed20_12 hsc;
de2103e4	254	struct drm_display_mode native_mode;
771fe6b9 JG	255	};
	256
	257	struct radeon_encoder_primary_dac {
	258	/* legacy primary dac */
	259	uint32_t ps2_pdac_adj;
	260	};
	261
	262	struct radeon_encoder_lvds {
	263	/* legacy lvds */
	264	uint16_t panel_vcc_delay;
	265	uint8_t panel_pwr_delay;
	266	uint8_t panel_digon_delay;
	267	uint8_t panel_blon_delay;
	268	uint16_t panel_ref_divider;
	269	uint8_t panel_post_divider;
	270	uint16_t panel_fb_divider;
	271	bool use_bios_dividers;
	272	uint32_t lvds_gen_cntl;
	273	/* panel mode */
de2103e4	274	struct drm_display_mode native_mode;
771fe6b9 JG	275	};
	276
	277	struct radeon_encoder_tv_dac {
	278	/* legacy tv dac */
	279	uint32_t ps2_tvdac_adj;
	280	uint32_t ntsc_tvdac_adj;
	281	uint32_t pal_tvdac_adj;
	282
4ce001ab DA	283	int h_pos;
	284	int v_pos;
	285	int h_size;
	286	int supported_tv_stds;
	287	bool tv_on;
771fe6b9	288	enum radeon_tv_std tv_std;
4ce001ab	289	struct radeon_tv_regs tv;
771fe6b9 JG	290	};
	291
	292	struct radeon_encoder_int_tmds {
	293	/* legacy int tmds */
	294	struct radeon_tmds_pll tmds_pll[4];
	295	};
	296
fcec570b AD	297	struct radeon_encoder_ext_tmds {
	298	/* tmds over dvo */
	299	struct radeon_i2c_chan *i2c_bus;
	300	uint8_t slave_addr;
	301	enum radeon_dvo_chip dvo_chip;
	302	};
	303
ebbe1cb9 AD	304	/* spread spectrum */
	305	struct radeon_atom_ss {
	306	uint16_t percentage;
	307	uint8_t type;
	308	uint8_t step;
	309	uint8_t delay;
	310	uint8_t range;
	311	uint8_t refdiv;
	312	};
	313
771fe6b9 JG	314	struct radeon_encoder_atom_dig {
	315	/* atom dig */
	316	bool coherent_mode;
f28cf339	317	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
771fe6b9 JG	318	/* atom lvds */
	319	uint32_t lvds_misc;
	320	uint16_t panel_pwr_delay;
7c27f87d	321	enum radeon_pll_algo pll_algo;
ebbe1cb9	322	struct radeon_atom_ss *ss;
771fe6b9	323	/* panel mode */
de2103e4	324	struct drm_display_mode native_mode;
771fe6b9 JG	325	};
771fe6b9 JG	326
4ce001ab DA	327	struct radeon_encoder_atom_dac {
	328	enum radeon_tv_std tv_std;
	329	};
	330
771fe6b9 JG	331	struct radeon_encoder {
	332	struct drm_encoder base;
	333	uint32_t encoder_id;
	334	uint32_t devices;
4ce001ab	335	uint32_t active_device;
771fe6b9 JG	336	uint32_t flags;
	337	uint32_t pixel_clock;
	338	enum radeon_rmx_type rmx_type;
de2103e4	339	struct drm_display_mode native_mode;
771fe6b9	340	void *enc_priv;
dafc3bd5 CK	341	int hdmi_offset;
	342	int hdmi_audio_workaround;
	343	int hdmi_buffer_status;
771fe6b9 JG	344	};
	345
	346	struct radeon_connector_atom_dig {
	347	uint32_t igp_lane_info;
	348	bool linkb;
4143e919	349	/* displayport */
746c1aa4	350	struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a	351	u8 dpcd[8];
4143e919	352	u8 dp_sink_type;
5801ead6 AD	353	int dp_clock;
5801ead6 AD	354	int dp_lane_count;
771fe6b9 JG	355	};
771fe6b9 JG	356
eed45b30 AD	357	struct radeon_gpio_rec {
	358	bool valid;
	359	u8 id;
	360	u32 reg;
	361	u32 mask;
	362	};
	363
	364	enum radeon_hpd_id {
	365	RADEON_HPD_NONE = 0,
	366	RADEON_HPD_1,
	367	RADEON_HPD_2,
	368	RADEON_HPD_3,
	369	RADEON_HPD_4,
	370	RADEON_HPD_5,
	371	RADEON_HPD_6,
	372	};
	373
	374	struct radeon_hpd {
	375	enum radeon_hpd_id hpd;
	376	u8 plugged_state;
	377	struct radeon_gpio_rec gpio;
	378	};
	379
771fe6b9 JG	380	struct radeon_connector {
	381	struct drm_connector base;
	382	uint32_t connector_id;
	383	uint32_t devices;
	384	struct radeon_i2c_chan *ddc_bus;
0294cf4f AD	385	/* some systems have a an hdmi and vga port with a shared ddc line */
0294cf4f AD	386	bool shared_ddc;
4ce001ab DA	387	bool use_digital;
	388	/* we need to mind the EDID between detect
	389	and get modes due to analog/digital/tvencoder */
	390	struct edid *edid;
771fe6b9	391	void *con_priv;
445282db	392	bool dac_load_detect;
b75fad06	393	uint16_t connector_object_id;
eed45b30	394	struct radeon_hpd hpd;
771fe6b9 JG	395	};
	396
	397	struct radeon_framebuffer {
	398	struct drm_framebuffer base;
	399	struct drm_gem_object *obj;
	400	};
	401
d79766fa AD	402	extern enum radeon_tv_std
	403	radeon_combios_get_tv_info(struct radeon_device *rdev);
	404	extern enum radeon_tv_std
	405	radeon_atombios_get_tv_info(struct radeon_device *rdev);
	406
d4877cf2 AD	407	extern void radeon_connector_hotplug(struct drm_connector *connector);
d4877cf2 AD	408	extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6 AD	409	extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
	410	struct drm_display_mode *mode);
	411	extern void radeon_dp_set_link_config(struct drm_connector *connector,
	412	struct drm_display_mode *mode);
	413	extern void dp_link_train(struct drm_encoder *encoder,
	414	struct drm_connector *connector);
4143e919	415	extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98	416	extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
5801ead6 AD	417	extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
	418	int action, uint8_t lane_num,
	419	uint8_t lane_set);
746c1aa4 DA	420	extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
	421	uint8_t write_byte, uint8_t *read_byte);
	422
	423	extern struct radeon_i2c_chan radeon_i2c_create_dp(struct drm_device dev,
6a93cb25 AD	424	struct radeon_i2c_bus_rec *rec,
6a93cb25 AD	425	const char *name);
771fe6b9 JG	426	extern struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev,
	427	struct radeon_i2c_bus_rec *rec,
	428	const char *name);
	429	extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5 AD	430	extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c);
	431	extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
	432	u8 slave_addr,
	433	u8 addr,
	434	u8 *val);
	435	extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
	436	u8 slave_addr,
	437	u8 addr,
	438	u8 val);
771fe6b9 JG	439	extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
	440	extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
	441
	442	extern struct drm_encoder radeon_best_encoder(struct drm_connector connector);
	443
	444	extern void radeon_compute_pll(struct radeon_pll *pll,
	445	uint64_t freq,
	446	uint32_t *dot_clock_p,
	447	uint32_t *fb_div_p,
	448	uint32_t *frac_fb_div_p,
	449	uint32_t *ref_div_p,
fc10332b	450	uint32_t *post_div_p);
771fe6b9	451
1f3b6a45 DA	452	extern void radeon_setup_encoder_clones(struct drm_device *dev);
1f3b6a45 DA	453
771fe6b9 JG	454	struct drm_encoder radeon_encoder_legacy_lvds_add(struct drm_device dev, int bios_index);
	455	struct drm_encoder radeon_encoder_legacy_primary_dac_add(struct drm_device dev, int bios_index, int with_tv);
	456	struct drm_encoder radeon_encoder_legacy_tv_dac_add(struct drm_device dev, int bios_index, int with_tv);
	457	struct drm_encoder radeon_encoder_legacy_tmds_int_add(struct drm_device dev, int bios_index);
	458	struct drm_encoder radeon_encoder_legacy_tmds_ext_add(struct drm_device dev, int bios_index);
	459	extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe	460	extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9	461	extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab	462	extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9 JG	463
	464	extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
	465	extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
	466	struct drm_framebuffer *old_fb);
	467	extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
	468	struct drm_display_mode *mode,
	469	struct drm_display_mode *adjusted_mode,
	470	int x, int y,
	471	struct drm_framebuffer *old_fb);
	472	extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
	473
	474	extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
	475	struct drm_framebuffer *old_fb);
771fe6b9 JG	476
	477	extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
	478	struct drm_file *file_priv,
	479	uint32_t handle,
	480	uint32_t width,
	481	uint32_t height);
	482	extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
	483	int x, int y);
	484
3c537889 AD	485	extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
	486	extern struct edid *
	487	radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9 JG	488	extern bool radeon_atom_get_clock_info(struct drm_device *dev);
	489	extern bool radeon_combios_get_clock_info(struct drm_device *dev);
	490	extern struct radeon_encoder_atom_dig *
	491	radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b AD	492	extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
	493	struct radeon_encoder_int_tmds *tmds);
	494	extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
	495	struct radeon_encoder_int_tmds *tmds);
	496	extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
	497	struct radeon_encoder_int_tmds *tmds);
	498	extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
	499	struct radeon_encoder_ext_tmds *tmds);
	500	extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
	501	struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f AD	502	extern struct radeon_encoder_primary_dac *
	503	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
	504	extern struct radeon_encoder_tv_dac *
	505	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9 JG	506	extern struct radeon_encoder_lvds *
771fe6b9 JG	507	radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9 JG	508	extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
	509	extern struct radeon_encoder_tv_dac *
	510	radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
	511	extern struct radeon_encoder_primary_dac *
	512	radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b AD	513	extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
fcec570b AD	514	extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9 JG	515	extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
	516	extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
	517	extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
	518	extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7 YZ	519	extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
f657c2a7 YZ	520	extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9 JG	521	extern void
	522	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
	523	extern void
	524	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
	525	extern void
	526	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
	527	extern void
	528	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
	529	extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	530	u16 blue, int regno);
b8c00ac5 DA	531	extern void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
b8c00ac5 DA	532	u16 *blue, int regno);
771fe6b9 JG	533	struct drm_framebuffer radeon_framebuffer_create(struct drm_device dev,
	534	struct drm_mode_fb_cmd *mode_cmd,
	535	struct drm_gem_object *obj);
	536
	537	int radeonfb_probe(struct drm_device *dev);
	538
	539	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb);
	540	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
	541	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
	542	void radeon_atombios_init_crtc(struct drm_device *dev,
	543	struct radeon_crtc *radeon_crtc);
	544	void radeon_legacy_init_crtc(struct drm_device *dev,
	545	struct radeon_crtc *radeon_crtc);
771fe6b9 JG	546
	547	void radeon_get_clock_info(struct drm_device *dev);
	548
	549	extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
	550	extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
	551
771fe6b9 JG	552	void radeon_enc_destroy(struct drm_encoder *encoder);
	553	void radeon_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
	554	void radeon_combios_asic_init(struct drm_device *dev);
	555	extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b JG	556	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	557	struct drm_display_mode *mode,
	558	struct drm_display_mode *adjusted_mode);
4ce001ab DA	559	void atom_rv515_force_tv_scaler(struct radeon_device rdev, struct radeon_crtc radeon_crtc);
	560
	561	/* legacy tv */
	562	void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
	563	uint32_t h_total_disp, uint32_t h_sync_strt_wid,
	564	uint32_t v_total_disp, uint32_t v_sync_strt_wid);
	565	void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
	566	uint32_t htotal_cntl, uint32_t ppll_ref_div,
	567	uint32_t ppll_div_3, uint32_t pixclks_cntl);
	568	void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
	569	uint32_t htotal2_cntl, uint32_t p2pll_ref_div,
	570	uint32_t p2pll_div_0, uint32_t pixclks_cntl);
	571	void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
	572	struct drm_display_mode *mode,
	573	struct drm_display_mode *adjusted_mode);
771fe6b9	574	#endif