[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_trace.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

void radeon_bo_clear_va(struct radeon_bo *bo)
{
	struct radeon_bo_va *bo_va, *tmp;

	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
		/* remove from all vm address space */
		radeon_vm_bo_rmv(bo->rdev, bo_va);
	}
}

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	radeon_bo_clear_va(bo);
	drm_gem_object_release(&bo->gem_base);
	kfree(bo);
}

bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT) {
		if (rbo->rdev->flags & RADEON_IS_AGP) {
			rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
		} else {
			rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
		}
	}
	if (domain & RADEON_GEM_DOMAIN_CPU) {
		if (rbo->rdev->flags & RADEON_IS_AGP) {
			rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
		} else {
			rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
		}
	}
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev,
		     unsigned long size, int byte_align, bool kernel, u32 domain,
		     struct sg_table *sg, struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	size_t acc_size;
	int r;

	size = ALIGN(size, PAGE_SIZE);

	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else if (sg) {
		type = ttm_bo_type_sg;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;

	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
				       sizeof(struct radeon_bo));

	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	if (unlikely(r)) {
		kfree(bo);
		return r;
	}
	bo->rdev = rdev;
	bo->gem_base.driver_private = NULL;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);
	INIT_LIST_HEAD(&bo->va);
	radeon_ttm_placement_from_domain(bo, domain);
	/* Kernel allocation are uninterruptible */
	down_read(&rdev->pm.mclk_lock);
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, page_align, !kernel, NULL,
			acc_size, sg, &radeon_ttm_bo_destroy);
	up_read(&rdev->pm.mclk_lock);
	if (unlikely(r != 0)) {
		return r;
	}
	*bo_ptr = bo;

	trace_radeon_bo_create(bo);

	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;
	struct radeon_device *rdev;

	if ((*bo) == NULL)
		return;
	rdev = (*bo)->rdev;
	tbo = &((*bo)->tbo);
	down_read(&rdev->pm.mclk_lock);
	ttm_bo_unref(&tbo);
	up_read(&rdev->pm.mclk_lock);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
			     u64 *gpu_addr)
{
	int r, i;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);

		if (max_offset != 0) {
			u64 domain_start;

			if (domain == RADEON_GEM_DOMAIN_VRAM)
				domain_start = bo->rdev->mc.vram_start;
			else
				domain_start = bo->rdev->mc.gtt_start;
			WARN_ON_ONCE(max_offset <
				     (radeon_bo_gpu_offset(bo) - domain_start));
		}

		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
	if (max_offset) {
		u64 lpfn = max_offset >> PAGE_SHIFT;

		if (!bo->placement.lpfn)
			bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;

		if (lpfn < bo->placement.lpfn)
			bo->placement.lpfn = lpfn;
	}
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	return r;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
	return r;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
			*((unsigned long *)&bo->gem_base.refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		/* this should unref the ttm bo */
		drm_gem_object_unreference(&bo->gem_base);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	if (!rdev->fastfb_working) {
		rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
						      rdev->mc.aper_size);
	}
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
	arch_phys_wc_del(rdev->mc.vram_mtrr);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->written) {
		list_add(&lobj->tv.head, head);
	} else {
		list_add_tail(&lobj->tv.head, head);
	}
}

int radeon_bo_list_validate(struct ww_acquire_ctx *ticket,
			    struct list_head *head, int ring)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	u32 domain;
	int r;

	r = ttm_eu_reserve_buffers(ticket, head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, tv.head) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			domain = lobj->domain;
			
		retry:
			radeon_ttm_placement_from_domain(bo, domain);
			if (ring == R600_RING_TYPE_UVD_INDEX)
				radeon_uvd_force_into_uvd_segment(bo);
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
						true, false);
			if (unlikely(r)) {
				if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
					domain = lobj->alt_domain;
					goto retry;
				}
				return r;
			}
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
	}
	return 0;
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!radeon_bo_is_reserved(bo));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	struct radeon_device *rdev = bo->rdev;
	int r;

	if (rdev->family >= CHIP_CEDAR) {
		unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;

		bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
		bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
		mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
		tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
		stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
		switch (bankw) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		switch (bankh) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		switch (mtaspect) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		if (tilesplit > 6) {
			return -EINVAL;
		}
		if (stilesplit > 6) {
			return -EINVAL;
		}
	}
	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!radeon_bo_is_reserved(bo));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
	radeon_vm_bo_invalidate(rbo->rdev, rbo);
}

int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_device *rdev;
	struct radeon_bo *rbo;
	unsigned long offset, size;
	int r;

	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return 0;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
	rdev = rbo->rdev;
	if (bo->mem.mem_type == TTM_PL_VRAM) {
		size = bo->mem.num_pages << PAGE_SHIFT;
		offset = bo->mem.start << PAGE_SHIFT;
		if ((offset + size) > rdev->mc.visible_vram_size) {
			/* hurrah the memory is not visible ! */
			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
			rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
			r = ttm_bo_validate(bo, &rbo->placement, false, false);
			if (unlikely(r != 0))
				return r;
			offset = bo->mem.start << PAGE_SHIFT;
			/* this should not happen */
			if ((offset + size) > rdev->mc.visible_vram_size)
				return -EINVAL;
		}
	}
	return 0;
}

int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	if (unlikely(r != 0))
		return r;
	spin_lock(&bo->tbo.bdev->fence_lock);
	if (mem_type)
		*mem_type = bo->tbo.mem.mem_type;
	if (bo->tbo.sync_obj)
		r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
	spin_unlock(&bo->tbo.bdev->fence_lock);
	ttm_bo_unreserve(&bo->tbo);
	return r;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
5a0e3ad6	33	#include <linux/slab.h>
771fe6b9	34	#include <drm/drmP.h>
760285e7	35	#include <drm/radeon_drm.h>
771fe6b9	36	#include "radeon.h"
99ee7fac	37	#include "radeon_trace.h"
771fe6b9	38
771fe6b9 JG	39
	40	int radeon_ttm_init(struct radeon_device *rdev);
	41	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	42	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	43
	44	/*
	45	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	46	* function are calling it.
	47	*/
	48
721604a1 JG	49	void radeon_bo_clear_va(struct radeon_bo *bo)
	50	{
	51	struct radeon_bo_va bo_va, tmp;
	52
	53	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
	54	/* remove from all vm address space */
e971bd5e	55	radeon_vm_bo_rmv(bo->rdev, bo_va);
721604a1 JG	56	}
	57	}
	58
4c788679	59	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	60	{
4c788679	61	struct radeon_bo *bo;
771fe6b9	62
4c788679 JG	63	bo = container_of(tbo, struct radeon_bo, tbo);
	64	mutex_lock(&bo->rdev->gem.mutex);
	65	list_del_init(&bo->list);
	66	mutex_unlock(&bo->rdev->gem.mutex);
	67	radeon_bo_clear_surface_reg(bo);
721604a1	68	radeon_bo_clear_va(bo);
441921d5	69	drm_gem_object_release(&bo->gem_base);
4c788679	70	kfree(bo);
771fe6b9 JG	71	}
771fe6b9 JG	72
d03d8589 JG	73	bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
	74	{
	75	if (bo->destroy == &radeon_ttm_bo_destroy)
	76	return true;
	77	return false;
	78	}
	79
312ea8da JG	80	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	81	{
	82	u32 c = 0;
	83
	84	rbo->placement.fpfn = 0;
93225b0d	85	rbo->placement.lpfn = 0;
312ea8da	86	rbo->placement.placement = rbo->placements;
20707874	87	rbo->placement.busy_placement = rbo->placements;
312ea8da JG	88	if (domain & RADEON_GEM_DOMAIN_VRAM)
	89	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	90	TTM_PL_FLAG_VRAM;
0d0b3e74 JG	91	if (domain & RADEON_GEM_DOMAIN_GTT) {
	92	if (rbo->rdev->flags & RADEON_IS_AGP) {
	93	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_TT;
	94	} else {
	95	rbo->placements[c++] = TTM_PL_FLAG_CACHED \| TTM_PL_FLAG_TT;
	96	}
	97	}
	98	if (domain & RADEON_GEM_DOMAIN_CPU) {
	99	if (rbo->rdev->flags & RADEON_IS_AGP) {
dd54fee7	100	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_SYSTEM;
0d0b3e74	101	} else {
dd54fee7	102	rbo->placements[c++] = TTM_PL_FLAG_CACHED \| TTM_PL_FLAG_SYSTEM;
0d0b3e74 JG	103	}
0d0b3e74 JG	104	}
9fb03e63 JG	105	if (!c)
9fb03e63 JG	106	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
312ea8da JG	107	rbo->placement.num_placement = c;
	108	rbo->placement.num_busy_placement = c;
	109	}
	110
441921d5	111	int radeon_bo_create(struct radeon_device *rdev,
268b2510	112	unsigned long size, int byte_align, bool kernel, u32 domain,
40f5cf99	113	struct sg_table sg, struct radeon_bo *bo_ptr)
771fe6b9	114	{
4c788679	115	struct radeon_bo *bo;
771fe6b9	116	enum ttm_bo_type type;
93225b0d	117	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
57de4ba9	118	size_t acc_size;
771fe6b9 JG	119	int r;
771fe6b9 JG	120
441921d5 DV	121	size = ALIGN(size, PAGE_SIZE);
441921d5 DV	122
949c4a34	123	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
771fe6b9 JG	124	if (kernel) {
771fe6b9 JG	125	type = ttm_bo_type_kernel;
40f5cf99 AD	126	} else if (sg) {
40f5cf99 AD	127	type = ttm_bo_type_sg;
771fe6b9 JG	128	} else {
	129	type = ttm_bo_type_device;
	130	}
4c788679	131	*bo_ptr = NULL;
2b66b50b	132
57de4ba9 JG	133	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
	134	sizeof(struct radeon_bo));
	135
4c788679 JG	136	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
4c788679 JG	137	if (bo == NULL)
771fe6b9	138	return -ENOMEM;
441921d5 DV	139	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	140	if (unlikely(r)) {
	141	kfree(bo);
	142	return r;
	143	}
4c788679	144	bo->rdev = rdev;
7e4d15d9	145	bo->gem_base.driver_private = NULL;
4c788679 JG	146	bo->surface_reg = -1;
4c788679 JG	147	INIT_LIST_HEAD(&bo->list);
721604a1	148	INIT_LIST_HEAD(&bo->va);
1fb107fc	149	radeon_ttm_placement_from_domain(bo, domain);
5cc6fbab	150	/* Kernel allocation are uninterruptible */
db7fce39	151	down_read(&rdev->pm.mclk_lock);
1fb107fc	152	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
0b91c4a1	153	&bo->placement, page_align, !kernel, NULL,
40f5cf99	154	acc_size, sg, &radeon_ttm_bo_destroy);
db7fce39	155	up_read(&rdev->pm.mclk_lock);
771fe6b9	156	if (unlikely(r != 0)) {
771fe6b9 JG	157	return r;
771fe6b9 JG	158	}
4c788679	159	*bo_ptr = bo;
441921d5	160
99ee7fac	161	trace_radeon_bo_create(bo);
441921d5	162
771fe6b9 JG	163	return 0;
	164	}
	165
4c788679	166	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	167	{
4c788679	168	bool is_iomem;
771fe6b9 JG	169	int r;
771fe6b9 JG	170
4c788679	171	if (bo->kptr) {
771fe6b9	172	if (ptr) {
4c788679	173	*ptr = bo->kptr;
771fe6b9	174	}
771fe6b9 JG	175	return 0;
771fe6b9 JG	176	}
4c788679	177	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	178	if (r) {
	179	return r;
	180	}
4c788679	181	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	182	if (ptr) {
4c788679	183	*ptr = bo->kptr;
771fe6b9	184	}
4c788679	185	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	186	return 0;
	187	}
	188
4c788679	189	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	190	{
4c788679	191	if (bo->kptr == NULL)
771fe6b9	192	return;
4c788679 JG	193	bo->kptr = NULL;
	194	radeon_bo_check_tiling(bo, 0, 0);
	195	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	196	}
771fe6b9 JG	197
4c788679	198	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	199	{
4c788679	200	struct ttm_buffer_object *tbo;
f4b7fb94	201	struct radeon_device *rdev;
771fe6b9	202
4c788679	203	if ((*bo) == NULL)
771fe6b9	204	return;
f4b7fb94	205	rdev = (*bo)->rdev;
4c788679	206	tbo = &((*bo)->tbo);
db7fce39	207	down_read(&rdev->pm.mclk_lock);
4c788679	208	ttm_bo_unref(&tbo);
db7fce39	209	up_read(&rdev->pm.mclk_lock);
4c788679 JG	210	if (tbo == NULL)
4c788679 JG	211	*bo = NULL;
771fe6b9 JG	212	}
771fe6b9 JG	213
c4353016 MD	214	int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
c4353016 MD	215	u64 *gpu_addr)
771fe6b9	216	{
312ea8da	217	int r, i;
771fe6b9	218
4c788679 JG	219	if (bo->pin_count) {
	220	bo->pin_count++;
	221	if (gpu_addr)
	222	*gpu_addr = radeon_bo_gpu_offset(bo);
d936622c MD	223
	224	if (max_offset != 0) {
	225	u64 domain_start;
	226
	227	if (domain == RADEON_GEM_DOMAIN_VRAM)
	228	domain_start = bo->rdev->mc.vram_start;
	229	else
	230	domain_start = bo->rdev->mc.gtt_start;
e199fd42 MD	231	WARN_ON_ONCE(max_offset <
e199fd42 MD	232	(radeon_bo_gpu_offset(bo) - domain_start));
d936622c MD	233	}
d936622c MD	234
771fe6b9 JG	235	return 0;
771fe6b9 JG	236	}
312ea8da	237	radeon_ttm_placement_from_domain(bo, domain);
3ca82da3 MD	238	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	239	/* force to pin into visible video ram */
	240	bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	241	}
c4353016 MD	242	if (max_offset) {
	243	u64 lpfn = max_offset >> PAGE_SHIFT;
	244
	245	if (!bo->placement.lpfn)
	246	bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
	247
	248	if (lpfn < bo->placement.lpfn)
	249	bo->placement.lpfn = lpfn;
	250	}
312ea8da JG	251	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	252	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
97a875cb	253	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
4c788679 JG	254	if (likely(r == 0)) {
	255	bo->pin_count = 1;
	256	if (gpu_addr != NULL)
	257	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	258	}
5cc6fbab	259	if (unlikely(r != 0))
4c788679	260	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 JG	261	return r;
771fe6b9 JG	262	}
c4353016 MD	263
	264	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
	265	{
	266	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
	267	}
771fe6b9	268
4c788679	269	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	270	{
312ea8da	271	int r, i;
771fe6b9	272
4c788679 JG	273	if (!bo->pin_count) {
	274	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	275	return 0;
771fe6b9	276	}
4c788679 JG	277	bo->pin_count--;
	278	if (bo->pin_count)
	279	return 0;
312ea8da JG	280	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	281	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
97a875cb	282	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
5cc6fbab	283	if (unlikely(r != 0))
4c788679	284	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
5cc6fbab	285	return r;
cefb87ef DA	286	}
cefb87ef DA	287
4c788679	288	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9	289	{
d796d844 DA	290	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
d796d844 DA	291	if (0 && (rdev->flags & RADEON_IS_IGP)) {
06b6476d AD	292	if (rdev->mc.igp_sideport_enabled == false)
	293	/* Useless to evict on IGP chips */
	294	return 0;
771fe6b9 JG	295	}
	296	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	297	}
	298
4c788679	299	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	300	{
4c788679	301	struct radeon_bo bo, n;
771fe6b9 JG	302
	303	if (list_empty(&rdev->gem.objects)) {
	304	return;
	305	}
4c788679 JG	306	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	307	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	308	mutex_lock(&rdev->ddev->struct_mutex);
4c788679	309	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
31c3603d DV	310	&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
31c3603d DV	311	((unsigned long )&bo->gem_base.refcount));
4c788679 JG	312	mutex_lock(&bo->rdev->gem.mutex);
	313	list_del_init(&bo->list);
	314	mutex_unlock(&bo->rdev->gem.mutex);
91132d6b	315	/* this should unref the ttm bo */
31c3603d	316	drm_gem_object_unreference(&bo->gem_base);
771fe6b9 JG	317	mutex_unlock(&rdev->ddev->struct_mutex);
	318	}
	319	}
	320
4c788679	321	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	322	{
a4d68279	323	/* Add an MTRR for the VRAM */
a0a53aa8	324	if (!rdev->fastfb_working) {
07ebea25 AL	325	rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
07ebea25 AL	326	rdev->mc.aper_size);
a0a53aa8	327	}
a4d68279 JG	328	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	329	rdev->mc.mc_vram_size >> 20,
	330	(unsigned long long)rdev->mc.aper_size >> 20);
	331	DRM_INFO("RAM width %dbits %cDR\n",
	332	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	333	return radeon_ttm_init(rdev);
	334	}
	335
4c788679	336	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	337	{
771fe6b9 JG	338	radeon_ttm_fini(rdev);
07ebea25	339	arch_phys_wc_del(rdev->mc.vram_mtrr);
771fe6b9 JG	340	}
771fe6b9 JG	341
4c788679 JG	342	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	343	struct list_head *head)
771fe6b9	344	{
4474f3a9	345	if (lobj->written) {
147666fb	346	list_add(&lobj->tv.head, head);
771fe6b9	347	} else {
147666fb	348	list_add_tail(&lobj->tv.head, head);
771fe6b9 JG	349	}
	350	}
	351
ecff665f ML	352	int radeon_bo_list_validate(struct ww_acquire_ctx *ticket,
ecff665f ML	353	struct list_head *head, int ring)
771fe6b9	354	{
4c788679 JG	355	struct radeon_bo_list *lobj;
4c788679 JG	356	struct radeon_bo *bo;
20707874	357	u32 domain;
771fe6b9 JG	358	int r;
771fe6b9 JG	359
ecff665f	360	r = ttm_eu_reserve_buffers(ticket, head);
771fe6b9	361	if (unlikely(r != 0)) {
771fe6b9 JG	362	return r;
771fe6b9 JG	363	}
147666fb	364	list_for_each_entry(lobj, head, tv.head) {
4c788679 JG	365	bo = lobj->bo;
4c788679 JG	366	if (!bo->pin_count) {
4474f3a9	367	domain = lobj->domain;
20707874 AD	368
	369	retry:
	370	radeon_ttm_placement_from_domain(bo, domain);
f2ba57b5 CK	371	if (ring == R600_RING_TYPE_UVD_INDEX)
f2ba57b5 CK	372	radeon_uvd_force_into_uvd_segment(bo);
1fb107fc	373	r = ttm_bo_validate(&bo->tbo, &bo->placement,
97a875cb	374	true, false);
e376573f	375	if (unlikely(r)) {
4474f3a9 CK	376	if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
4474f3a9 CK	377	domain = lobj->alt_domain;
20707874 AD	378	goto retry;
20707874 AD	379	}
771fe6b9	380	return r;
e376573f	381	}
771fe6b9	382	}
4c788679 JG	383	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	384	lobj->tiling_flags = bo->tiling_flags;
771fe6b9 JG	385	}
	386	return 0;
	387	}
	388
4c788679	389	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	390	struct vm_area_struct *vma)
771fe6b9 JG	391	{
4c788679	392	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	393	}
771fe6b9 JG	394
550e2d92	395	int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	396	{
4c788679	397	struct radeon_device *rdev = bo->rdev;
e024e110	398	struct radeon_surface_reg *reg;
4c788679	399	struct radeon_bo *old_object;
e024e110 DA	400	int steal;
	401	int i;
	402
0a46fb5f	403	BUG_ON(!radeon_bo_is_reserved(bo));
4c788679 JG	404
4c788679 JG	405	if (!bo->tiling_flags)
e024e110 DA	406	return 0;
e024e110 DA	407
4c788679 JG	408	if (bo->surface_reg >= 0) {
	409	reg = &rdev->surface_regs[bo->surface_reg];
	410	i = bo->surface_reg;
e024e110 DA	411	goto out;
	412	}
	413
	414	steal = -1;
	415	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	416
	417	reg = &rdev->surface_regs[i];
4c788679	418	if (!reg->bo)
e024e110 DA	419	break;
e024e110 DA	420
4c788679	421	old_object = reg->bo;
e024e110 DA	422	if (old_object->pin_count == 0)
	423	steal = i;
	424	}
	425
	426	/* if we are all out */
	427	if (i == RADEON_GEM_MAX_SURFACES) {
	428	if (steal == -1)
	429	return -ENOMEM;
	430	/* find someone with a surface reg and nuke their BO */
	431	reg = &rdev->surface_regs[steal];
4c788679	432	old_object = reg->bo;
e024e110 DA	433	/* blow away the mapping */
e024e110 DA	434	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	435	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	436	old_object->surface_reg = -1;
	437	i = steal;
	438	}
	439
4c788679 JG	440	bo->surface_reg = i;
4c788679 JG	441	reg->bo = bo;
e024e110 DA	442
e024e110 DA	443	out:
4c788679	444	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
d961db75	445	bo->tbo.mem.start << PAGE_SHIFT,
4c788679	446	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	447	return 0;
	448	}
	449
4c788679	450	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	451	{
4c788679	452	struct radeon_device *rdev = bo->rdev;
e024e110 DA	453	struct radeon_surface_reg *reg;
e024e110 DA	454
4c788679	455	if (bo->surface_reg == -1)
e024e110 DA	456	return;
e024e110 DA	457
4c788679 JG	458	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	459	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	460
4c788679 JG	461	reg->bo = NULL;
4c788679 JG	462	bo->surface_reg = -1;
e024e110 DA	463	}
e024e110 DA	464
4c788679 JG	465	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	466	uint32_t tiling_flags, uint32_t pitch)
e024e110	467	{
285484e2	468	struct radeon_device *rdev = bo->rdev;
4c788679 JG	469	int r;
4c788679 JG	470
285484e2 JG	471	if (rdev->family >= CHIP_CEDAR) {
	472	unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
	473
	474	bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
	475	bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
	476	mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
	477	tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
	478	stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
	479	switch (bankw) {
	480	case 0:
	481	case 1:
	482	case 2:
	483	case 4:
	484	case 8:
	485	break;
	486	default:
	487	return -EINVAL;
	488	}
	489	switch (bankh) {
	490	case 0:
	491	case 1:
	492	case 2:
	493	case 4:
	494	case 8:
	495	break;
	496	default:
	497	return -EINVAL;
	498	}
	499	switch (mtaspect) {
	500	case 0:
	501	case 1:
	502	case 2:
	503	case 4:
	504	case 8:
	505	break;
	506	default:
	507	return -EINVAL;
	508	}
	509	if (tilesplit > 6) {
	510	return -EINVAL;
	511	}
	512	if (stilesplit > 6) {
	513	return -EINVAL;
	514	}
	515	}
4c788679 JG	516	r = radeon_bo_reserve(bo, false);
	517	if (unlikely(r != 0))
	518	return r;
	519	bo->tiling_flags = tiling_flags;
	520	bo->pitch = pitch;
	521	radeon_bo_unreserve(bo);
	522	return 0;
e024e110 DA	523	}
e024e110 DA	524
4c788679 JG	525	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	526	uint32_t *tiling_flags,
	527	uint32_t *pitch)
e024e110	528	{
0a46fb5f	529	BUG_ON(!radeon_bo_is_reserved(bo));
e024e110	530	if (tiling_flags)
4c788679	531	*tiling_flags = bo->tiling_flags;
e024e110	532	if (pitch)
4c788679	533	*pitch = bo->pitch;
e024e110 DA	534	}
e024e110 DA	535
4c788679 JG	536	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	537	bool force_drop)
e024e110	538	{
6ed9ccb4	539	BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
4c788679 JG	540
4c788679 JG	541	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	542	return 0;
	543
	544	if (force_drop) {
4c788679	545	radeon_bo_clear_surface_reg(bo);
e024e110 DA	546	return 0;
	547	}
	548
4c788679	549	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	550	if (!has_moved)
	551	return 0;
	552
4c788679 JG	553	if (bo->surface_reg >= 0)
4c788679 JG	554	radeon_bo_clear_surface_reg(bo);
e024e110 DA	555	return 0;
	556	}
	557
4c788679	558	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	559	return 0;
e024e110 DA	560
4c788679	561	return radeon_bo_get_surface_reg(bo);
e024e110 DA	562	}
	563
	564	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
d03d8589	565	struct ttm_mem_reg *mem)
e024e110	566	{
d03d8589 JG	567	struct radeon_bo *rbo;
	568	if (!radeon_ttm_bo_is_radeon_bo(bo))
	569	return;
	570	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	571	radeon_bo_check_tiling(rbo, 0, 1);
721604a1	572	radeon_vm_bo_invalidate(rbo->rdev, rbo);
e024e110 DA	573	}
e024e110 DA	574
0a2d50e3	575	int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
e024e110	576	{
0a2d50e3	577	struct radeon_device *rdev;
d03d8589	578	struct radeon_bo *rbo;
0a2d50e3 JG	579	unsigned long offset, size;
	580	int r;
	581
d03d8589	582	if (!radeon_ttm_bo_is_radeon_bo(bo))
0a2d50e3	583	return 0;
d03d8589	584	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	585	radeon_bo_check_tiling(rbo, 0, 0);
0a2d50e3 JG	586	rdev = rbo->rdev;
	587	if (bo->mem.mem_type == TTM_PL_VRAM) {
	588	size = bo->mem.num_pages << PAGE_SHIFT;
d961db75	589	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	590	if ((offset + size) > rdev->mc.visible_vram_size) {
	591	/* hurrah the memory is not visible ! */
	592	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
	593	rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
97a875cb	594	r = ttm_bo_validate(bo, &rbo->placement, false, false);
0a2d50e3 JG	595	if (unlikely(r != 0))
0a2d50e3 JG	596	return r;
d961db75	597	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	598	/* this should not happen */
	599	if ((offset + size) > rdev->mc.visible_vram_size)
	600	return -EINVAL;
	601	}
	602	}
	603	return 0;
e024e110	604	}
ce580fab	605
83f30d0e	606	int radeon_bo_wait(struct radeon_bo bo, u32 mem_type, bool no_wait)
ce580fab AK	607	{
	608	int r;
	609
	610	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	611	if (unlikely(r != 0))
	612	return r;
	613	spin_lock(&bo->tbo.bdev->fence_lock);
	614	if (mem_type)
	615	*mem_type = bo->tbo.mem.mem_type;
	616	if (bo->tbo.sync_obj)
1717c0e2	617	r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
ce580fab AK	618	spin_unlock(&bo->tbo.bdev->fence_lock);
	619	ttm_bo_unreserve(&bo->tbo);
	620	return r;
	621	}