Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 JG |
34 | #include <drm/drmP.h> |
35 | #include "radeon_drm.h" | |
36 | #include "radeon.h" | |
37 | ||
771fe6b9 JG |
38 | |
39 | int radeon_ttm_init(struct radeon_device *rdev); | |
40 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 41 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
42 | |
43 | /* | |
44 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
45 | * function are calling it. | |
46 | */ | |
47 | ||
4c788679 | 48 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 49 | { |
4c788679 | 50 | struct radeon_bo *bo; |
771fe6b9 | 51 | |
4c788679 JG |
52 | bo = container_of(tbo, struct radeon_bo, tbo); |
53 | mutex_lock(&bo->rdev->gem.mutex); | |
54 | list_del_init(&bo->list); | |
55 | mutex_unlock(&bo->rdev->gem.mutex); | |
56 | radeon_bo_clear_surface_reg(bo); | |
57 | kfree(bo); | |
771fe6b9 JG |
58 | } |
59 | ||
d03d8589 JG |
60 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
61 | { | |
62 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
63 | return true; | |
64 | return false; | |
65 | } | |
66 | ||
312ea8da JG |
67 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
68 | { | |
69 | u32 c = 0; | |
70 | ||
71 | rbo->placement.fpfn = 0; | |
72 | rbo->placement.lpfn = 0; | |
73 | rbo->placement.placement = rbo->placements; | |
74 | rbo->placement.busy_placement = rbo->placements; | |
75 | if (domain & RADEON_GEM_DOMAIN_VRAM) | |
76 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | | |
77 | TTM_PL_FLAG_VRAM; | |
78 | if (domain & RADEON_GEM_DOMAIN_GTT) | |
79 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
80 | if (domain & RADEON_GEM_DOMAIN_CPU) | |
81 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
9fb03e63 JG |
82 | if (!c) |
83 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
312ea8da JG |
84 | rbo->placement.num_placement = c; |
85 | rbo->placement.num_busy_placement = c; | |
86 | } | |
87 | ||
4c788679 JG |
88 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
89 | unsigned long size, bool kernel, u32 domain, | |
90 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 91 | { |
4c788679 | 92 | struct radeon_bo *bo; |
771fe6b9 | 93 | enum ttm_bo_type type; |
771fe6b9 JG |
94 | int r; |
95 | ||
96 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { | |
97 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
98 | } | |
99 | if (kernel) { | |
100 | type = ttm_bo_type_kernel; | |
101 | } else { | |
102 | type = ttm_bo_type_device; | |
103 | } | |
4c788679 JG |
104 | *bo_ptr = NULL; |
105 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); | |
106 | if (bo == NULL) | |
771fe6b9 | 107 | return -ENOMEM; |
4c788679 JG |
108 | bo->rdev = rdev; |
109 | bo->gobj = gobj; | |
110 | bo->surface_reg = -1; | |
111 | INIT_LIST_HEAD(&bo->list); | |
112 | ||
1fb107fc | 113 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 114 | /* Kernel allocation are uninterruptible */ |
5876dd24 | 115 | mutex_lock(&rdev->vram_mutex); |
1fb107fc JG |
116 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
117 | &bo->placement, 0, 0, !kernel, NULL, size, | |
118 | &radeon_ttm_bo_destroy); | |
5876dd24 | 119 | mutex_unlock(&rdev->vram_mutex); |
771fe6b9 | 120 | if (unlikely(r != 0)) { |
5cc6fbab TH |
121 | if (r != -ERESTARTSYS) |
122 | dev_err(rdev->dev, | |
1fb107fc JG |
123 | "object_init failed for (%lu, 0x%08X)\n", |
124 | size, domain); | |
771fe6b9 JG |
125 | return r; |
126 | } | |
4c788679 | 127 | *bo_ptr = bo; |
771fe6b9 | 128 | if (gobj) { |
4c788679 JG |
129 | mutex_lock(&bo->rdev->gem.mutex); |
130 | list_add_tail(&bo->list, &rdev->gem.objects); | |
131 | mutex_unlock(&bo->rdev->gem.mutex); | |
771fe6b9 JG |
132 | } |
133 | return 0; | |
134 | } | |
135 | ||
4c788679 | 136 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 137 | { |
4c788679 | 138 | bool is_iomem; |
771fe6b9 JG |
139 | int r; |
140 | ||
4c788679 | 141 | if (bo->kptr) { |
771fe6b9 | 142 | if (ptr) { |
4c788679 | 143 | *ptr = bo->kptr; |
771fe6b9 | 144 | } |
771fe6b9 JG |
145 | return 0; |
146 | } | |
4c788679 | 147 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
148 | if (r) { |
149 | return r; | |
150 | } | |
4c788679 | 151 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 152 | if (ptr) { |
4c788679 | 153 | *ptr = bo->kptr; |
771fe6b9 | 154 | } |
4c788679 | 155 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
156 | return 0; |
157 | } | |
158 | ||
4c788679 | 159 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 160 | { |
4c788679 | 161 | if (bo->kptr == NULL) |
771fe6b9 | 162 | return; |
4c788679 JG |
163 | bo->kptr = NULL; |
164 | radeon_bo_check_tiling(bo, 0, 0); | |
165 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
166 | } |
167 | ||
4c788679 | 168 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 169 | { |
4c788679 | 170 | struct ttm_buffer_object *tbo; |
771fe6b9 | 171 | |
4c788679 | 172 | if ((*bo) == NULL) |
771fe6b9 | 173 | return; |
4c788679 | 174 | tbo = &((*bo)->tbo); |
5876dd24 | 175 | mutex_lock(&(*bo)->rdev->vram_mutex); |
4c788679 | 176 | ttm_bo_unref(&tbo); |
5876dd24 | 177 | mutex_unlock(&(*bo)->rdev->vram_mutex); |
4c788679 JG |
178 | if (tbo == NULL) |
179 | *bo = NULL; | |
771fe6b9 JG |
180 | } |
181 | ||
4c788679 | 182 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
771fe6b9 | 183 | { |
312ea8da | 184 | int r, i; |
771fe6b9 | 185 | |
4c788679 JG |
186 | if (bo->pin_count) { |
187 | bo->pin_count++; | |
188 | if (gpu_addr) | |
189 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 JG |
190 | return 0; |
191 | } | |
312ea8da | 192 | radeon_ttm_placement_from_domain(bo, domain); |
3ca82da3 MD |
193 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
194 | /* force to pin into visible video ram */ | |
195 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
196 | } | |
312ea8da JG |
197 | for (i = 0; i < bo->placement.num_placement; i++) |
198 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
9d87fa21 | 199 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
4c788679 JG |
200 | if (likely(r == 0)) { |
201 | bo->pin_count = 1; | |
202 | if (gpu_addr != NULL) | |
203 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 | 204 | } |
5cc6fbab | 205 | if (unlikely(r != 0)) |
4c788679 | 206 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
771fe6b9 JG |
207 | return r; |
208 | } | |
209 | ||
4c788679 | 210 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 211 | { |
312ea8da | 212 | int r, i; |
771fe6b9 | 213 | |
4c788679 JG |
214 | if (!bo->pin_count) { |
215 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
216 | return 0; | |
771fe6b9 | 217 | } |
4c788679 JG |
218 | bo->pin_count--; |
219 | if (bo->pin_count) | |
220 | return 0; | |
312ea8da JG |
221 | for (i = 0; i < bo->placement.num_placement; i++) |
222 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
9d87fa21 | 223 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
5cc6fbab | 224 | if (unlikely(r != 0)) |
4c788679 | 225 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
5cc6fbab | 226 | return r; |
cefb87ef DA |
227 | } |
228 | ||
4c788679 | 229 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 230 | { |
d796d844 DA |
231 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
232 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
233 | if (rdev->mc.igp_sideport_enabled == false) |
234 | /* Useless to evict on IGP chips */ | |
235 | return 0; | |
771fe6b9 JG |
236 | } |
237 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
238 | } | |
239 | ||
4c788679 | 240 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 241 | { |
4c788679 | 242 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
243 | struct drm_gem_object *gobj; |
244 | ||
245 | if (list_empty(&rdev->gem.objects)) { | |
246 | return; | |
247 | } | |
4c788679 JG |
248 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
249 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 250 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 JG |
251 | gobj = bo->gobj; |
252 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", | |
253 | gobj, bo, (unsigned long)gobj->size, | |
254 | *((unsigned long *)&gobj->refcount)); | |
255 | mutex_lock(&bo->rdev->gem.mutex); | |
256 | list_del_init(&bo->list); | |
257 | mutex_unlock(&bo->rdev->gem.mutex); | |
258 | radeon_bo_unref(&bo); | |
771fe6b9 JG |
259 | gobj->driver_private = NULL; |
260 | drm_gem_object_unreference(gobj); | |
261 | mutex_unlock(&rdev->ddev->struct_mutex); | |
262 | } | |
263 | } | |
264 | ||
4c788679 | 265 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 266 | { |
a4d68279 JG |
267 | /* Add an MTRR for the VRAM */ |
268 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | |
269 | MTRR_TYPE_WRCOMB, 1); | |
270 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", | |
271 | rdev->mc.mc_vram_size >> 20, | |
272 | (unsigned long long)rdev->mc.aper_size >> 20); | |
273 | DRM_INFO("RAM width %dbits %cDR\n", | |
274 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
275 | return radeon_ttm_init(rdev); |
276 | } | |
277 | ||
4c788679 | 278 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
279 | { |
280 | radeon_ttm_fini(rdev); | |
281 | } | |
282 | ||
4c788679 JG |
283 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
284 | struct list_head *head) | |
771fe6b9 JG |
285 | { |
286 | if (lobj->wdomain) { | |
287 | list_add(&lobj->list, head); | |
288 | } else { | |
289 | list_add_tail(&lobj->list, head); | |
290 | } | |
291 | } | |
292 | ||
4c788679 | 293 | int radeon_bo_list_reserve(struct list_head *head) |
771fe6b9 | 294 | { |
4c788679 | 295 | struct radeon_bo_list *lobj; |
771fe6b9 JG |
296 | int r; |
297 | ||
9d8401fc | 298 | list_for_each_entry(lobj, head, list){ |
4c788679 JG |
299 | r = radeon_bo_reserve(lobj->bo, false); |
300 | if (unlikely(r != 0)) | |
301 | return r; | |
771fe6b9 JG |
302 | } |
303 | return 0; | |
304 | } | |
305 | ||
4c788679 | 306 | void radeon_bo_list_unreserve(struct list_head *head) |
771fe6b9 | 307 | { |
4c788679 | 308 | struct radeon_bo_list *lobj; |
771fe6b9 | 309 | |
9d8401fc | 310 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
311 | /* only unreserve object we successfully reserved */ |
312 | if (radeon_bo_is_reserved(lobj->bo)) | |
313 | radeon_bo_unreserve(lobj->bo); | |
771fe6b9 JG |
314 | } |
315 | } | |
316 | ||
6cb8e1f7 | 317 | int radeon_bo_list_validate(struct list_head *head) |
771fe6b9 | 318 | { |
4c788679 JG |
319 | struct radeon_bo_list *lobj; |
320 | struct radeon_bo *bo; | |
771fe6b9 JG |
321 | int r; |
322 | ||
4c788679 | 323 | r = radeon_bo_list_reserve(head); |
771fe6b9 | 324 | if (unlikely(r != 0)) { |
771fe6b9 JG |
325 | return r; |
326 | } | |
9d8401fc | 327 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
328 | bo = lobj->bo; |
329 | if (!bo->pin_count) { | |
664f8659 | 330 | if (lobj->wdomain) { |
312ea8da JG |
331 | radeon_ttm_placement_from_domain(bo, |
332 | lobj->wdomain); | |
664f8659 | 333 | } else { |
312ea8da JG |
334 | radeon_ttm_placement_from_domain(bo, |
335 | lobj->rdomain); | |
664f8659 | 336 | } |
1fb107fc | 337 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
9d87fa21 | 338 | true, false, false); |
5cc6fbab | 339 | if (unlikely(r)) |
771fe6b9 | 340 | return r; |
771fe6b9 | 341 | } |
4c788679 JG |
342 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
343 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 JG |
344 | } |
345 | return 0; | |
346 | } | |
347 | ||
6cb8e1f7 | 348 | void radeon_bo_list_fence(struct list_head *head, void *fence) |
771fe6b9 | 349 | { |
4c788679 | 350 | struct radeon_bo_list *lobj; |
6cb8e1f7 JG |
351 | struct radeon_bo *bo; |
352 | struct radeon_fence *old_fence = NULL; | |
353 | ||
354 | list_for_each_entry(lobj, head, list) { | |
355 | bo = lobj->bo; | |
356 | spin_lock(&bo->tbo.lock); | |
357 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; | |
358 | bo->tbo.sync_obj = radeon_fence_ref(fence); | |
359 | bo->tbo.sync_obj_arg = NULL; | |
360 | spin_unlock(&bo->tbo.lock); | |
361 | if (old_fence) { | |
362 | radeon_fence_unref(&old_fence); | |
771fe6b9 | 363 | } |
6cb8e1f7 | 364 | } |
771fe6b9 JG |
365 | } |
366 | ||
4c788679 | 367 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
771fe6b9 JG |
368 | struct vm_area_struct *vma) |
369 | { | |
4c788679 | 370 | return ttm_fbdev_mmap(vma, &bo->tbo); |
771fe6b9 JG |
371 | } |
372 | ||
550e2d92 | 373 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 374 | { |
4c788679 | 375 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 376 | struct radeon_surface_reg *reg; |
4c788679 | 377 | struct radeon_bo *old_object; |
e024e110 DA |
378 | int steal; |
379 | int i; | |
380 | ||
4c788679 JG |
381 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
382 | ||
383 | if (!bo->tiling_flags) | |
e024e110 DA |
384 | return 0; |
385 | ||
4c788679 JG |
386 | if (bo->surface_reg >= 0) { |
387 | reg = &rdev->surface_regs[bo->surface_reg]; | |
388 | i = bo->surface_reg; | |
e024e110 DA |
389 | goto out; |
390 | } | |
391 | ||
392 | steal = -1; | |
393 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
394 | ||
395 | reg = &rdev->surface_regs[i]; | |
4c788679 | 396 | if (!reg->bo) |
e024e110 DA |
397 | break; |
398 | ||
4c788679 | 399 | old_object = reg->bo; |
e024e110 DA |
400 | if (old_object->pin_count == 0) |
401 | steal = i; | |
402 | } | |
403 | ||
404 | /* if we are all out */ | |
405 | if (i == RADEON_GEM_MAX_SURFACES) { | |
406 | if (steal == -1) | |
407 | return -ENOMEM; | |
408 | /* find someone with a surface reg and nuke their BO */ | |
409 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 410 | old_object = reg->bo; |
e024e110 DA |
411 | /* blow away the mapping */ |
412 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 413 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
414 | old_object->surface_reg = -1; |
415 | i = steal; | |
416 | } | |
417 | ||
4c788679 JG |
418 | bo->surface_reg = i; |
419 | reg->bo = bo; | |
e024e110 DA |
420 | |
421 | out: | |
4c788679 JG |
422 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
423 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, | |
424 | bo->tbo.num_pages << PAGE_SHIFT); | |
e024e110 DA |
425 | return 0; |
426 | } | |
427 | ||
4c788679 | 428 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 429 | { |
4c788679 | 430 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
431 | struct radeon_surface_reg *reg; |
432 | ||
4c788679 | 433 | if (bo->surface_reg == -1) |
e024e110 DA |
434 | return; |
435 | ||
4c788679 JG |
436 | reg = &rdev->surface_regs[bo->surface_reg]; |
437 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 438 | |
4c788679 JG |
439 | reg->bo = NULL; |
440 | bo->surface_reg = -1; | |
e024e110 DA |
441 | } |
442 | ||
4c788679 JG |
443 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
444 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 445 | { |
4c788679 JG |
446 | int r; |
447 | ||
448 | r = radeon_bo_reserve(bo, false); | |
449 | if (unlikely(r != 0)) | |
450 | return r; | |
451 | bo->tiling_flags = tiling_flags; | |
452 | bo->pitch = pitch; | |
453 | radeon_bo_unreserve(bo); | |
454 | return 0; | |
e024e110 DA |
455 | } |
456 | ||
4c788679 JG |
457 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
458 | uint32_t *tiling_flags, | |
459 | uint32_t *pitch) | |
e024e110 | 460 | { |
4c788679 | 461 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
e024e110 | 462 | if (tiling_flags) |
4c788679 | 463 | *tiling_flags = bo->tiling_flags; |
e024e110 | 464 | if (pitch) |
4c788679 | 465 | *pitch = bo->pitch; |
e024e110 DA |
466 | } |
467 | ||
4c788679 JG |
468 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
469 | bool force_drop) | |
e024e110 | 470 | { |
4c788679 JG |
471 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
472 | ||
473 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
474 | return 0; |
475 | ||
476 | if (force_drop) { | |
4c788679 | 477 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
478 | return 0; |
479 | } | |
480 | ||
4c788679 | 481 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
482 | if (!has_moved) |
483 | return 0; | |
484 | ||
4c788679 JG |
485 | if (bo->surface_reg >= 0) |
486 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
487 | return 0; |
488 | } | |
489 | ||
4c788679 | 490 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
491 | return 0; |
492 | ||
4c788679 | 493 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
494 | } |
495 | ||
496 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
d03d8589 | 497 | struct ttm_mem_reg *mem) |
e024e110 | 498 | { |
d03d8589 JG |
499 | struct radeon_bo *rbo; |
500 | if (!radeon_ttm_bo_is_radeon_bo(bo)) | |
501 | return; | |
502 | rbo = container_of(bo, struct radeon_bo, tbo); | |
4c788679 | 503 | radeon_bo_check_tiling(rbo, 0, 1); |
e024e110 DA |
504 | } |
505 | ||
0a2d50e3 | 506 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 507 | { |
0a2d50e3 | 508 | struct radeon_device *rdev; |
d03d8589 | 509 | struct radeon_bo *rbo; |
0a2d50e3 JG |
510 | unsigned long offset, size; |
511 | int r; | |
512 | ||
d03d8589 | 513 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 514 | return 0; |
d03d8589 | 515 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 516 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 JG |
517 | rdev = rbo->rdev; |
518 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
519 | size = bo->mem.num_pages << PAGE_SHIFT; | |
520 | offset = bo->mem.mm_node->start << PAGE_SHIFT; | |
521 | if ((offset + size) > rdev->mc.visible_vram_size) { | |
522 | /* hurrah the memory is not visible ! */ | |
523 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
524 | rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
525 | r = ttm_bo_validate(bo, &rbo->placement, false, true, false); | |
526 | if (unlikely(r != 0)) | |
527 | return r; | |
528 | offset = bo->mem.mm_node->start << PAGE_SHIFT; | |
529 | /* this should not happen */ | |
530 | if ((offset + size) > rdev->mc.visible_vram_size) | |
531 | return -EINVAL; | |
532 | } | |
533 | } | |
534 | return 0; | |
e024e110 | 535 | } |