[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_trace.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

void radeon_bo_clear_va(struct radeon_bo *bo)
{
	struct radeon_bo_va *bo_va, *tmp;

	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
		/* remove from all vm address space */
		radeon_vm_bo_rmv(bo->rdev, bo_va);
	}
}

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	radeon_bo_clear_va(bo);
	drm_gem_object_release(&bo->gem_base);
	kfree(bo);
}

bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev,
		     unsigned long size, int byte_align, bool kernel, u32 domain,
		     struct sg_table *sg, struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	size_t acc_size;
	int r;

	size = ALIGN(size, PAGE_SIZE);

	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else if (sg) {
		type = ttm_bo_type_sg;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;

	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
				       sizeof(struct radeon_bo));

	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	if (unlikely(r)) {
		kfree(bo);
		return r;
	}
	bo->rdev = rdev;
	bo->gem_base.driver_private = NULL;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);
	INIT_LIST_HEAD(&bo->va);
	radeon_ttm_placement_from_domain(bo, domain);
	/* Kernel allocation are uninterruptible */
	down_read(&rdev->pm.mclk_lock);
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, page_align, 0, !kernel, NULL,
			acc_size, sg, &radeon_ttm_bo_destroy);
	up_read(&rdev->pm.mclk_lock);
	if (unlikely(r != 0)) {
		return r;
	}
	*bo_ptr = bo;

	trace_radeon_bo_create(bo);

	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;
	struct radeon_device *rdev;

	if ((*bo) == NULL)
		return;
	rdev = (*bo)->rdev;
	tbo = &((*bo)->tbo);
	down_read(&rdev->pm.mclk_lock);
	ttm_bo_unref(&tbo);
	up_read(&rdev->pm.mclk_lock);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
			     u64 *gpu_addr)
{
	int r, i;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);

		if (max_offset != 0) {
			u64 domain_start;

			if (domain == RADEON_GEM_DOMAIN_VRAM)
				domain_start = bo->rdev->mc.vram_start;
			else
				domain_start = bo->rdev->mc.gtt_start;
			WARN_ON_ONCE(max_offset <
				     (radeon_bo_gpu_offset(bo) - domain_start));
		}

		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
	if (max_offset) {
		u64 lpfn = max_offset >> PAGE_SHIFT;

		if (!bo->placement.lpfn)
			bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;

		if (lpfn < bo->placement.lpfn)
			bo->placement.lpfn = lpfn;
	}
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	return r;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
	return r;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
			*((unsigned long *)&bo->gem_base.refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		/* this should unref the ttm bo */
		drm_gem_object_unreference(&bo->gem_base);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->wdomain) {
		list_add(&lobj->tv.head, head);
	} else {
		list_add_tail(&lobj->tv.head, head);
	}
}

int radeon_bo_list_validate(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	u32 domain;
	int r;

	r = ttm_eu_reserve_buffers(head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, tv.head) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
			
		retry:
			radeon_ttm_placement_from_domain(bo, domain);
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
						true, false, false);
			if (unlikely(r)) {
				if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
					domain |= RADEON_GEM_DOMAIN_GTT;
					goto retry;
				}
				return r;
			}
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
	}
	return 0;
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	struct radeon_device *rdev = bo->rdev;
	int r;

	if (rdev->family >= CHIP_CEDAR) {
		unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;

		bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
		bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
		mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
		tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
		stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
		switch (bankw) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		switch (bankh) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		switch (mtaspect) {
		case 0:
		case 1:
		case 2:
		case 4:
		case 8:
			break;
		default:
			return -EINVAL;
		}
		if (tilesplit > 6) {
			return -EINVAL;
		}
		if (stilesplit > 6) {
			return -EINVAL;
		}
	}
	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
	radeon_vm_bo_invalidate(rbo->rdev, rbo);
}

int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_device *rdev;
	struct radeon_bo *rbo;
	unsigned long offset, size;
	int r;

	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return 0;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
	rdev = rbo->rdev;
	if (bo->mem.mem_type == TTM_PL_VRAM) {
		size = bo->mem.num_pages << PAGE_SHIFT;
		offset = bo->mem.start << PAGE_SHIFT;
		if ((offset + size) > rdev->mc.visible_vram_size) {
			/* hurrah the memory is not visible ! */
			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
			rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
			r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
			if (unlikely(r != 0))
				return r;
			offset = bo->mem.start << PAGE_SHIFT;
			/* this should not happen */
			if ((offset + size) > rdev->mc.visible_vram_size)
				return -EINVAL;
		}
	}
	return 0;
}

int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	if (unlikely(r != 0))
		return r;
	spin_lock(&bo->tbo.bdev->fence_lock);
	if (mem_type)
		*mem_type = bo->tbo.mem.mem_type;
	if (bo->tbo.sync_obj)
		r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
	spin_unlock(&bo->tbo.bdev->fence_lock);
	ttm_bo_unreserve(&bo->tbo);
	return r;
}


/**
 * radeon_bo_reserve - reserve bo
 * @bo:		bo structure
 * @no_intr:	don't return -ERESTARTSYS on pending signal
 *
 * Returns:
 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 * a signal. Release all buffer reservations and return to user-space.
 */
int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS)
			dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
		return r;
	}
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
5a0e3ad6	33	#include <linux/slab.h>
771fe6b9	34	#include <drm/drmP.h>
760285e7	35	#include <drm/radeon_drm.h>
771fe6b9	36	#include "radeon.h"
99ee7fac	37	#include "radeon_trace.h"
771fe6b9	38
771fe6b9 JG	39
	40	int radeon_ttm_init(struct radeon_device *rdev);
	41	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	42	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	43
	44	/*
	45	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	46	* function are calling it.
	47	*/
	48
721604a1 JG	49	void radeon_bo_clear_va(struct radeon_bo *bo)
	50	{
	51	struct radeon_bo_va bo_va, tmp;
	52
	53	list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
	54	/* remove from all vm address space */
e971bd5e	55	radeon_vm_bo_rmv(bo->rdev, bo_va);
721604a1 JG	56	}
	57	}
	58
4c788679	59	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	60	{
4c788679	61	struct radeon_bo *bo;
771fe6b9	62
4c788679 JG	63	bo = container_of(tbo, struct radeon_bo, tbo);
	64	mutex_lock(&bo->rdev->gem.mutex);
	65	list_del_init(&bo->list);
	66	mutex_unlock(&bo->rdev->gem.mutex);
	67	radeon_bo_clear_surface_reg(bo);
721604a1	68	radeon_bo_clear_va(bo);
441921d5	69	drm_gem_object_release(&bo->gem_base);
4c788679	70	kfree(bo);
771fe6b9 JG	71	}
771fe6b9 JG	72
d03d8589 JG	73	bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
	74	{
	75	if (bo->destroy == &radeon_ttm_bo_destroy)
	76	return true;
	77	return false;
	78	}
	79
312ea8da JG	80	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	81	{
	82	u32 c = 0;
	83
	84	rbo->placement.fpfn = 0;
93225b0d	85	rbo->placement.lpfn = 0;
312ea8da JG	86	rbo->placement.placement = rbo->placements;
	87	rbo->placement.busy_placement = rbo->placements;
	88	if (domain & RADEON_GEM_DOMAIN_VRAM)
	89	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	90	TTM_PL_FLAG_VRAM;
	91	if (domain & RADEON_GEM_DOMAIN_GTT)
	92	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_TT;
	93	if (domain & RADEON_GEM_DOMAIN_CPU)
	94	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
9fb03e63 JG	95	if (!c)
9fb03e63 JG	96	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
312ea8da JG	97	rbo->placement.num_placement = c;
	98	rbo->placement.num_busy_placement = c;
	99	}
	100
441921d5	101	int radeon_bo_create(struct radeon_device *rdev,
268b2510	102	unsigned long size, int byte_align, bool kernel, u32 domain,
40f5cf99	103	struct sg_table sg, struct radeon_bo *bo_ptr)
771fe6b9	104	{
4c788679	105	struct radeon_bo *bo;
771fe6b9	106	enum ttm_bo_type type;
93225b0d	107	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
57de4ba9	108	size_t acc_size;
771fe6b9 JG	109	int r;
771fe6b9 JG	110
441921d5 DV	111	size = ALIGN(size, PAGE_SIZE);
441921d5 DV	112
949c4a34	113	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
771fe6b9 JG	114	if (kernel) {
771fe6b9 JG	115	type = ttm_bo_type_kernel;
40f5cf99 AD	116	} else if (sg) {
40f5cf99 AD	117	type = ttm_bo_type_sg;
771fe6b9 JG	118	} else {
	119	type = ttm_bo_type_device;
	120	}
4c788679	121	*bo_ptr = NULL;
2b66b50b	122
57de4ba9 JG	123	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
	124	sizeof(struct radeon_bo));
	125
4c788679 JG	126	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
4c788679 JG	127	if (bo == NULL)
771fe6b9	128	return -ENOMEM;
441921d5 DV	129	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
	130	if (unlikely(r)) {
	131	kfree(bo);
	132	return r;
	133	}
4c788679	134	bo->rdev = rdev;
7e4d15d9	135	bo->gem_base.driver_private = NULL;
4c788679 JG	136	bo->surface_reg = -1;
4c788679 JG	137	INIT_LIST_HEAD(&bo->list);
721604a1	138	INIT_LIST_HEAD(&bo->va);
1fb107fc	139	radeon_ttm_placement_from_domain(bo, domain);
5cc6fbab	140	/* Kernel allocation are uninterruptible */
db7fce39	141	down_read(&rdev->pm.mclk_lock);
1fb107fc	142	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
57de4ba9	143	&bo->placement, page_align, 0, !kernel, NULL,
40f5cf99	144	acc_size, sg, &radeon_ttm_bo_destroy);
db7fce39	145	up_read(&rdev->pm.mclk_lock);
771fe6b9	146	if (unlikely(r != 0)) {
771fe6b9 JG	147	return r;
771fe6b9 JG	148	}
4c788679	149	*bo_ptr = bo;
441921d5	150
99ee7fac	151	trace_radeon_bo_create(bo);
441921d5	152
771fe6b9 JG	153	return 0;
	154	}
	155
4c788679	156	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	157	{
4c788679	158	bool is_iomem;
771fe6b9 JG	159	int r;
771fe6b9 JG	160
4c788679	161	if (bo->kptr) {
771fe6b9	162	if (ptr) {
4c788679	163	*ptr = bo->kptr;
771fe6b9	164	}
771fe6b9 JG	165	return 0;
771fe6b9 JG	166	}
4c788679	167	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	168	if (r) {
	169	return r;
	170	}
4c788679	171	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	172	if (ptr) {
4c788679	173	*ptr = bo->kptr;
771fe6b9	174	}
4c788679	175	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	176	return 0;
	177	}
	178
4c788679	179	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	180	{
4c788679	181	if (bo->kptr == NULL)
771fe6b9	182	return;
4c788679 JG	183	bo->kptr = NULL;
	184	radeon_bo_check_tiling(bo, 0, 0);
	185	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	186	}
771fe6b9 JG	187
4c788679	188	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	189	{
4c788679	190	struct ttm_buffer_object *tbo;
f4b7fb94	191	struct radeon_device *rdev;
771fe6b9	192
4c788679	193	if ((*bo) == NULL)
771fe6b9	194	return;
f4b7fb94	195	rdev = (*bo)->rdev;
4c788679	196	tbo = &((*bo)->tbo);
db7fce39	197	down_read(&rdev->pm.mclk_lock);
4c788679	198	ttm_bo_unref(&tbo);
db7fce39	199	up_read(&rdev->pm.mclk_lock);
4c788679 JG	200	if (tbo == NULL)
4c788679 JG	201	*bo = NULL;
771fe6b9 JG	202	}
771fe6b9 JG	203
c4353016 MD	204	int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
c4353016 MD	205	u64 *gpu_addr)
771fe6b9	206	{
312ea8da	207	int r, i;
771fe6b9	208
4c788679 JG	209	if (bo->pin_count) {
	210	bo->pin_count++;
	211	if (gpu_addr)
	212	*gpu_addr = radeon_bo_gpu_offset(bo);
d936622c MD	213
	214	if (max_offset != 0) {
	215	u64 domain_start;
	216
	217	if (domain == RADEON_GEM_DOMAIN_VRAM)
	218	domain_start = bo->rdev->mc.vram_start;
	219	else
	220	domain_start = bo->rdev->mc.gtt_start;
e199fd42 MD	221	WARN_ON_ONCE(max_offset <
e199fd42 MD	222	(radeon_bo_gpu_offset(bo) - domain_start));
d936622c MD	223	}
d936622c MD	224
771fe6b9 JG	225	return 0;
771fe6b9 JG	226	}
312ea8da	227	radeon_ttm_placement_from_domain(bo, domain);
3ca82da3 MD	228	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	229	/* force to pin into visible video ram */
	230	bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	231	}
c4353016 MD	232	if (max_offset) {
	233	u64 lpfn = max_offset >> PAGE_SHIFT;
	234
	235	if (!bo->placement.lpfn)
	236	bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
	237
	238	if (lpfn < bo->placement.lpfn)
	239	bo->placement.lpfn = lpfn;
	240	}
312ea8da JG	241	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	242	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
9d87fa21	243	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
4c788679 JG	244	if (likely(r == 0)) {
	245	bo->pin_count = 1;
	246	if (gpu_addr != NULL)
	247	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	248	}
5cc6fbab	249	if (unlikely(r != 0))
4c788679	250	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 JG	251	return r;
771fe6b9 JG	252	}
c4353016 MD	253
	254	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
	255	{
	256	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
	257	}
771fe6b9	258
4c788679	259	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	260	{
312ea8da	261	int r, i;
771fe6b9	262
4c788679 JG	263	if (!bo->pin_count) {
	264	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	265	return 0;
771fe6b9	266	}
4c788679 JG	267	bo->pin_count--;
	268	if (bo->pin_count)
	269	return 0;
312ea8da JG	270	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	271	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
9d87fa21	272	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
5cc6fbab	273	if (unlikely(r != 0))
4c788679	274	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
5cc6fbab	275	return r;
cefb87ef DA	276	}
cefb87ef DA	277
4c788679	278	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9	279	{
d796d844 DA	280	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
d796d844 DA	281	if (0 && (rdev->flags & RADEON_IS_IGP)) {
06b6476d AD	282	if (rdev->mc.igp_sideport_enabled == false)
	283	/* Useless to evict on IGP chips */
	284	return 0;
771fe6b9 JG	285	}
	286	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	287	}
	288
4c788679	289	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	290	{
4c788679	291	struct radeon_bo bo, n;
771fe6b9 JG	292
	293	if (list_empty(&rdev->gem.objects)) {
	294	return;
	295	}
4c788679 JG	296	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	297	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	298	mutex_lock(&rdev->ddev->struct_mutex);
4c788679	299	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
31c3603d DV	300	&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
31c3603d DV	301	((unsigned long )&bo->gem_base.refcount));
4c788679 JG	302	mutex_lock(&bo->rdev->gem.mutex);
	303	list_del_init(&bo->list);
	304	mutex_unlock(&bo->rdev->gem.mutex);
91132d6b	305	/* this should unref the ttm bo */
31c3603d	306	drm_gem_object_unreference(&bo->gem_base);
771fe6b9 JG	307	mutex_unlock(&rdev->ddev->struct_mutex);
	308	}
	309	}
	310
4c788679	311	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	312	{
a4d68279 JG	313	/* Add an MTRR for the VRAM */
	314	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
	315	MTRR_TYPE_WRCOMB, 1);
	316	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	317	rdev->mc.mc_vram_size >> 20,
	318	(unsigned long long)rdev->mc.aper_size >> 20);
	319	DRM_INFO("RAM width %dbits %cDR\n",
	320	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	321	return radeon_ttm_init(rdev);
	322	}
	323
4c788679	324	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	325	{
	326	radeon_ttm_fini(rdev);
	327	}
	328
4c788679 JG	329	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	330	struct list_head *head)
771fe6b9 JG	331	{
771fe6b9 JG	332	if (lobj->wdomain) {
147666fb	333	list_add(&lobj->tv.head, head);
771fe6b9	334	} else {
147666fb	335	list_add_tail(&lobj->tv.head, head);
771fe6b9 JG	336	}
	337	}
	338
6cb8e1f7	339	int radeon_bo_list_validate(struct list_head *head)
771fe6b9	340	{
4c788679 JG	341	struct radeon_bo_list *lobj;
4c788679 JG	342	struct radeon_bo *bo;
e376573f	343	u32 domain;
771fe6b9 JG	344	int r;
771fe6b9 JG	345
147666fb	346	r = ttm_eu_reserve_buffers(head);
771fe6b9	347	if (unlikely(r != 0)) {
771fe6b9 JG	348	return r;
771fe6b9 JG	349	}
147666fb	350	list_for_each_entry(lobj, head, tv.head) {
4c788679 JG	351	bo = lobj->bo;
4c788679 JG	352	if (!bo->pin_count) {
e376573f MD	353	domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
	354
	355	retry:
	356	radeon_ttm_placement_from_domain(bo, domain);
1fb107fc	357	r = ttm_bo_validate(&bo->tbo, &bo->placement,
9d87fa21	358	true, false, false);
e376573f MD	359	if (unlikely(r)) {
	360	if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
	361	domain \|= RADEON_GEM_DOMAIN_GTT;
	362	goto retry;
	363	}
771fe6b9	364	return r;
e376573f	365	}
771fe6b9	366	}
4c788679 JG	367	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	368	lobj->tiling_flags = bo->tiling_flags;
771fe6b9 JG	369	}
	370	return 0;
	371	}
	372
4c788679	373	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	374	struct vm_area_struct *vma)
771fe6b9 JG	375	{
4c788679	376	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	377	}
771fe6b9 JG	378
550e2d92	379	int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	380	{
4c788679	381	struct radeon_device *rdev = bo->rdev;
e024e110	382	struct radeon_surface_reg *reg;
4c788679	383	struct radeon_bo *old_object;
e024e110 DA	384	int steal;
	385	int i;
	386
4c788679 JG	387	BUG_ON(!atomic_read(&bo->tbo.reserved));
	388
	389	if (!bo->tiling_flags)
e024e110 DA	390	return 0;
e024e110 DA	391
4c788679 JG	392	if (bo->surface_reg >= 0) {
	393	reg = &rdev->surface_regs[bo->surface_reg];
	394	i = bo->surface_reg;
e024e110 DA	395	goto out;
	396	}
	397
	398	steal = -1;
	399	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	400
	401	reg = &rdev->surface_regs[i];
4c788679	402	if (!reg->bo)
e024e110 DA	403	break;
e024e110 DA	404
4c788679	405	old_object = reg->bo;
e024e110 DA	406	if (old_object->pin_count == 0)
	407	steal = i;
	408	}
	409
	410	/* if we are all out */
	411	if (i == RADEON_GEM_MAX_SURFACES) {
	412	if (steal == -1)
	413	return -ENOMEM;
	414	/* find someone with a surface reg and nuke their BO */
	415	reg = &rdev->surface_regs[steal];
4c788679	416	old_object = reg->bo;
e024e110 DA	417	/* blow away the mapping */
e024e110 DA	418	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	419	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	420	old_object->surface_reg = -1;
	421	i = steal;
	422	}
	423
4c788679 JG	424	bo->surface_reg = i;
4c788679 JG	425	reg->bo = bo;
e024e110 DA	426
e024e110 DA	427	out:
4c788679	428	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
d961db75	429	bo->tbo.mem.start << PAGE_SHIFT,
4c788679	430	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	431	return 0;
	432	}
	433
4c788679	434	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	435	{
4c788679	436	struct radeon_device *rdev = bo->rdev;
e024e110 DA	437	struct radeon_surface_reg *reg;
e024e110 DA	438
4c788679	439	if (bo->surface_reg == -1)
e024e110 DA	440	return;
e024e110 DA	441
4c788679 JG	442	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	443	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	444
4c788679 JG	445	reg->bo = NULL;
4c788679 JG	446	bo->surface_reg = -1;
e024e110 DA	447	}
e024e110 DA	448
4c788679 JG	449	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	450	uint32_t tiling_flags, uint32_t pitch)
e024e110	451	{
285484e2	452	struct radeon_device *rdev = bo->rdev;
4c788679 JG	453	int r;
4c788679 JG	454
285484e2 JG	455	if (rdev->family >= CHIP_CEDAR) {
	456	unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
	457
	458	bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
	459	bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
	460	mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
	461	tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
	462	stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
	463	switch (bankw) {
	464	case 0:
	465	case 1:
	466	case 2:
	467	case 4:
	468	case 8:
	469	break;
	470	default:
	471	return -EINVAL;
	472	}
	473	switch (bankh) {
	474	case 0:
	475	case 1:
	476	case 2:
	477	case 4:
	478	case 8:
	479	break;
	480	default:
	481	return -EINVAL;
	482	}
	483	switch (mtaspect) {
	484	case 0:
	485	case 1:
	486	case 2:
	487	case 4:
	488	case 8:
	489	break;
	490	default:
	491	return -EINVAL;
	492	}
	493	if (tilesplit > 6) {
	494	return -EINVAL;
	495	}
	496	if (stilesplit > 6) {
	497	return -EINVAL;
	498	}
	499	}
4c788679 JG	500	r = radeon_bo_reserve(bo, false);
	501	if (unlikely(r != 0))
	502	return r;
	503	bo->tiling_flags = tiling_flags;
	504	bo->pitch = pitch;
	505	radeon_bo_unreserve(bo);
	506	return 0;
e024e110 DA	507	}
e024e110 DA	508
4c788679 JG	509	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	510	uint32_t *tiling_flags,
	511	uint32_t *pitch)
e024e110	512	{
4c788679	513	BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110	514	if (tiling_flags)
4c788679	515	*tiling_flags = bo->tiling_flags;
e024e110	516	if (pitch)
4c788679	517	*pitch = bo->pitch;
e024e110 DA	518	}
e024e110 DA	519
4c788679 JG	520	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	521	bool force_drop)
e024e110	522	{
4c788679 JG	523	BUG_ON(!atomic_read(&bo->tbo.reserved));
	524
	525	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	526	return 0;
	527
	528	if (force_drop) {
4c788679	529	radeon_bo_clear_surface_reg(bo);
e024e110 DA	530	return 0;
	531	}
	532
4c788679	533	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	534	if (!has_moved)
	535	return 0;
	536
4c788679 JG	537	if (bo->surface_reg >= 0)
4c788679 JG	538	radeon_bo_clear_surface_reg(bo);
e024e110 DA	539	return 0;
	540	}
	541
4c788679	542	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	543	return 0;
e024e110 DA	544
4c788679	545	return radeon_bo_get_surface_reg(bo);
e024e110 DA	546	}
	547
	548	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
d03d8589	549	struct ttm_mem_reg *mem)
e024e110	550	{
d03d8589 JG	551	struct radeon_bo *rbo;
	552	if (!radeon_ttm_bo_is_radeon_bo(bo))
	553	return;
	554	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	555	radeon_bo_check_tiling(rbo, 0, 1);
721604a1	556	radeon_vm_bo_invalidate(rbo->rdev, rbo);
e024e110 DA	557	}
e024e110 DA	558
0a2d50e3	559	int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
e024e110	560	{
0a2d50e3	561	struct radeon_device *rdev;
d03d8589	562	struct radeon_bo *rbo;
0a2d50e3 JG	563	unsigned long offset, size;
	564	int r;
	565
d03d8589	566	if (!radeon_ttm_bo_is_radeon_bo(bo))
0a2d50e3	567	return 0;
d03d8589	568	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	569	radeon_bo_check_tiling(rbo, 0, 0);
0a2d50e3 JG	570	rdev = rbo->rdev;
	571	if (bo->mem.mem_type == TTM_PL_VRAM) {
	572	size = bo->mem.num_pages << PAGE_SHIFT;
d961db75	573	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	574	if ((offset + size) > rdev->mc.visible_vram_size) {
	575	/* hurrah the memory is not visible ! */
	576	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
	577	rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
	578	r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
	579	if (unlikely(r != 0))
	580	return r;
d961db75	581	offset = bo->mem.start << PAGE_SHIFT;
0a2d50e3 JG	582	/* this should not happen */
	583	if ((offset + size) > rdev->mc.visible_vram_size)
	584	return -EINVAL;
	585	}
	586	}
	587	return 0;
e024e110	588	}
ce580fab	589
83f30d0e	590	int radeon_bo_wait(struct radeon_bo bo, u32 mem_type, bool no_wait)
ce580fab AK	591	{
	592	int r;
	593
	594	r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
	595	if (unlikely(r != 0))
	596	return r;
	597	spin_lock(&bo->tbo.bdev->fence_lock);
	598	if (mem_type)
	599	*mem_type = bo->tbo.mem.mem_type;
	600	if (bo->tbo.sync_obj)
1717c0e2	601	r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
ce580fab AK	602	spin_unlock(&bo->tbo.bdev->fence_lock);
	603	ttm_bo_unreserve(&bo->tbo);
	604	return r;
	605	}
	606
	607
	608	/**
	609	* radeon_bo_reserve - reserve bo
	610	* @bo: bo structure
d63dfed5	611	* @no_intr: don't return -ERESTARTSYS on pending signal
ce580fab AK	612	*
ce580fab AK	613	* Returns:
ce580fab AK	614	* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
	615	* a signal. Release all buffer reservations and return to user-space.
	616	*/
d63dfed5	617	int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
ce580fab AK	618	{
	619	int r;
	620
d63dfed5	621	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
ce580fab AK	622	if (unlikely(r != 0)) {
	623	if (r != -ERESTARTSYS)
	624	dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
	625	return r;
	626	}
	627	return 0;
	628	}