[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <drm/drmP.h>
#include "radeon_drm.h"
#include "radeon.h"


int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);

/*
 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
 * function are calling it.
 */

static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct radeon_bo *bo;

	bo = container_of(tbo, struct radeon_bo, tbo);
	mutex_lock(&bo->rdev->gem.mutex);
	list_del_init(&bo->list);
	mutex_unlock(&bo->rdev->gem.mutex);
	radeon_bo_clear_surface_reg(bo);
	kfree(bo);
}

bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &radeon_ttm_bo_destroy)
		return true;
	return false;
}

void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
{
	u32 c = 0;

	rbo->placement.fpfn = 0;
	rbo->placement.lpfn = 0;
	rbo->placement.placement = rbo->placements;
	rbo->placement.busy_placement = rbo->placements;
	if (domain & RADEON_GEM_DOMAIN_VRAM)
		rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
					TTM_PL_FLAG_VRAM;
	if (domain & RADEON_GEM_DOMAIN_GTT)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
	if (domain & RADEON_GEM_DOMAIN_CPU)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	if (!c)
		rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
	rbo->placement.num_placement = c;
	rbo->placement.num_busy_placement = c;
}

int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
			unsigned long size, bool kernel, u32 domain,
			struct radeon_bo **bo_ptr)
{
	struct radeon_bo *bo;
	enum ttm_bo_type type;
	int r;

	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	}
	if (kernel) {
		type = ttm_bo_type_kernel;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;
	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	bo->rdev = rdev;
	bo->gobj = gobj;
	bo->surface_reg = -1;
	INIT_LIST_HEAD(&bo->list);

	radeon_ttm_placement_from_domain(bo, domain);
	/* Kernel allocation are uninterruptible */
	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, 0, 0, !kernel, NULL, size,
			&radeon_ttm_bo_destroy);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS)
			dev_err(rdev->dev,
				"object_init failed for (%lu, 0x%08X)\n",
				size, domain);
		return r;
	}
	*bo_ptr = bo;
	if (gobj) {
		mutex_lock(&bo->rdev->gem.mutex);
		list_add_tail(&bo->list, &rdev->gem.objects);
		mutex_unlock(&bo->rdev->gem.mutex);
	}
	return 0;
}

int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
{
	bool is_iomem;
	int r;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r) {
		return r;
	}
	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr) {
		*ptr = bo->kptr;
	}
	radeon_bo_check_tiling(bo, 0, 0);
	return 0;
}

void radeon_bo_kunmap(struct radeon_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	radeon_bo_check_tiling(bo, 0, 0);
	ttm_bo_kunmap(&bo->kmap);
}

void radeon_bo_unref(struct radeon_bo **bo)
{
	struct ttm_buffer_object *tbo;

	if ((*bo) == NULL)
		return;
	tbo = &((*bo)->tbo);
	ttm_bo_unref(&tbo);
	if (tbo == NULL)
		*bo = NULL;
}

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
{
	int r, i;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = radeon_bo_gpu_offset(bo);
		return 0;
	}
	radeon_ttm_placement_from_domain(bo, domain);
	if (domain == RADEON_GEM_DOMAIN_VRAM) {
		/* force to pin into visible video ram */
		bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	}
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = radeon_bo_gpu_offset(bo);
	}
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
	return r;
}

int radeon_bo_unpin(struct radeon_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++)
		bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
	if (unlikely(r != 0))
		dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
	return r;
}

int radeon_bo_evict_vram(struct radeon_device *rdev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (rdev->flags & RADEON_IS_IGP)) {
		if (rdev->mc.igp_sideport_enabled == false)
			/* Useless to evict on IGP chips */
			return 0;
	}
	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

void radeon_bo_force_delete(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;
	struct drm_gem_object *gobj;

	if (list_empty(&rdev->gem.objects)) {
		return;
	}
	dev_err(rdev->dev, "Userspace still has active objects !\n");
	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		mutex_lock(&rdev->ddev->struct_mutex);
		gobj = bo->gobj;
		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
			gobj, bo, (unsigned long)gobj->size,
			*((unsigned long *)&gobj->refcount));
		mutex_lock(&bo->rdev->gem.mutex);
		list_del_init(&bo->list);
		mutex_unlock(&bo->rdev->gem.mutex);
		radeon_bo_unref(&bo);
		gobj->driver_private = NULL;
		drm_gem_object_unreference(gobj);
		mutex_unlock(&rdev->ddev->struct_mutex);
	}
}

int radeon_bo_init(struct radeon_device *rdev)
{
	/* Add an MTRR for the VRAM */
	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
			MTRR_TYPE_WRCOMB, 1);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		rdev->mc.mc_vram_size >> 20,
		(unsigned long long)rdev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %cDR\n",
			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
	return radeon_ttm_init(rdev);
}

void radeon_bo_fini(struct radeon_device *rdev)
{
	radeon_ttm_fini(rdev);
}

void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
				struct list_head *head)
{
	if (lobj->wdomain) {
		list_add(&lobj->list, head);
	} else {
		list_add_tail(&lobj->list, head);
	}
}

int radeon_bo_list_reserve(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	int r;

	list_for_each_entry(lobj, head, list){
		r = radeon_bo_reserve(lobj->bo, false);
		if (unlikely(r != 0))
			return r;
	}
	return 0;
}

void radeon_bo_list_unreserve(struct list_head *head)
{
	struct radeon_bo_list *lobj;

	list_for_each_entry(lobj, head, list) {
		/* only unreserve object we successfully reserved */
		if (radeon_bo_is_reserved(lobj->bo))
			radeon_bo_unreserve(lobj->bo);
	}
}

int radeon_bo_list_validate(struct list_head *head)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	r = radeon_bo_list_reserve(head);
	if (unlikely(r != 0)) {
		return r;
	}
	list_for_each_entry(lobj, head, list) {
		bo = lobj->bo;
		if (!bo->pin_count) {
			if (lobj->wdomain) {
				radeon_ttm_placement_from_domain(bo,
								lobj->wdomain);
			} else {
				radeon_ttm_placement_from_domain(bo,
								lobj->rdomain);
			}
			r = ttm_bo_validate(&bo->tbo, &bo->placement,
						true, false, false);
			if (unlikely(r))
				return r;
		}
		lobj->gpu_offset = radeon_bo_gpu_offset(bo);
		lobj->tiling_flags = bo->tiling_flags;
	}
	return 0;
}

void radeon_bo_list_fence(struct list_head *head, void *fence)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	struct radeon_fence *old_fence = NULL;

	list_for_each_entry(lobj, head, list) {
		bo = lobj->bo;
		spin_lock(&bo->tbo.lock);
		old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
		bo->tbo.sync_obj = radeon_fence_ref(fence);
		bo->tbo.sync_obj_arg = NULL;
		spin_unlock(&bo->tbo.lock);
		if (old_fence) {
			radeon_fence_unref(&old_fence);
		}
	}
}

int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int radeon_bo_get_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;
	struct radeon_bo *old_object;
	int steal;
	int i;

	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!bo->tiling_flags)
		return 0;

	if (bo->surface_reg >= 0) {
		reg = &rdev->surface_regs[bo->surface_reg];
		i = bo->surface_reg;
		goto out;
	}

	steal = -1;
	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

		reg = &rdev->surface_regs[i];
		if (!reg->bo)
			break;

		old_object = reg->bo;
		if (old_object->pin_count == 0)
			steal = i;
	}

	/* if we are all out */
	if (i == RADEON_GEM_MAX_SURFACES) {
		if (steal == -1)
			return -ENOMEM;
		/* find someone with a surface reg and nuke their BO */
		reg = &rdev->surface_regs[steal];
		old_object = reg->bo;
		/* blow away the mapping */
		DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
		ttm_bo_unmap_virtual(&old_object->tbo);
		old_object->surface_reg = -1;
		i = steal;
	}

	bo->surface_reg = i;
	reg->bo = bo;

out:
	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
			       bo->tbo.mem.mm_node->start << PAGE_SHIFT,
			       bo->tbo.num_pages << PAGE_SHIFT);
	return 0;
}

static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
{
	struct radeon_device *rdev = bo->rdev;
	struct radeon_surface_reg *reg;

	if (bo->surface_reg == -1)
		return;

	reg = &rdev->surface_regs[bo->surface_reg];
	radeon_clear_surface_reg(rdev, bo->surface_reg);

	reg->bo = NULL;
	bo->surface_reg = -1;
}

int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
				uint32_t tiling_flags, uint32_t pitch)
{
	int r;

	r = radeon_bo_reserve(bo, false);
	if (unlikely(r != 0))
		return r;
	bo->tiling_flags = tiling_flags;
	bo->pitch = pitch;
	radeon_bo_unreserve(bo);
	return 0;
}

void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
				uint32_t *tiling_flags,
				uint32_t *pitch)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));
	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
	if (pitch)
		*pitch = bo->pitch;
}

int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
				bool force_drop)
{
	BUG_ON(!atomic_read(&bo->tbo.reserved));

	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
		return 0;

	if (force_drop) {
		radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
		if (!has_moved)
			return 0;

		if (bo->surface_reg >= 0)
			radeon_bo_clear_surface_reg(bo);
		return 0;
	}

	if ((bo->surface_reg >= 0) && !has_moved)
		return 0;

	return radeon_bo_get_surface_reg(bo);
}

void radeon_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *mem)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 1);
}

void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct radeon_bo *rbo;
	if (!radeon_ttm_bo_is_radeon_bo(bo))
		return;
	rbo = container_of(bo, struct radeon_bo, tbo);
	radeon_bo_check_tiling(rbo, 0, 0);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
	33	#include <drm/drmP.h>
	34	#include "radeon_drm.h"
	35	#include "radeon.h"
	36
771fe6b9 JG	37
	38	int radeon_ttm_init(struct radeon_device *rdev);
	39	void radeon_ttm_fini(struct radeon_device *rdev);
4c788679	40	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9 JG	41
	42	/*
	43	* To exclude mutual BO access we rely on bo_reserve exclusion, as all
	44	* function are calling it.
	45	*/
	46
4c788679	47	static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9	48	{
4c788679	49	struct radeon_bo *bo;
771fe6b9	50
4c788679 JG	51	bo = container_of(tbo, struct radeon_bo, tbo);
	52	mutex_lock(&bo->rdev->gem.mutex);
	53	list_del_init(&bo->list);
	54	mutex_unlock(&bo->rdev->gem.mutex);
	55	radeon_bo_clear_surface_reg(bo);
	56	kfree(bo);
771fe6b9 JG	57	}
771fe6b9 JG	58
d03d8589 JG	59	bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
	60	{
	61	if (bo->destroy == &radeon_ttm_bo_destroy)
	62	return true;
	63	return false;
	64	}
	65
312ea8da JG	66	void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
	67	{
	68	u32 c = 0;
	69
	70	rbo->placement.fpfn = 0;
	71	rbo->placement.lpfn = 0;
	72	rbo->placement.placement = rbo->placements;
	73	rbo->placement.busy_placement = rbo->placements;
	74	if (domain & RADEON_GEM_DOMAIN_VRAM)
	75	rbo->placements[c++] = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	76	TTM_PL_FLAG_VRAM;
	77	if (domain & RADEON_GEM_DOMAIN_GTT)
	78	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_TT;
	79	if (domain & RADEON_GEM_DOMAIN_CPU)
	80	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
9fb03e63 JG	81	if (!c)
9fb03e63 JG	82	rbo->placements[c++] = TTM_PL_MASK_CACHING \| TTM_PL_FLAG_SYSTEM;
312ea8da JG	83	rbo->placement.num_placement = c;
	84	rbo->placement.num_busy_placement = c;
	85	}
	86
4c788679 JG	87	int radeon_bo_create(struct radeon_device rdev, struct drm_gem_object gobj,
	88	unsigned long size, bool kernel, u32 domain,
	89	struct radeon_bo **bo_ptr)
771fe6b9	90	{
4c788679	91	struct radeon_bo *bo;
771fe6b9	92	enum ttm_bo_type type;
771fe6b9 JG	93	int r;
	94
	95	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
	96	rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
	97	}
	98	if (kernel) {
	99	type = ttm_bo_type_kernel;
	100	} else {
	101	type = ttm_bo_type_device;
	102	}
4c788679 JG	103	*bo_ptr = NULL;
	104	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
	105	if (bo == NULL)
771fe6b9	106	return -ENOMEM;
4c788679 JG	107	bo->rdev = rdev;
	108	bo->gobj = gobj;
	109	bo->surface_reg = -1;
	110	INIT_LIST_HEAD(&bo->list);
	111
1fb107fc	112	radeon_ttm_placement_from_domain(bo, domain);
5cc6fbab	113	/* Kernel allocation are uninterruptible */
1fb107fc JG	114	r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
	115	&bo->placement, 0, 0, !kernel, NULL, size,
	116	&radeon_ttm_bo_destroy);
771fe6b9	117	if (unlikely(r != 0)) {
5cc6fbab TH	118	if (r != -ERESTARTSYS)
5cc6fbab TH	119	dev_err(rdev->dev,
1fb107fc JG	120	"object_init failed for (%lu, 0x%08X)\n",
1fb107fc JG	121	size, domain);
771fe6b9 JG	122	return r;
771fe6b9 JG	123	}
4c788679	124	*bo_ptr = bo;
771fe6b9	125	if (gobj) {
4c788679 JG	126	mutex_lock(&bo->rdev->gem.mutex);
	127	list_add_tail(&bo->list, &rdev->gem.objects);
	128	mutex_unlock(&bo->rdev->gem.mutex);
771fe6b9 JG	129	}
	130	return 0;
	131	}
	132
4c788679	133	int radeon_bo_kmap(struct radeon_bo bo, void *ptr)
771fe6b9	134	{
4c788679	135	bool is_iomem;
771fe6b9 JG	136	int r;
771fe6b9 JG	137
4c788679	138	if (bo->kptr) {
771fe6b9	139	if (ptr) {
4c788679	140	*ptr = bo->kptr;
771fe6b9	141	}
771fe6b9 JG	142	return 0;
771fe6b9 JG	143	}
4c788679	144	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9 JG	145	if (r) {
	146	return r;
	147	}
4c788679	148	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9	149	if (ptr) {
4c788679	150	*ptr = bo->kptr;
771fe6b9	151	}
4c788679	152	radeon_bo_check_tiling(bo, 0, 0);
771fe6b9 JG	153	return 0;
	154	}
	155
4c788679	156	void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9	157	{
4c788679	158	if (bo->kptr == NULL)
771fe6b9	159	return;
4c788679 JG	160	bo->kptr = NULL;
	161	radeon_bo_check_tiling(bo, 0, 0);
	162	ttm_bo_kunmap(&bo->kmap);
771fe6b9 JG	163	}
771fe6b9 JG	164
4c788679	165	void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9	166	{
4c788679	167	struct ttm_buffer_object *tbo;
771fe6b9	168
4c788679	169	if ((*bo) == NULL)
771fe6b9	170	return;
4c788679 JG	171	tbo = &((*bo)->tbo);
	172	ttm_bo_unref(&tbo);
	173	if (tbo == NULL)
	174	*bo = NULL;
771fe6b9 JG	175	}
771fe6b9 JG	176
4c788679	177	int radeon_bo_pin(struct radeon_bo bo, u32 domain, u64 gpu_addr)
771fe6b9	178	{
312ea8da	179	int r, i;
771fe6b9	180
4c788679 JG	181	if (bo->pin_count) {
	182	bo->pin_count++;
	183	if (gpu_addr)
	184	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9 JG	185	return 0;
771fe6b9 JG	186	}
312ea8da	187	radeon_ttm_placement_from_domain(bo, domain);
3ca82da3 MD	188	if (domain == RADEON_GEM_DOMAIN_VRAM) {
	189	/* force to pin into visible video ram */
	190	bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
	191	}
312ea8da JG	192	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	193	bo->placements[i] \|= TTM_PL_FLAG_NO_EVICT;
9d87fa21	194	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
4c788679 JG	195	if (likely(r == 0)) {
	196	bo->pin_count = 1;
	197	if (gpu_addr != NULL)
	198	*gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9	199	}
5cc6fbab	200	if (unlikely(r != 0))
4c788679	201	dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 JG	202	return r;
	203	}
	204
4c788679	205	int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9	206	{
312ea8da	207	int r, i;
771fe6b9	208
4c788679 JG	209	if (!bo->pin_count) {
	210	dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
	211	return 0;
771fe6b9	212	}
4c788679 JG	213	bo->pin_count--;
	214	if (bo->pin_count)
	215	return 0;
312ea8da JG	216	for (i = 0; i < bo->placement.num_placement; i++)
312ea8da JG	217	bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
9d87fa21	218	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
5cc6fbab	219	if (unlikely(r != 0))
4c788679	220	dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
5cc6fbab	221	return r;
cefb87ef DA	222	}
cefb87ef DA	223
4c788679	224	int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9	225	{
d796d844 DA	226	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
d796d844 DA	227	if (0 && (rdev->flags & RADEON_IS_IGP)) {
06b6476d AD	228	if (rdev->mc.igp_sideport_enabled == false)
	229	/* Useless to evict on IGP chips */
	230	return 0;
771fe6b9 JG	231	}
	232	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
	233	}
	234
4c788679	235	void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9	236	{
4c788679	237	struct radeon_bo bo, n;
771fe6b9 JG	238	struct drm_gem_object *gobj;
	239
	240	if (list_empty(&rdev->gem.objects)) {
	241	return;
	242	}
4c788679 JG	243	dev_err(rdev->dev, "Userspace still has active objects !\n");
4c788679 JG	244	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9	245	mutex_lock(&rdev->ddev->struct_mutex);
4c788679 JG	246	gobj = bo->gobj;
	247	dev_err(rdev->dev, "%p %p %lu %lu force free\n",
	248	gobj, bo, (unsigned long)gobj->size,
	249	((unsigned long )&gobj->refcount));
	250	mutex_lock(&bo->rdev->gem.mutex);
	251	list_del_init(&bo->list);
	252	mutex_unlock(&bo->rdev->gem.mutex);
	253	radeon_bo_unref(&bo);
771fe6b9 JG	254	gobj->driver_private = NULL;
	255	drm_gem_object_unreference(gobj);
	256	mutex_unlock(&rdev->ddev->struct_mutex);
	257	}
	258	}
	259
4c788679	260	int radeon_bo_init(struct radeon_device *rdev)
771fe6b9	261	{
a4d68279 JG	262	/* Add an MTRR for the VRAM */
	263	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
	264	MTRR_TYPE_WRCOMB, 1);
	265	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	266	rdev->mc.mc_vram_size >> 20,
	267	(unsigned long long)rdev->mc.aper_size >> 20);
	268	DRM_INFO("RAM width %dbits %cDR\n",
	269	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9 JG	270	return radeon_ttm_init(rdev);
	271	}
	272
4c788679	273	void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9 JG	274	{
	275	radeon_ttm_fini(rdev);
	276	}
	277
4c788679 JG	278	void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
4c788679 JG	279	struct list_head *head)
771fe6b9 JG	280	{
	281	if (lobj->wdomain) {
	282	list_add(&lobj->list, head);
	283	} else {
	284	list_add_tail(&lobj->list, head);
	285	}
	286	}
	287
4c788679	288	int radeon_bo_list_reserve(struct list_head *head)
771fe6b9	289	{
4c788679	290	struct radeon_bo_list *lobj;
771fe6b9 JG	291	int r;
771fe6b9 JG	292
9d8401fc	293	list_for_each_entry(lobj, head, list){
4c788679 JG	294	r = radeon_bo_reserve(lobj->bo, false);
	295	if (unlikely(r != 0))
	296	return r;
771fe6b9 JG	297	}
	298	return 0;
	299	}
	300
4c788679	301	void radeon_bo_list_unreserve(struct list_head *head)
771fe6b9	302	{
4c788679	303	struct radeon_bo_list *lobj;
771fe6b9	304
9d8401fc	305	list_for_each_entry(lobj, head, list) {
4c788679 JG	306	/* only unreserve object we successfully reserved */
	307	if (radeon_bo_is_reserved(lobj->bo))
	308	radeon_bo_unreserve(lobj->bo);
771fe6b9 JG	309	}
	310	}
	311
6cb8e1f7	312	int radeon_bo_list_validate(struct list_head *head)
771fe6b9	313	{
4c788679 JG	314	struct radeon_bo_list *lobj;
4c788679 JG	315	struct radeon_bo *bo;
771fe6b9 JG	316	int r;
771fe6b9 JG	317
4c788679	318	r = radeon_bo_list_reserve(head);
771fe6b9	319	if (unlikely(r != 0)) {
771fe6b9 JG	320	return r;
771fe6b9 JG	321	}
9d8401fc	322	list_for_each_entry(lobj, head, list) {
4c788679 JG	323	bo = lobj->bo;
4c788679 JG	324	if (!bo->pin_count) {
664f8659	325	if (lobj->wdomain) {
312ea8da JG	326	radeon_ttm_placement_from_domain(bo,
312ea8da JG	327	lobj->wdomain);
664f8659	328	} else {
312ea8da JG	329	radeon_ttm_placement_from_domain(bo,
312ea8da JG	330	lobj->rdomain);
664f8659	331	}
1fb107fc	332	r = ttm_bo_validate(&bo->tbo, &bo->placement,
9d87fa21	333	true, false, false);
5cc6fbab	334	if (unlikely(r))
771fe6b9	335	return r;
771fe6b9	336	}
4c788679 JG	337	lobj->gpu_offset = radeon_bo_gpu_offset(bo);
4c788679 JG	338	lobj->tiling_flags = bo->tiling_flags;
771fe6b9 JG	339	}
	340	return 0;
	341	}
	342
6cb8e1f7	343	void radeon_bo_list_fence(struct list_head head, void fence)
771fe6b9	344	{
4c788679	345	struct radeon_bo_list *lobj;
6cb8e1f7 JG	346	struct radeon_bo *bo;
	347	struct radeon_fence *old_fence = NULL;
	348
	349	list_for_each_entry(lobj, head, list) {
	350	bo = lobj->bo;
	351	spin_lock(&bo->tbo.lock);
	352	old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
	353	bo->tbo.sync_obj = radeon_fence_ref(fence);
	354	bo->tbo.sync_obj_arg = NULL;
	355	spin_unlock(&bo->tbo.lock);
	356	if (old_fence) {
	357	radeon_fence_unref(&old_fence);
771fe6b9	358	}
6cb8e1f7	359	}
771fe6b9 JG	360	}
771fe6b9 JG	361
4c788679	362	int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9 JG	363	struct vm_area_struct *vma)
771fe6b9 JG	364	{
4c788679	365	return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9 JG	366	}
771fe6b9 JG	367
550e2d92	368	int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9	369	{
4c788679	370	struct radeon_device *rdev = bo->rdev;
e024e110	371	struct radeon_surface_reg *reg;
4c788679	372	struct radeon_bo *old_object;
e024e110 DA	373	int steal;
	374	int i;
	375
4c788679 JG	376	BUG_ON(!atomic_read(&bo->tbo.reserved));
	377
	378	if (!bo->tiling_flags)
e024e110 DA	379	return 0;
e024e110 DA	380
4c788679 JG	381	if (bo->surface_reg >= 0) {
	382	reg = &rdev->surface_regs[bo->surface_reg];
	383	i = bo->surface_reg;
e024e110 DA	384	goto out;
	385	}
	386
	387	steal = -1;
	388	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
	389
	390	reg = &rdev->surface_regs[i];
4c788679	391	if (!reg->bo)
e024e110 DA	392	break;
e024e110 DA	393
4c788679	394	old_object = reg->bo;
e024e110 DA	395	if (old_object->pin_count == 0)
	396	steal = i;
	397	}
	398
	399	/* if we are all out */
	400	if (i == RADEON_GEM_MAX_SURFACES) {
	401	if (steal == -1)
	402	return -ENOMEM;
	403	/* find someone with a surface reg and nuke their BO */
	404	reg = &rdev->surface_regs[steal];
4c788679	405	old_object = reg->bo;
e024e110 DA	406	/* blow away the mapping */
e024e110 DA	407	DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679	408	ttm_bo_unmap_virtual(&old_object->tbo);
e024e110 DA	409	old_object->surface_reg = -1;
	410	i = steal;
	411	}
	412
4c788679 JG	413	bo->surface_reg = i;
4c788679 JG	414	reg->bo = bo;
e024e110 DA	415
e024e110 DA	416	out:
4c788679 JG	417	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
	418	bo->tbo.mem.mm_node->start << PAGE_SHIFT,
	419	bo->tbo.num_pages << PAGE_SHIFT);
e024e110 DA	420	return 0;
	421	}
	422
4c788679	423	static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110	424	{
4c788679	425	struct radeon_device *rdev = bo->rdev;
e024e110 DA	426	struct radeon_surface_reg *reg;
e024e110 DA	427
4c788679	428	if (bo->surface_reg == -1)
e024e110 DA	429	return;
e024e110 DA	430
4c788679 JG	431	reg = &rdev->surface_regs[bo->surface_reg];
4c788679 JG	432	radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110	433
4c788679 JG	434	reg->bo = NULL;
4c788679 JG	435	bo->surface_reg = -1;
e024e110 DA	436	}
e024e110 DA	437
4c788679 JG	438	int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
4c788679 JG	439	uint32_t tiling_flags, uint32_t pitch)
e024e110	440	{
4c788679 JG	441	int r;
	442
	443	r = radeon_bo_reserve(bo, false);
	444	if (unlikely(r != 0))
	445	return r;
	446	bo->tiling_flags = tiling_flags;
	447	bo->pitch = pitch;
	448	radeon_bo_unreserve(bo);
	449	return 0;
e024e110 DA	450	}
e024e110 DA	451
4c788679 JG	452	void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
	453	uint32_t *tiling_flags,
	454	uint32_t *pitch)
e024e110	455	{
4c788679	456	BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110	457	if (tiling_flags)
4c788679	458	*tiling_flags = bo->tiling_flags;
e024e110	459	if (pitch)
4c788679	460	*pitch = bo->pitch;
e024e110 DA	461	}
e024e110 DA	462
4c788679 JG	463	int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
4c788679 JG	464	bool force_drop)
e024e110	465	{
4c788679 JG	466	BUG_ON(!atomic_read(&bo->tbo.reserved));
	467
	468	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110 DA	469	return 0;
	470
	471	if (force_drop) {
4c788679	472	radeon_bo_clear_surface_reg(bo);
e024e110 DA	473	return 0;
	474	}
	475
4c788679	476	if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110 DA	477	if (!has_moved)
	478	return 0;
	479
4c788679 JG	480	if (bo->surface_reg >= 0)
4c788679 JG	481	radeon_bo_clear_surface_reg(bo);
e024e110 DA	482	return 0;
	483	}
	484
4c788679	485	if ((bo->surface_reg >= 0) && !has_moved)
e024e110 DA	486	return 0;
e024e110 DA	487
4c788679	488	return radeon_bo_get_surface_reg(bo);
e024e110 DA	489	}
	490
	491	void radeon_bo_move_notify(struct ttm_buffer_object *bo,
d03d8589	492	struct ttm_mem_reg *mem)
e024e110	493	{
d03d8589 JG	494	struct radeon_bo *rbo;
	495	if (!radeon_ttm_bo_is_radeon_bo(bo))
	496	return;
	497	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	498	radeon_bo_check_tiling(rbo, 0, 1);
e024e110 DA	499	}
	500
	501	void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
	502	{
d03d8589 JG	503	struct radeon_bo *rbo;
	504	if (!radeon_ttm_bo_is_radeon_bo(bo))
	505	return;
	506	rbo = container_of(bo, struct radeon_bo, tbo);
4c788679	507	radeon_bo_check_tiling(rbo, 0, 0);
e024e110	508	}