drm/ttm: Rework validation & memory space allocation (V3)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_object.c
CommitLineData
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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <drm/drmP.h>
34#include "radeon_drm.h"
35#include "radeon.h"
36
771fe6b9
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37
38int radeon_ttm_init(struct radeon_device *rdev);
39void radeon_ttm_fini(struct radeon_device *rdev);
4c788679 40static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
771fe6b9
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41
42/*
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
45 */
46
4c788679 47static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
771fe6b9 48{
4c788679 49 struct radeon_bo *bo;
771fe6b9 50
4c788679
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51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
56 kfree(bo);
771fe6b9
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57}
58
4c788679 59static inline u32 radeon_ttm_flags_from_domain(u32 domain)
771fe6b9 60{
4c788679 61 u32 flags = 0;
771fe6b9 62
771fe6b9 63 if (domain & RADEON_GEM_DOMAIN_VRAM) {
664f8659 64 flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
771fe6b9
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65 }
66 if (domain & RADEON_GEM_DOMAIN_GTT) {
985fe845 67 flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
771fe6b9
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68 }
69 if (domain & RADEON_GEM_DOMAIN_CPU) {
664f8659 70 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
771fe6b9
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71 }
72 if (!flags) {
664f8659 73 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
771fe6b9
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74 }
75 return flags;
76}
77
4c788679
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78int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
79 unsigned long size, bool kernel, u32 domain,
80 struct radeon_bo **bo_ptr)
771fe6b9 81{
4c788679 82 struct radeon_bo *bo;
771fe6b9 83 enum ttm_bo_type type;
4c788679 84 u32 flags;
771fe6b9
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85 int r;
86
87 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
88 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
89 }
90 if (kernel) {
91 type = ttm_bo_type_kernel;
92 } else {
93 type = ttm_bo_type_device;
94 }
4c788679
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95 *bo_ptr = NULL;
96 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
97 if (bo == NULL)
771fe6b9 98 return -ENOMEM;
4c788679
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99 bo->rdev = rdev;
100 bo->gobj = gobj;
101 bo->surface_reg = -1;
102 INIT_LIST_HEAD(&bo->list);
103
104 flags = radeon_ttm_flags_from_domain(domain);
105retry:
106 r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type,
107 flags, 0, 0, true, NULL, size,
108 &radeon_ttm_bo_destroy);
771fe6b9 109 if (unlikely(r != 0)) {
4c788679
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110 if (r == -ERESTART)
111 goto retry;
771fe6b9 112 /* ttm call radeon_ttm_object_object_destroy if error happen */
4c788679
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113 dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n",
114 size, flags);
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115 return r;
116 }
4c788679 117 *bo_ptr = bo;
771fe6b9 118 if (gobj) {
4c788679
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119 mutex_lock(&bo->rdev->gem.mutex);
120 list_add_tail(&bo->list, &rdev->gem.objects);
121 mutex_unlock(&bo->rdev->gem.mutex);
771fe6b9
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122 }
123 return 0;
124}
125
4c788679 126int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
771fe6b9 127{
4c788679 128 bool is_iomem;
771fe6b9
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129 int r;
130
4c788679 131 if (bo->kptr) {
771fe6b9 132 if (ptr) {
4c788679 133 *ptr = bo->kptr;
771fe6b9 134 }
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135 return 0;
136 }
4c788679 137 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
771fe6b9
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138 if (r) {
139 return r;
140 }
4c788679 141 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
771fe6b9 142 if (ptr) {
4c788679 143 *ptr = bo->kptr;
771fe6b9 144 }
4c788679 145 radeon_bo_check_tiling(bo, 0, 0);
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146 return 0;
147}
148
4c788679 149void radeon_bo_kunmap(struct radeon_bo *bo)
771fe6b9 150{
4c788679 151 if (bo->kptr == NULL)
771fe6b9 152 return;
4c788679
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153 bo->kptr = NULL;
154 radeon_bo_check_tiling(bo, 0, 0);
155 ttm_bo_kunmap(&bo->kmap);
771fe6b9
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156}
157
4c788679 158void radeon_bo_unref(struct radeon_bo **bo)
771fe6b9 159{
4c788679 160 struct ttm_buffer_object *tbo;
771fe6b9 161
4c788679 162 if ((*bo) == NULL)
771fe6b9 163 return;
4c788679
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164 tbo = &((*bo)->tbo);
165 ttm_bo_unref(&tbo);
166 if (tbo == NULL)
167 *bo = NULL;
771fe6b9
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168}
169
4c788679 170int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
771fe6b9 171{
4c788679
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172 u32 flags;
173 u32 tmp;
771fe6b9
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174 int r;
175
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176 flags = radeon_ttm_flags_from_domain(domain);
177 if (bo->pin_count) {
178 bo->pin_count++;
179 if (gpu_addr)
180 *gpu_addr = radeon_bo_gpu_offset(bo);
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181 return 0;
182 }
4c788679 183 tmp = bo->tbo.mem.placement;
771fe6b9 184 ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
4c788679
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185 bo->tbo.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT |
186 TTM_PL_MASK_CACHING;
187retry:
188 r = ttm_buffer_object_validate(&bo->tbo, bo->tbo.proposed_placement,
189 true, false);
190 if (likely(r == 0)) {
191 bo->pin_count = 1;
192 if (gpu_addr != NULL)
193 *gpu_addr = radeon_bo_gpu_offset(bo);
771fe6b9 194 }
771fe6b9 195 if (unlikely(r != 0)) {
4c788679
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196 if (r == -ERESTART)
197 goto retry;
198 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
771fe6b9 199 }
771fe6b9
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200 return r;
201}
202
4c788679 203int radeon_bo_unpin(struct radeon_bo *bo)
771fe6b9 204{
771fe6b9
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205 int r;
206
4c788679
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207 if (!bo->pin_count) {
208 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
209 return 0;
771fe6b9 210 }
4c788679
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211 bo->pin_count--;
212 if (bo->pin_count)
213 return 0;
214 bo->tbo.proposed_placement = bo->tbo.mem.placement &
215 ~TTM_PL_FLAG_NO_EVICT;
216retry:
217 r = ttm_buffer_object_validate(&bo->tbo, bo->tbo.proposed_placement,
218 true, false);
cefb87ef 219 if (unlikely(r != 0)) {
4c788679
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220 if (r == -ERESTART)
221 goto retry;
222 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
cefb87ef
DA
223 return r;
224 }
4c788679 225 return 0;
cefb87ef
DA
226}
227
4c788679 228int radeon_bo_evict_vram(struct radeon_device *rdev)
771fe6b9
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229{
230 if (rdev->flags & RADEON_IS_IGP) {
231 /* Useless to evict on IGP chips */
232 return 0;
233 }
234 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
235}
236
4c788679 237void radeon_bo_force_delete(struct radeon_device *rdev)
771fe6b9 238{
4c788679 239 struct radeon_bo *bo, *n;
771fe6b9
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240 struct drm_gem_object *gobj;
241
242 if (list_empty(&rdev->gem.objects)) {
243 return;
244 }
4c788679
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245 dev_err(rdev->dev, "Userspace still has active objects !\n");
246 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
771fe6b9 247 mutex_lock(&rdev->ddev->struct_mutex);
4c788679
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248 gobj = bo->gobj;
249 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
250 gobj, bo, (unsigned long)gobj->size,
251 *((unsigned long *)&gobj->refcount));
252 mutex_lock(&bo->rdev->gem.mutex);
253 list_del_init(&bo->list);
254 mutex_unlock(&bo->rdev->gem.mutex);
255 radeon_bo_unref(&bo);
771fe6b9
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256 gobj->driver_private = NULL;
257 drm_gem_object_unreference(gobj);
258 mutex_unlock(&rdev->ddev->struct_mutex);
259 }
260}
261
4c788679 262int radeon_bo_init(struct radeon_device *rdev)
771fe6b9 263{
a4d68279
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264 /* Add an MTRR for the VRAM */
265 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
266 MTRR_TYPE_WRCOMB, 1);
267 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
268 rdev->mc.mc_vram_size >> 20,
269 (unsigned long long)rdev->mc.aper_size >> 20);
270 DRM_INFO("RAM width %dbits %cDR\n",
271 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
771fe6b9
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272 return radeon_ttm_init(rdev);
273}
274
4c788679 275void radeon_bo_fini(struct radeon_device *rdev)
771fe6b9
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276{
277 radeon_ttm_fini(rdev);
278}
279
4c788679
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280void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
281 struct list_head *head)
771fe6b9
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282{
283 if (lobj->wdomain) {
284 list_add(&lobj->list, head);
285 } else {
286 list_add_tail(&lobj->list, head);
287 }
288}
289
4c788679 290int radeon_bo_list_reserve(struct list_head *head)
771fe6b9 291{
4c788679 292 struct radeon_bo_list *lobj;
771fe6b9
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293 int r;
294
9d8401fc 295 list_for_each_entry(lobj, head, list){
4c788679
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296 r = radeon_bo_reserve(lobj->bo, false);
297 if (unlikely(r != 0))
298 return r;
771fe6b9
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299 }
300 return 0;
301}
302
4c788679 303void radeon_bo_list_unreserve(struct list_head *head)
771fe6b9 304{
4c788679 305 struct radeon_bo_list *lobj;
771fe6b9 306
9d8401fc 307 list_for_each_entry(lobj, head, list) {
4c788679
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308 /* only unreserve object we successfully reserved */
309 if (radeon_bo_is_reserved(lobj->bo))
310 radeon_bo_unreserve(lobj->bo);
771fe6b9
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311 }
312}
313
4c788679 314int radeon_bo_list_validate(struct list_head *head, void *fence)
771fe6b9 315{
4c788679
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316 struct radeon_bo_list *lobj;
317 struct radeon_bo *bo;
771fe6b9 318 struct radeon_fence *old_fence = NULL;
771fe6b9
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319 int r;
320
4c788679 321 r = radeon_bo_list_reserve(head);
771fe6b9 322 if (unlikely(r != 0)) {
771fe6b9
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323 return r;
324 }
9d8401fc 325 list_for_each_entry(lobj, head, list) {
4c788679
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326 bo = lobj->bo;
327 if (!bo->pin_count) {
664f8659 328 if (lobj->wdomain) {
4c788679
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329 bo->tbo.proposed_placement =
330 radeon_ttm_flags_from_domain(lobj->wdomain);
664f8659 331 } else {
4c788679
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332 bo->tbo.proposed_placement =
333 radeon_ttm_flags_from_domain(lobj->rdomain);
664f8659 334 }
4c788679
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335retry:
336 r = ttm_buffer_object_validate(&bo->tbo,
337 bo->tbo.proposed_placement,
338 true, false);
771fe6b9 339 if (unlikely(r)) {
4c788679
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340 if (r == -ERESTART)
341 goto retry;
771fe6b9
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342 return r;
343 }
771fe6b9 344 }
4c788679
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345 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
346 lobj->tiling_flags = bo->tiling_flags;
771fe6b9 347 if (fence) {
4c788679
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348 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
349 bo->tbo.sync_obj = radeon_fence_ref(fence);
350 bo->tbo.sync_obj_arg = NULL;
771fe6b9
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351 }
352 if (old_fence) {
353 radeon_fence_unref(&old_fence);
354 }
355 }
356 return 0;
357}
358
4c788679 359void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
771fe6b9 360{
4c788679
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361 struct radeon_bo_list *lobj;
362 struct radeon_fence *old_fence;
771fe6b9 363
4c788679
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364 if (fence)
365 list_for_each_entry(lobj, head, list) {
366 old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
367 if (old_fence == fence) {
368 lobj->bo->tbo.sync_obj = NULL;
369 radeon_fence_unref(&old_fence);
370 }
771fe6b9 371 }
4c788679 372 radeon_bo_list_unreserve(head);
771fe6b9
JG
373}
374
4c788679 375int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
771fe6b9
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376 struct vm_area_struct *vma)
377{
4c788679 378 return ttm_fbdev_mmap(vma, &bo->tbo);
771fe6b9
JG
379}
380
4c788679 381static int radeon_bo_get_surface_reg(struct radeon_bo *bo)
771fe6b9 382{
4c788679 383 struct radeon_device *rdev = bo->rdev;
e024e110 384 struct radeon_surface_reg *reg;
4c788679 385 struct radeon_bo *old_object;
e024e110
DA
386 int steal;
387 int i;
388
4c788679
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389 BUG_ON(!atomic_read(&bo->tbo.reserved));
390
391 if (!bo->tiling_flags)
e024e110
DA
392 return 0;
393
4c788679
JG
394 if (bo->surface_reg >= 0) {
395 reg = &rdev->surface_regs[bo->surface_reg];
396 i = bo->surface_reg;
e024e110
DA
397 goto out;
398 }
399
400 steal = -1;
401 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
402
403 reg = &rdev->surface_regs[i];
4c788679 404 if (!reg->bo)
e024e110
DA
405 break;
406
4c788679 407 old_object = reg->bo;
e024e110
DA
408 if (old_object->pin_count == 0)
409 steal = i;
410 }
411
412 /* if we are all out */
413 if (i == RADEON_GEM_MAX_SURFACES) {
414 if (steal == -1)
415 return -ENOMEM;
416 /* find someone with a surface reg and nuke their BO */
417 reg = &rdev->surface_regs[steal];
4c788679 418 old_object = reg->bo;
e024e110
DA
419 /* blow away the mapping */
420 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
4c788679 421 ttm_bo_unmap_virtual(&old_object->tbo);
e024e110
DA
422 old_object->surface_reg = -1;
423 i = steal;
424 }
425
4c788679
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426 bo->surface_reg = i;
427 reg->bo = bo;
e024e110
DA
428
429out:
4c788679
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430 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
431 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
432 bo->tbo.num_pages << PAGE_SHIFT);
e024e110
DA
433 return 0;
434}
435
4c788679 436static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
e024e110 437{
4c788679 438 struct radeon_device *rdev = bo->rdev;
e024e110
DA
439 struct radeon_surface_reg *reg;
440
4c788679 441 if (bo->surface_reg == -1)
e024e110
DA
442 return;
443
4c788679
JG
444 reg = &rdev->surface_regs[bo->surface_reg];
445 radeon_clear_surface_reg(rdev, bo->surface_reg);
e024e110 446
4c788679
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447 reg->bo = NULL;
448 bo->surface_reg = -1;
e024e110
DA
449}
450
4c788679
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451int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
452 uint32_t tiling_flags, uint32_t pitch)
e024e110 453{
4c788679
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454 int r;
455
456 r = radeon_bo_reserve(bo, false);
457 if (unlikely(r != 0))
458 return r;
459 bo->tiling_flags = tiling_flags;
460 bo->pitch = pitch;
461 radeon_bo_unreserve(bo);
462 return 0;
e024e110
DA
463}
464
4c788679
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465void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
466 uint32_t *tiling_flags,
467 uint32_t *pitch)
e024e110 468{
4c788679 469 BUG_ON(!atomic_read(&bo->tbo.reserved));
e024e110 470 if (tiling_flags)
4c788679 471 *tiling_flags = bo->tiling_flags;
e024e110 472 if (pitch)
4c788679 473 *pitch = bo->pitch;
e024e110
DA
474}
475
4c788679
JG
476int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
477 bool force_drop)
e024e110 478{
4c788679
JG
479 BUG_ON(!atomic_read(&bo->tbo.reserved));
480
481 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
e024e110
DA
482 return 0;
483
484 if (force_drop) {
4c788679 485 radeon_bo_clear_surface_reg(bo);
e024e110
DA
486 return 0;
487 }
488
4c788679 489 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
e024e110
DA
490 if (!has_moved)
491 return 0;
492
4c788679
JG
493 if (bo->surface_reg >= 0)
494 radeon_bo_clear_surface_reg(bo);
e024e110
DA
495 return 0;
496 }
497
4c788679 498 if ((bo->surface_reg >= 0) && !has_moved)
e024e110
DA
499 return 0;
500
4c788679 501 return radeon_bo_get_surface_reg(bo);
e024e110
DA
502}
503
504void radeon_bo_move_notify(struct ttm_buffer_object *bo,
4c788679 505 struct ttm_mem_reg *mem)
e024e110 506{
4c788679
JG
507 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
508 radeon_bo_check_tiling(rbo, 0, 1);
e024e110
DA
509}
510
511void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
512{
4c788679
JG
513 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
514 radeon_bo_check_tiling(rbo, 0, 0);
e024e110 515}
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