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drm/radeon: fix VM flush on CIK (v3)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
1c71bda0
AD		 70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
96682956
AD		 76 if (rdev->family == CHIP_ARUBA) {
77 if (rdev->asic->dpm.enable_bapm)
78 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
79 }
1c71bda0
AD		 80 mutex_unlock(&rdev->pm.mutex);
81 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
c4917074
AD		 82 if (rdev->pm.profile == PM_PROFILE_AUTO) {
83 mutex_lock(&rdev->pm.mutex);
84 radeon_pm_update_profile(rdev);
85 radeon_pm_set_clocks(rdev);
86 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 87 }
88 }
ce8f5370 89}
ce8f5370
AD		 90
91static void radeon_pm_update_profile(struct radeon_device *rdev)
92{
93 switch (rdev->pm.profile) {
94 case PM_PROFILE_DEFAULT:
95 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
96 break;
97 case PM_PROFILE_AUTO:
98 if (power_supply_is_system_supplied() > 0) {
99 if (rdev->pm.active_crtc_count > 1)
100 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
101 else
102 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
103 } else {
104 if (rdev->pm.active_crtc_count > 1)
c9e75b21 105 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 106 else
c9e75b21 107 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 108 }
109 break;
110 case PM_PROFILE_LOW:
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
113 else
114 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
115 break;
c9e75b21
AD		 116 case PM_PROFILE_MID:
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
119 else
120 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
121 break;
ce8f5370
AD		 122 case PM_PROFILE_HIGH:
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
125 else
126 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
127 break;
128 }
129
130 if (rdev->pm.active_crtc_count == 0) {
131 rdev->pm.requested_power_state_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
133 rdev->pm.requested_clock_mode_index =
134 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
135 } else {
136 rdev->pm.requested_power_state_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
138 rdev->pm.requested_clock_mode_index =
139 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
140 }
141}
c913e23a 142
5876dd24
MG		 143static void radeon_unmap_vram_bos(struct radeon_device *rdev)
144{
145 struct radeon_bo *bo, *n;
146
147 if (list_empty(&rdev->gem.objects))
148 return;
149
150 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
151 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
152 ttm_bo_unmap_virtual(&bo->tbo);
153 }
5876dd24
MG		 154}
155
ce8f5370 156static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 157{
ce8f5370
AD		 158 if (rdev->pm.active_crtcs) {
159 rdev->pm.vblank_sync = false;
160 wait_event_timeout(
161 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
162 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
163 }
164}
165
166static void radeon_set_power_state(struct radeon_device *rdev)
167{
168 u32 sclk, mclk;
92645879 169 bool misc_after = false;
ce8f5370
AD		 170
171 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
172 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
173 return;
174
175 if (radeon_gui_idle(rdev)) {
176 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
177 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 178 if (sclk > rdev->pm.default_sclk)
179 sclk = rdev->pm.default_sclk;
ce8f5370 180
27810fb2
AD		 181 /* starting with BTC, there is one state that is used for both
182 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 183 * mclk and vddci.
27810fb2
AD		 184 */
185 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
186 (rdev->family >= CHIP_BARTS) &&
187 rdev->pm.active_crtc_count &&
188 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
189 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
190 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
191 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
192 else
193 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
194 clock_info[rdev->pm.requested_clock_mode_index].mclk;
195
9ace9f7b
AD		 196 if (mclk > rdev->pm.default_mclk)
197 mclk = rdev->pm.default_mclk;
ce8f5370 198
92645879
AD		 199 /* upvolt before raising clocks, downvolt after lowering clocks */
200 if (sclk < rdev->pm.current_sclk)
201 misc_after = true;
ce8f5370 202
92645879 203 radeon_sync_with_vblank(rdev);
ce8f5370 204
92645879 205 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 206 if (!radeon_pm_in_vbl(rdev))
207 return;
92645879 208 }
ce8f5370 209
92645879 210 radeon_pm_prepare(rdev);
ce8f5370 211
92645879
AD		 212 if (!misc_after)
213 /* voltage, pcie lanes, etc.*/
214 radeon_pm_misc(rdev);
215
216 /* set engine clock */
217 if (sclk != rdev->pm.current_sclk) {
218 radeon_pm_debug_check_in_vbl(rdev, false);
219 radeon_set_engine_clock(rdev, sclk);
220 radeon_pm_debug_check_in_vbl(rdev, true);
221 rdev->pm.current_sclk = sclk;
d9fdaafb 222 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 223 }
224
225 /* set memory clock */
798bcf73 226 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 227 radeon_pm_debug_check_in_vbl(rdev, false);
228 radeon_set_memory_clock(rdev, mclk);
229 radeon_pm_debug_check_in_vbl(rdev, true);
230 rdev->pm.current_mclk = mclk;
d9fdaafb 231 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 232 }
2aba631c 233
92645879
AD		 234 if (misc_after)
235 /* voltage, pcie lanes, etc.*/
236 radeon_pm_misc(rdev);
237
238 radeon_pm_finish(rdev);
239
ce8f5370
AD		 240 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
241 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
242 } else
d9fdaafb 243 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 244}
245
246static void radeon_pm_set_clocks(struct radeon_device *rdev)
247{
5f8f635e 248 int i, r;
c37d230a 249
4e186b2d
AD		 250 /* no need to take locks, etc. if nothing's going to change */
251 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
252 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
253 return;
254
612e06ce 255 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 256 down_write(&rdev->pm.mclk_lock);
d6999bc7 257 mutex_lock(&rdev->ring_lock);
4f3218cb 258
95f5a3ac
AD		 259 /* wait for the rings to drain */
260 for (i = 0; i < RADEON_NUM_RINGS; i++) {
261 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 262 if (!ring->ready) {
263 continue;
264 }
37615527 265 r = radeon_fence_wait_empty(rdev, i);
5f8f635e
JG		 266 if (r) {
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev->ring_lock);
269 up_write(&rdev->pm.mclk_lock);
270 mutex_unlock(&rdev->ddev->struct_mutex);
271 return;
272 }
4f3218cb 273 }
95f5a3ac 274
5876dd24
MG		 275 radeon_unmap_vram_bos(rdev);
276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.active_crtcs & (1 << i)) {
280 rdev->pm.req_vblank |= (1 << i);
281 drm_vblank_get(rdev->ddev, i);
282 }
283 }
284 }
539d2418 285
ce8f5370 286 radeon_set_power_state(rdev);
2aba631c 287
ce8f5370 288 if (rdev->irq.installed) {
2aba631c
MG		 289 for (i = 0; i < rdev->num_crtc; i++) {
290 if (rdev->pm.req_vblank & (1 << i)) {
291 rdev->pm.req_vblank &= ~(1 << i);
292 drm_vblank_put(rdev->ddev, i);
293 }
294 }
295 }
5876dd24 296
a424816f
AD		 297 /* update display watermarks based on new power state */
298 radeon_update_bandwidth_info(rdev);
299 if (rdev->pm.active_crtc_count)
300 radeon_bandwidth_update(rdev);
301
ce8f5370 302 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 303
d6999bc7 304 mutex_unlock(&rdev->ring_lock);
db7fce39 305 up_write(&rdev->pm.mclk_lock);
612e06ce 306 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 307}
308
f712d0c7
RM		 309static void radeon_pm_print_states(struct radeon_device *rdev)
310{
311 int i, j;
312 struct radeon_power_state *power_state;
313 struct radeon_pm_clock_info *clock_info;
314
d9fdaafb 315 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 316 for (i = 0; i < rdev->pm.num_power_states; i++) {
317 power_state = &rdev->pm.power_state[i];
d9fdaafb 318 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 319 radeon_pm_state_type_name[power_state->type]);
320 if (i == rdev->pm.default_power_state_index)
d9fdaafb 321 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 322 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 323 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 324 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 325 DRM_DEBUG_DRIVER("\tSingle display only\n");
326 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 327 for (j = 0; j < power_state->num_clock_modes; j++) {
328 clock_info = &(power_state->clock_info[j]);
329 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 330 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
331 j,
332 clock_info->sclk * 10);
f712d0c7 333 else
eb2c27a0
AD		 334 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
335 j,
336 clock_info->sclk * 10,
337 clock_info->mclk * 10,
338 clock_info->voltage.voltage);
f712d0c7
RM		 339 }
340 }
341}
342
ce8f5370
AD		 343static ssize_t radeon_get_pm_profile(struct device *dev,
344 struct device_attribute *attr,
345 char *buf)
a424816f 346{
3e4e2129 347 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 348 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 349 int cp = rdev->pm.profile;
a424816f 350
ce8f5370
AD		 351 return snprintf(buf, PAGE_SIZE, "%s\n",
352 (cp == PM_PROFILE_AUTO) ? "auto" :
353 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 354 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 355 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 356}
357
ce8f5370
AD		 358static ssize_t radeon_set_pm_profile(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf,
361 size_t count)
a424816f 362{
3e4e2129 363 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 364 struct radeon_device *rdev = ddev->dev_private;
a424816f 365
4f2f2039
AD		 366 /* Can't set profile when the card is off */
367 if ((rdev->flags & RADEON_IS_PX) &&
368 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
369 return -EINVAL;
370
a424816f 371 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 372 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
373 if (strncmp("default", buf, strlen("default")) == 0)
374 rdev->pm.profile = PM_PROFILE_DEFAULT;
375 else if (strncmp("auto", buf, strlen("auto")) == 0)
376 rdev->pm.profile = PM_PROFILE_AUTO;
377 else if (strncmp("low", buf, strlen("low")) == 0)
378 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 379 else if (strncmp("mid", buf, strlen("mid")) == 0)
380 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 381 else if (strncmp("high", buf, strlen("high")) == 0)
382 rdev->pm.profile = PM_PROFILE_HIGH;
383 else {
1783e4bf 384 count = -EINVAL;
ce8f5370 385 goto fail;
a424816f 386 }
ce8f5370
AD		 387 radeon_pm_update_profile(rdev);
388 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 389 } else
390 count = -EINVAL;
391
ce8f5370 392fail:
a424816f
AD		 393 mutex_unlock(&rdev->pm.mutex);
394
395 return count;
396}
397
ce8f5370
AD		 398static ssize_t radeon_get_pm_method(struct device *dev,
399 struct device_attribute *attr,
400 char *buf)
a424816f 401{
3e4e2129 402 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 403 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 404 int pm = rdev->pm.pm_method;
a424816f
AD		 405
406 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 407 (pm == PM_METHOD_DYNPM) ? "dynpm" :
408 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 409}
410
ce8f5370
AD		 411static ssize_t radeon_set_pm_method(struct device *dev,
412 struct device_attribute *attr,
413 const char *buf,
414 size_t count)
a424816f 415{
3e4e2129 416 struct drm_device *ddev = dev_get_drvdata(dev);
a424816f 417 struct radeon_device *rdev = ddev->dev_private;
a424816f 418
4f2f2039
AD		 419 /* Can't set method when the card is off */
420 if ((rdev->flags & RADEON_IS_PX) &&
421 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
422 count = -EINVAL;
423 goto fail;
424 }
425
da321c8a
AD		 426 /* we don't support the legacy modes with dpm */
427 if (rdev->pm.pm_method == PM_METHOD_DPM) {
428 count = -EINVAL;
429 goto fail;
430 }
ce8f5370
AD		 431
432 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 433 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 434 rdev->pm.pm_method = PM_METHOD_DYNPM;
435 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
436 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 437 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 438 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
439 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 440 /* disable dynpm */
441 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
442 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 443 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 444 mutex_unlock(&rdev->pm.mutex);
32c87fca 445 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 446 } else {
1783e4bf 447 count = -EINVAL;
ce8f5370
AD		 448 goto fail;
449 }
450 radeon_pm_compute_clocks(rdev);
451fail:
a424816f
AD		 452 return count;
453}
454
da321c8a
AD		 455static ssize_t radeon_get_dpm_state(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458{
3e4e2129 459 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 460 struct radeon_device *rdev = ddev->dev_private;
461 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
462
463 return snprintf(buf, PAGE_SIZE, "%s\n",
464 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
465 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
466}
467
468static ssize_t radeon_set_dpm_state(struct device *dev,
469 struct device_attribute *attr,
470 const char *buf,
471 size_t count)
472{
3e4e2129 473 struct drm_device *ddev = dev_get_drvdata(dev);
da321c8a
AD		 474 struct radeon_device *rdev = ddev->dev_private;
475
476 mutex_lock(&rdev->pm.mutex);
477 if (strncmp("battery", buf, strlen("battery")) == 0)
478 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
479 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
481 else if (strncmp("performance", buf, strlen("performance")) == 0)
482 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
483 else {
484 mutex_unlock(&rdev->pm.mutex);
485 count = -EINVAL;
486 goto fail;
487 }
488 mutex_unlock(&rdev->pm.mutex);
b07a657e
PR		 489
490 /* Can't set dpm state when the card is off */
491 if (!(rdev->flags & RADEON_IS_PX) ||
492 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
493 radeon_pm_compute_clocks(rdev);
494
da321c8a
AD		 495fail:
496 return count;
497}
498
70d01a5e
AD		 499static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
500 struct device_attribute *attr,
501 char *buf)
502{
3e4e2129 503 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 504 struct radeon_device *rdev = ddev->dev_private;
505 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
506
4f2f2039
AD		 507 if ((rdev->flags & RADEON_IS_PX) &&
508 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
509 return snprintf(buf, PAGE_SIZE, "off\n");
510
70d01a5e
AD		 511 return snprintf(buf, PAGE_SIZE, "%s\n",
512 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
513 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
514}
515
516static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
517 struct device_attribute *attr,
518 const char *buf,
519 size_t count)
520{
3e4e2129 521 struct drm_device *ddev = dev_get_drvdata(dev);
70d01a5e
AD		 522 struct radeon_device *rdev = ddev->dev_private;
523 enum radeon_dpm_forced_level level;
524 int ret = 0;
525
4f2f2039
AD		 526 /* Can't force performance level when the card is off */
527 if ((rdev->flags & RADEON_IS_PX) &&
528 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
529 return -EINVAL;
530
70d01a5e
AD		 531 mutex_lock(&rdev->pm.mutex);
532 if (strncmp("low", buf, strlen("low")) == 0) {
533 level = RADEON_DPM_FORCED_LEVEL_LOW;
534 } else if (strncmp("high", buf, strlen("high")) == 0) {
535 level = RADEON_DPM_FORCED_LEVEL_HIGH;
536 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
537 level = RADEON_DPM_FORCED_LEVEL_AUTO;
538 } else {
70d01a5e
AD		 539 count = -EINVAL;
540 goto fail;
541 }
542 if (rdev->asic->dpm.force_performance_level) {
0a17af37
AD		 543 if (rdev->pm.dpm.thermal_active) {
544 count = -EINVAL;
545 goto fail;
546 }
70d01a5e
AD		 547 ret = radeon_dpm_force_performance_level(rdev, level);
548 if (ret)
549 count = -EINVAL;
550 }
70d01a5e 551fail:
0a17af37
AD		 552 mutex_unlock(&rdev->pm.mutex);
553
70d01a5e
AD		 554 return count;
555}
556
ce8f5370
AD		 557static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
558static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 559static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
70d01a5e
AD		 560static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
561 radeon_get_dpm_forced_performance_level,
562 radeon_set_dpm_forced_performance_level);
a424816f 563
21a8122a
AD		 564static ssize_t radeon_hwmon_show_temp(struct device *dev,
565 struct device_attribute *attr,
566 char *buf)
567{
ec39f64b 568 struct radeon_device *rdev = dev_get_drvdata(dev);
4f2f2039 569 struct drm_device *ddev = rdev->ddev;
20d391d7 570 int temp;
21a8122a 571
4f2f2039
AD		 572 /* Can't get temperature when the card is off */
573 if ((rdev->flags & RADEON_IS_PX) &&
574 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
575 return -EINVAL;
576
6bd1c385
AD		 577 if (rdev->asic->pm.get_temperature)
578 temp = radeon_get_temperature(rdev);
579 else
21a8122a 580 temp = 0;
21a8122a
AD		 581
582 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
583}
584
6ea4e84d
JD		 585static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
586 struct device_attribute *attr,
587 char *buf)
588{
e4158f1b 589 struct radeon_device *rdev = dev_get_drvdata(dev);
6ea4e84d
JD		 590 int hyst = to_sensor_dev_attr(attr)->index;
591 int temp;
592
593 if (hyst)
594 temp = rdev->pm.dpm.thermal.min_temp;
595 else
596 temp = rdev->pm.dpm.thermal.max_temp;
597
598 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
599}
600
21a8122a 601static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
6ea4e84d
JD		 602static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
603static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
21a8122a
AD		 604
605static struct attribute *hwmon_attributes[] = {
606 &sensor_dev_attr_temp1_input.dev_attr.attr,
6ea4e84d
JD		 607 &sensor_dev_attr_temp1_crit.dev_attr.attr,
608 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
21a8122a
AD		 609 NULL
610};
611
6ea4e84d
JD		 612static umode_t hwmon_attributes_visible(struct kobject *kobj,
613 struct attribute *attr, int index)
614{
615 struct device *dev = container_of(kobj, struct device, kobj);
e4158f1b 616 struct radeon_device *rdev = dev_get_drvdata(dev);
6ea4e84d
JD		 617
618 /* Skip limit attributes if DPM is not enabled */
619 if (rdev->pm.pm_method != PM_METHOD_DPM &&
620 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
621 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
622 return 0;
623
624 return attr->mode;
625}
626
21a8122a
AD		 627static const struct attribute_group hwmon_attrgroup = {
628 .attrs = hwmon_attributes,
6ea4e84d 629 .is_visible = hwmon_attributes_visible,
21a8122a
AD		 630};
631
ec39f64b
GR		 632static const struct attribute_group *hwmon_groups[] = {
633 &hwmon_attrgroup,
634 NULL
635};
636
0d18abed 637static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 638{
0d18abed 639 int err = 0;
21a8122a
AD		 640
641 switch (rdev->pm.int_thermal_type) {
642 case THERMAL_TYPE_RV6XX:
643 case THERMAL_TYPE_RV770:
644 case THERMAL_TYPE_EVERGREEN:
457558ed 645 case THERMAL_TYPE_NI:
e33df25f 646 case THERMAL_TYPE_SUMO:
1bd47d2e 647 case THERMAL_TYPE_SI:
286d9cc6
AD		 648 case THERMAL_TYPE_CI:
649 case THERMAL_TYPE_KV:
6bd1c385 650 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 651 return err;
cb3e4e7c
AD		 652 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
653 "radeon", rdev,
654 hwmon_groups);
655 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
656 err = PTR_ERR(rdev->pm.int_hwmon_dev);
0d18abed
DC		 657 dev_err(rdev->dev,
658 "Unable to register hwmon device: %d\n", err);
0d18abed 659 }
21a8122a
AD		 660 break;
661 default:
662 break;
663 }
0d18abed
DC		 664
665 return err;
21a8122a
AD		 666}
667
cb3e4e7c
AD		 668static void radeon_hwmon_fini(struct radeon_device *rdev)
669{
670 if (rdev->pm.int_hwmon_dev)
671 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
672}
673
da321c8a
AD		 674static void radeon_dpm_thermal_work_handler(struct work_struct *work)
675{
676 struct radeon_device *rdev =
677 container_of(work, struct radeon_device,
678 pm.dpm.thermal.work);
679 /* switch to the thermal state */
680 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
681
682 if (!rdev->pm.dpm_enabled)
683 return;
684
685 if (rdev->asic->pm.get_temperature) {
686 int temp = radeon_get_temperature(rdev);
687
688 if (temp < rdev->pm.dpm.thermal.min_temp)
689 /* switch back the user state */
690 dpm_state = rdev->pm.dpm.user_state;
691 } else {
692 if (rdev->pm.dpm.thermal.high_to_low)
693 /* switch back the user state */
694 dpm_state = rdev->pm.dpm.user_state;
695 }
60320347
AD		 696 mutex_lock(&rdev->pm.mutex);
697 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
698 rdev->pm.dpm.thermal_active = true;
699 else
700 rdev->pm.dpm.thermal_active = false;
701 rdev->pm.dpm.state = dpm_state;
702 mutex_unlock(&rdev->pm.mutex);
703
704 radeon_pm_compute_clocks(rdev);
da321c8a
AD		 705}
706
707static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
708 enum radeon_pm_state_type dpm_state)
709{
710 int i;
711 struct radeon_ps *ps;
712 u32 ui_class;
48783069
AD		 713 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
714 true : false;
715
716 /* check if the vblank period is too short to adjust the mclk */
717 if (single_display && rdev->asic->dpm.vblank_too_short) {
718 if (radeon_dpm_vblank_too_short(rdev))
719 single_display = false;
720 }
da321c8a 721
edcaa5b1
AD		 722 /* certain older asics have a separare 3D performance state,
723 * so try that first if the user selected performance
724 */
725 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
726 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 727 /* balanced states don't exist at the moment */
728 if (dpm_state == POWER_STATE_TYPE_BALANCED)
729 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
730
edcaa5b1 731restart_search:
da321c8a
AD		 732 /* Pick the best power state based on current conditions */
733 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
734 ps = &rdev->pm.dpm.ps[i];
735 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
736 switch (dpm_state) {
737 /* user states */
738 case POWER_STATE_TYPE_BATTERY:
739 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
740 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 741 if (single_display)
da321c8a
AD		 742 return ps;
743 } else
744 return ps;
745 }
746 break;
747 case POWER_STATE_TYPE_BALANCED:
748 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
749 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 750 if (single_display)
da321c8a
AD		 751 return ps;
752 } else
753 return ps;
754 }
755 break;
756 case POWER_STATE_TYPE_PERFORMANCE:
757 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
758 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
48783069 759 if (single_display)
da321c8a
AD		 760 return ps;
761 } else
762 return ps;
763 }
764 break;
765 /* internal states */
766 case POWER_STATE_TYPE_INTERNAL_UVD:
d4d3278c
AD		 767 if (rdev->pm.dpm.uvd_ps)
768 return rdev->pm.dpm.uvd_ps;
769 else
770 break;
da321c8a
AD		 771 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
772 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
773 return ps;
774 break;
775 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
776 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
777 return ps;
778 break;
779 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
780 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
781 return ps;
782 break;
783 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
784 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
785 return ps;
786 break;
787 case POWER_STATE_TYPE_INTERNAL_BOOT:
788 return rdev->pm.dpm.boot_ps;
789 case POWER_STATE_TYPE_INTERNAL_THERMAL:
790 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
791 return ps;
792 break;
793 case POWER_STATE_TYPE_INTERNAL_ACPI:
794 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
795 return ps;
796 break;
797 case POWER_STATE_TYPE_INTERNAL_ULV:
798 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
799 return ps;
800 break;
edcaa5b1
AD		 801 case POWER_STATE_TYPE_INTERNAL_3DPERF:
802 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
803 return ps;
804 break;
da321c8a
AD		 805 default:
806 break;
807 }
808 }
809 /* use a fallback state if we didn't match */
810 switch (dpm_state) {
811 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
ce3537d5
AD		 812 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
813 goto restart_search;
da321c8a
AD		 814 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
815 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
816 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
d4d3278c
AD		 817 if (rdev->pm.dpm.uvd_ps) {
818 return rdev->pm.dpm.uvd_ps;
819 } else {
820 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
821 goto restart_search;
822 }
da321c8a
AD		 823 case POWER_STATE_TYPE_INTERNAL_THERMAL:
824 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
825 goto restart_search;
826 case POWER_STATE_TYPE_INTERNAL_ACPI:
827 dpm_state = POWER_STATE_TYPE_BATTERY;
828 goto restart_search;
829 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 830 case POWER_STATE_TYPE_BALANCED:
831 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 832 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
833 goto restart_search;
834 default:
835 break;
836 }
837
838 return NULL;
839}
840
841static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
842{
843 int i;
844 struct radeon_ps *ps;
845 enum radeon_pm_state_type dpm_state;
84dd1928 846 int ret;
da321c8a
AD		 847
848 /* if dpm init failed */
849 if (!rdev->pm.dpm_enabled)
850 return;
851
852 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
853 /* add other state override checks here */
8a227555
AD		 854 if ((!rdev->pm.dpm.thermal_active) &&
855 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 856 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
857 }
858 dpm_state = rdev->pm.dpm.state;
859
860 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
861 if (ps)
89c9bc56 862 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 863 else
864 return;
865
d22b7e40 866 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 867 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
b62d628b
AD		 868 /* vce just modifies an existing state so force a change */
869 if (ps->vce_active != rdev->pm.dpm.vce_active)
870 goto force;
d22b7e40
AD		 871 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
872 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
873 * all we need to do is update the display configuration.
874 */
875 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
876 /* update display watermarks based on new power state */
877 radeon_bandwidth_update(rdev);
878 /* update displays */
879 radeon_dpm_display_configuration_changed(rdev);
880 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
881 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
882 }
883 return;
884 } else {
885 /* for BTC+ if the num crtcs hasn't changed and state is the same,
886 * nothing to do, if the num crtcs is > 1 and state is the same,
887 * update display configuration.
888 */
889 if (rdev->pm.dpm.new_active_crtcs ==
890 rdev->pm.dpm.current_active_crtcs) {
891 return;
892 } else {
893 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
894 (rdev->pm.dpm.new_active_crtc_count > 1)) {
895 /* update display watermarks based on new power state */
896 radeon_bandwidth_update(rdev);
897 /* update displays */
898 radeon_dpm_display_configuration_changed(rdev);
899 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
900 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
901 return;
902 }
903 }
da321c8a 904 }
da321c8a
AD		 905 }
906
b62d628b 907force:
033a37df
AD		 908 if (radeon_dpm == 1) {
909 printk("switching from power state:\n");
910 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
911 printk("switching to power state:\n");
912 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
913 }
b62d628b 914
da321c8a
AD		 915 mutex_lock(&rdev->ddev->struct_mutex);
916 down_write(&rdev->pm.mclk_lock);
917 mutex_lock(&rdev->ring_lock);
918
b62d628b
AD		 919 /* update whether vce is active */
920 ps->vce_active = rdev->pm.dpm.vce_active;
921
89c9bc56
AD		 922 ret = radeon_dpm_pre_set_power_state(rdev);
923 if (ret)
924 goto done;
84dd1928 925
da321c8a
AD		 926 /* update display watermarks based on new power state */
927 radeon_bandwidth_update(rdev);
928 /* update displays */
929 radeon_dpm_display_configuration_changed(rdev);
930
931 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
932 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
933
934 /* wait for the rings to drain */
935 for (i = 0; i < RADEON_NUM_RINGS; i++) {
936 struct radeon_ring *ring = &rdev->ring[i];
937 if (ring->ready)
37615527 938 radeon_fence_wait_empty(rdev, i);
da321c8a
AD		 939 }
940
941 /* program the new power state */
942 radeon_dpm_set_power_state(rdev);
943
944 /* update current power state */
945 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
946
89c9bc56 947 radeon_dpm_post_set_power_state(rdev);
84dd1928 948
1cd8b21a 949 if (rdev->asic->dpm.force_performance_level) {
14ac88af
AD		 950 if (rdev->pm.dpm.thermal_active) {
951 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1cd8b21a
AD		 952 /* force low perf level for thermal */
953 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
14ac88af
AD		 954 /* save the user's level */
955 rdev->pm.dpm.forced_level = level;
956 } else {
957 /* otherwise, user selected level */
958 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
959 }
60320347
AD		 960 }
961
84dd1928 962done:
da321c8a
AD		 963 mutex_unlock(&rdev->ring_lock);
964 up_write(&rdev->pm.mclk_lock);
965 mutex_unlock(&rdev->ddev->struct_mutex);
966}
967
ce3537d5
AD		 968void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
969{
970 enum radeon_pm_state_type dpm_state;
971
9e9d9762 972 if (rdev->asic->dpm.powergate_uvd) {
ce3537d5 973 mutex_lock(&rdev->pm.mutex);
8158eb9e
CK		 974 /* don't powergate anything if we
975 have active but pause streams */
976 enable |= rdev->pm.dpm.sd > 0;
977 enable |= rdev->pm.dpm.hd > 0;
9e9d9762
AD		 978 /* enable/disable UVD */
979 radeon_dpm_powergate_uvd(rdev, !enable);
ce3537d5
AD		 980 mutex_unlock(&rdev->pm.mutex);
981 } else {
9e9d9762
AD		 982 if (enable) {
983 mutex_lock(&rdev->pm.mutex);
984 rdev->pm.dpm.uvd_active = true;
0690a229
AD		 985 /* disable this for now */
986#if 0
9e9d9762
AD		 987 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
988 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
989 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
990 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
991 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
992 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
993 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
994 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
995 else
0690a229 996#endif
9e9d9762
AD		 997 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
998 rdev->pm.dpm.state = dpm_state;
999 mutex_unlock(&rdev->pm.mutex);
1000 } else {
1001 mutex_lock(&rdev->pm.mutex);
1002 rdev->pm.dpm.uvd_active = false;
1003 mutex_unlock(&rdev->pm.mutex);
1004 }
ce3537d5 1005
9e9d9762
AD		 1006 radeon_pm_compute_clocks(rdev);
1007 }
ce3537d5
AD		 1008}
1009
03afe6f6
AD		 1010void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1011{
1012 if (enable) {
1013 mutex_lock(&rdev->pm.mutex);
1014 rdev->pm.dpm.vce_active = true;
1015 /* XXX select vce level based on ring/task */
1016 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1017 mutex_unlock(&rdev->pm.mutex);
1018 } else {
1019 mutex_lock(&rdev->pm.mutex);
1020 rdev->pm.dpm.vce_active = false;
1021 mutex_unlock(&rdev->pm.mutex);
1022 }
1023
1024 radeon_pm_compute_clocks(rdev);
1025}
1026
da321c8a 1027static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 1028{
ce8f5370 1029 mutex_lock(&rdev->pm.mutex);
3f53eb6f 1030 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 1031 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1032 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 1033 }
ce8f5370 1034 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1035
1036 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 1037}
1038
da321c8a
AD		 1039static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1040{
1041 mutex_lock(&rdev->pm.mutex);
1042 /* disable dpm */
1043 radeon_dpm_disable(rdev);
1044 /* reset the power state */
1045 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1046 rdev->pm.dpm_enabled = false;
1047 mutex_unlock(&rdev->pm.mutex);
1048}
1049
1050void radeon_pm_suspend(struct radeon_device *rdev)
1051{
1052 if (rdev->pm.pm_method == PM_METHOD_DPM)
1053 radeon_pm_suspend_dpm(rdev);
1054 else
1055 radeon_pm_suspend_old(rdev);
1056}
1057
1058static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 1059{
ed18a360 1060 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1061 if ((rdev->family >= CHIP_BARTS) &&
36099186 1062 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1063 rdev->mc_fw) {
ed18a360 1064 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1065 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1066 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 1067 if (rdev->pm.default_vddci)
1068 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1069 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1070 if (rdev->pm.default_sclk)
1071 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1072 if (rdev->pm.default_mclk)
1073 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1074 }
f8ed8b4c
AD		 1075 /* asic init will reset the default power state */
1076 mutex_lock(&rdev->pm.mutex);
1077 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1078 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 1079 rdev->pm.current_sclk = rdev->pm.default_sclk;
1080 rdev->pm.current_mclk = rdev->pm.default_mclk;
37016951
MD		 1081 if (rdev->pm.power_state) {
1082 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1083 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1084 }
3f53eb6f
RW		 1085 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1086 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1087 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1088 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1089 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 1090 }
f8ed8b4c 1091 mutex_unlock(&rdev->pm.mutex);
ce8f5370 1092 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 1093}
1094
da321c8a
AD		 1095static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1096{
1097 int ret;
1098
1099 /* asic init will reset to the boot state */
1100 mutex_lock(&rdev->pm.mutex);
1101 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1102 radeon_dpm_setup_asic(rdev);
1103 ret = radeon_dpm_enable(rdev);
1104 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1105 if (ret)
1106 goto dpm_resume_fail;
e14cd2bb 1107 rdev->pm.dpm_enabled = true;
e14cd2bb
AD		 1108 return;
1109
1110dpm_resume_fail:
1111 DRM_ERROR("radeon: dpm resume failed\n");
1112 if ((rdev->family >= CHIP_BARTS) &&
1113 (rdev->family <= CHIP_CAYMAN) &&
1114 rdev->mc_fw) {
1115 if (rdev->pm.default_vddc)
1116 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1117 SET_VOLTAGE_TYPE_ASIC_VDDC);
1118 if (rdev->pm.default_vddci)
1119 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1120 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1121 if (rdev->pm.default_sclk)
1122 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1123 if (rdev->pm.default_mclk)
1124 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
da321c8a
AD		 1125 }
1126}
1127
1128void radeon_pm_resume(struct radeon_device *rdev)
1129{
1130 if (rdev->pm.pm_method == PM_METHOD_DPM)
1131 radeon_pm_resume_dpm(rdev);
1132 else
1133 radeon_pm_resume_old(rdev);
1134}
1135
1136static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 1137{
26481fb1 1138 int ret;
0d18abed 1139
f8ed8b4c 1140 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 1141 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1142 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1143 rdev->pm.dynpm_can_upclock = true;
1144 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 1145 rdev->pm.default_sclk = rdev->clock.default_sclk;
1146 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 1147 rdev->pm.current_sclk = rdev->clock.default_sclk;
1148 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 1149 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 1150
56278a8e
AD		 1151 if (rdev->bios) {
1152 if (rdev->is_atom_bios)
1153 radeon_atombios_get_power_modes(rdev);
1154 else
1155 radeon_combios_get_power_modes(rdev);
f712d0c7 1156 radeon_pm_print_states(rdev);
ce8f5370 1157 radeon_pm_init_profile(rdev);
ed18a360 1158 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 1159 if ((rdev->family >= CHIP_BARTS) &&
36099186 1160 (rdev->family <= CHIP_CAYMAN) &&
2e3b3b10 1161 rdev->mc_fw) {
ed18a360 1162 if (rdev->pm.default_vddc)
8a83ec5e
AD		 1163 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1164 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 1165 if (rdev->pm.default_vddci)
1166 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1167 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 1168 if (rdev->pm.default_sclk)
1169 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1170 if (rdev->pm.default_mclk)
1171 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1172 }
56278a8e
AD		 1173 }
1174
21a8122a 1175 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 1176 ret = radeon_hwmon_init(rdev);
1177 if (ret)
1178 return ret;
32c87fca
TH		 1179
1180 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1181
ce8f5370 1182 if (rdev->pm.num_power_states > 1) {
ce8f5370 1183 /* where's the best place to put these? */
26481fb1
DA		 1184 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1185 if (ret)
1186 DRM_ERROR("failed to create device file for power profile\n");
1187 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1188 if (ret)
1189 DRM_ERROR("failed to create device file for power method\n");
a424816f 1190
ce8f5370
AD		 1191 if (radeon_debugfs_pm_init(rdev)) {
1192 DRM_ERROR("Failed to register debugfs file for PM!\n");
1193 }
c913e23a 1194
ce8f5370
AD		 1195 DRM_INFO("radeon: power management initialized\n");
1196 }
c913e23a 1197
7433874e
RM		 1198 return 0;
1199}
1200
da321c8a
AD		 1201static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1202{
1203 int i;
1204
1205 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1206 printk("== power state %d ==\n", i);
1207 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1208 }
1209}
1210
1211static int radeon_pm_init_dpm(struct radeon_device *rdev)
1212{
1213 int ret;
1214
1cd8b21a 1215 /* default to balanced state */
edcaa5b1
AD		 1216 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1217 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1cd8b21a 1218 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
da321c8a
AD		 1219 rdev->pm.default_sclk = rdev->clock.default_sclk;
1220 rdev->pm.default_mclk = rdev->clock.default_mclk;
1221 rdev->pm.current_sclk = rdev->clock.default_sclk;
1222 rdev->pm.current_mclk = rdev->clock.default_mclk;
1223 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1224
1225 if (rdev->bios && rdev->is_atom_bios)
1226 radeon_atombios_get_power_modes(rdev);
1227 else
1228 return -EINVAL;
1229
1230 /* set up the internal thermal sensor if applicable */
1231 ret = radeon_hwmon_init(rdev);
1232 if (ret)
1233 return ret;
1234
1235 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1236 mutex_lock(&rdev->pm.mutex);
1237 radeon_dpm_init(rdev);
1238 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
033a37df
AD		 1239 if (radeon_dpm == 1)
1240 radeon_dpm_print_power_states(rdev);
da321c8a
AD		 1241 radeon_dpm_setup_asic(rdev);
1242 ret = radeon_dpm_enable(rdev);
1243 mutex_unlock(&rdev->pm.mutex);
e14cd2bb
AD		 1244 if (ret)
1245 goto dpm_failed;
da321c8a 1246 rdev->pm.dpm_enabled = true;
da321c8a 1247
bb5abf9f
AD		 1248 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1249 if (ret)
1250 DRM_ERROR("failed to create device file for dpm state\n");
1251 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1252 if (ret)
1253 DRM_ERROR("failed to create device file for dpm state\n");
1254 /* XXX: these are noops for dpm but are here for backwards compat */
1255 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1256 if (ret)
1257 DRM_ERROR("failed to create device file for power profile\n");
1258 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1259 if (ret)
1260 DRM_ERROR("failed to create device file for power method\n");
1316b792 1261
bb5abf9f
AD		 1262 if (radeon_debugfs_pm_init(rdev)) {
1263 DRM_ERROR("Failed to register debugfs file for dpm!\n");
da321c8a
AD		 1264 }
1265
bb5abf9f
AD		 1266 DRM_INFO("radeon: dpm initialized\n");
1267
da321c8a 1268 return 0;
e14cd2bb
AD		 1269
1270dpm_failed:
1271 rdev->pm.dpm_enabled = false;
1272 if ((rdev->family >= CHIP_BARTS) &&
1273 (rdev->family <= CHIP_CAYMAN) &&
1274 rdev->mc_fw) {
1275 if (rdev->pm.default_vddc)
1276 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1277 SET_VOLTAGE_TYPE_ASIC_VDDC);
1278 if (rdev->pm.default_vddci)
1279 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1280 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1281 if (rdev->pm.default_sclk)
1282 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1283 if (rdev->pm.default_mclk)
1284 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1285 }
1286 DRM_ERROR("radeon: dpm initialization failed\n");
1287 return ret;
da321c8a
AD		 1288}
1289
1290int radeon_pm_init(struct radeon_device *rdev)
1291{
1292 /* enable dpm on rv6xx+ */
1293 switch (rdev->family) {
4a6369e9
AD		 1294 case CHIP_RV610:
1295 case CHIP_RV630:
1296 case CHIP_RV620:
1297 case CHIP_RV635:
1298 case CHIP_RV670:
9d67006e
AD		 1299 case CHIP_RS780:
1300 case CHIP_RS880:
76e6dcec 1301 case CHIP_RV770:
8a53fa23 1302 /* DPM requires the RLC, RV770+ dGPU requires SMC */
761bfb99
AD		 1303 if (!rdev->rlc_fw)
1304 rdev->pm.pm_method = PM_METHOD_PROFILE;
8a53fa23
AD		 1305 else if ((rdev->family >= CHIP_RV770) &&
1306 (!(rdev->flags & RADEON_IS_IGP)) &&
1307 (!rdev->smc_fw))
1308 rdev->pm.pm_method = PM_METHOD_PROFILE;
761bfb99 1309 else if (radeon_dpm == 1)
9d67006e
AD		 1310 rdev->pm.pm_method = PM_METHOD_DPM;
1311 else
1312 rdev->pm.pm_method = PM_METHOD_PROFILE;
1313 break;
ab70b1dd
AD		 1314 case CHIP_RV730:
1315 case CHIP_RV710:
1316 case CHIP_RV740:
59f7a2f2
AD		 1317 case CHIP_CEDAR:
1318 case CHIP_REDWOOD:
1319 case CHIP_JUNIPER:
1320 case CHIP_CYPRESS:
1321 case CHIP_HEMLOCK:
5a16f761
AD		 1322 case CHIP_PALM:
1323 case CHIP_SUMO:
1324 case CHIP_SUMO2:
c08abf11
AD		 1325 case CHIP_BARTS:
1326 case CHIP_TURKS:
1327 case CHIP_CAICOS:
8f500af4 1328 case CHIP_CAYMAN:
3a118989 1329 case CHIP_ARUBA:
68bc7785
AD		 1330 case CHIP_TAHITI:
1331 case CHIP_PITCAIRN:
1332 case CHIP_VERDE:
1333 case CHIP_OLAND:
1334 case CHIP_HAINAN:
4f22dde3 1335 case CHIP_BONAIRE:
e308b1d3
AD		 1336 case CHIP_KABINI:
1337 case CHIP_KAVERI:
4f22dde3 1338 case CHIP_HAWAII:
7d032a4b 1339 case CHIP_MULLINS:
5a16f761
AD		 1340 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1341 if (!rdev->rlc_fw)
1342 rdev->pm.pm_method = PM_METHOD_PROFILE;
1343 else if ((rdev->family >= CHIP_RV770) &&
1344 (!(rdev->flags & RADEON_IS_IGP)) &&
1345 (!rdev->smc_fw))
1346 rdev->pm.pm_method = PM_METHOD_PROFILE;
1347 else if (radeon_dpm == 0)
1348 rdev->pm.pm_method = PM_METHOD_PROFILE;
1349 else
1350 rdev->pm.pm_method = PM_METHOD_DPM;
1351 break;
da321c8a
AD		 1352 default:
1353 /* default to profile method */
1354 rdev->pm.pm_method = PM_METHOD_PROFILE;
1355 break;
1356 }
1357
1358 if (rdev->pm.pm_method == PM_METHOD_DPM)
1359 return radeon_pm_init_dpm(rdev);
1360 else
1361 return radeon_pm_init_old(rdev);
1362}
1363
914a8987
AD		 1364int radeon_pm_late_init(struct radeon_device *rdev)
1365{
1366 int ret = 0;
1367
1368 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1369 mutex_lock(&rdev->pm.mutex);
1370 ret = radeon_dpm_late_enable(rdev);
1371 mutex_unlock(&rdev->pm.mutex);
1372 }
1373 return ret;
1374}
1375
da321c8a 1376static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1377{
ce8f5370 1378 if (rdev->pm.num_power_states > 1) {
a424816f 1379 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1380 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1381 rdev->pm.profile = PM_PROFILE_DEFAULT;
1382 radeon_pm_update_profile(rdev);
1383 radeon_pm_set_clocks(rdev);
1384 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1385 /* reset default clocks */
1386 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1387 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1388 radeon_pm_set_clocks(rdev);
1389 }
a424816f 1390 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1391
1392 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1393
ce8f5370
AD		 1394 device_remove_file(rdev->dev, &dev_attr_power_profile);
1395 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1396 }
a424816f 1397
cb3e4e7c 1398 radeon_hwmon_fini(rdev);
9c244878 1399 kfree(rdev->pm.power_state);
29fb52ca
AD		 1400}
1401
da321c8a
AD		 1402static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1403{
1404 if (rdev->pm.num_power_states > 1) {
1405 mutex_lock(&rdev->pm.mutex);
1406 radeon_dpm_disable(rdev);
1407 mutex_unlock(&rdev->pm.mutex);
1408
1409 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
70d01a5e 1410 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
da321c8a
AD		 1411 /* XXX backwards compat */
1412 device_remove_file(rdev->dev, &dev_attr_power_profile);
1413 device_remove_file(rdev->dev, &dev_attr_power_method);
1414 }
1415 radeon_dpm_fini(rdev);
1416
cb3e4e7c 1417 radeon_hwmon_fini(rdev);
9c244878 1418 kfree(rdev->pm.power_state);
da321c8a
AD		 1419}
1420
1421void radeon_pm_fini(struct radeon_device *rdev)
1422{
1423 if (rdev->pm.pm_method == PM_METHOD_DPM)
1424 radeon_pm_fini_dpm(rdev);
1425 else
1426 radeon_pm_fini_old(rdev);
1427}
1428
1429static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1430{
1431 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1432 struct drm_crtc *crtc;
c913e23a 1433 struct radeon_crtc *radeon_crtc;
c913e23a 1434
ce8f5370
AD		 1435 if (rdev->pm.num_power_states < 2)
1436 return;
1437
c913e23a
RM		 1438 mutex_lock(&rdev->pm.mutex);
1439
1440 rdev->pm.active_crtcs = 0;
a48b9b4e 1441 rdev->pm.active_crtc_count = 0;
3ed9a335
AD		 1442 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1443 list_for_each_entry(crtc,
1444 &ddev->mode_config.crtc_list, head) {
1445 radeon_crtc = to_radeon_crtc(crtc);
1446 if (radeon_crtc->enabled) {
1447 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1448 rdev->pm.active_crtc_count++;
1449 }
c913e23a
RM		 1450 }
1451 }
1452
ce8f5370
AD		 1453 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1454 radeon_pm_update_profile(rdev);
1455 radeon_pm_set_clocks(rdev);
1456 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1457 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1458 if (rdev->pm.active_crtc_count > 1) {
1459 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1460 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1461
1462 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1463 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1464 radeon_pm_get_dynpm_state(rdev);
1465 radeon_pm_set_clocks(rdev);
1466
d9fdaafb 1467 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1468 }
1469 } else if (rdev->pm.active_crtc_count == 1) {
1470 /* TODO: Increase clocks if needed for current mode */
1471
1472 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1473 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1474 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1475 radeon_pm_get_dynpm_state(rdev);
1476 radeon_pm_set_clocks(rdev);
1477
32c87fca
TH		 1478 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1479 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1480 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1481 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1482 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1483 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1484 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1485 }
1486 } else { /* count == 0 */
1487 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1488 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1489
1490 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1491 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1492 radeon_pm_get_dynpm_state(rdev);
1493 radeon_pm_set_clocks(rdev);
1494 }
1495 }
c913e23a 1496 }
c913e23a 1497 }
73a6d3fc
RM		 1498
1499 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1500}
1501
da321c8a
AD		 1502static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1503{
1504 struct drm_device *ddev = rdev->ddev;
1505 struct drm_crtc *crtc;
1506 struct radeon_crtc *radeon_crtc;
1507
6c7bccea
AD		 1508 if (!rdev->pm.dpm_enabled)
1509 return;
1510
da321c8a
AD		 1511 mutex_lock(&rdev->pm.mutex);
1512
5ca302f7 1513 /* update active crtc counts */
da321c8a
AD		 1514 rdev->pm.dpm.new_active_crtcs = 0;
1515 rdev->pm.dpm.new_active_crtc_count = 0;
3ed9a335
AD		 1516 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1517 list_for_each_entry(crtc,
1518 &ddev->mode_config.crtc_list, head) {
1519 radeon_crtc = to_radeon_crtc(crtc);
1520 if (crtc->enabled) {
1521 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1522 rdev->pm.dpm.new_active_crtc_count++;
1523 }
da321c8a
AD		 1524 }
1525 }
1526
5ca302f7
AD		 1527 /* update battery/ac status */
1528 if (power_supply_is_system_supplied() > 0)
1529 rdev->pm.dpm.ac_power = true;
1530 else
1531 rdev->pm.dpm.ac_power = false;
1532
da321c8a
AD		 1533 radeon_dpm_change_power_state_locked(rdev);
1534
1535 mutex_unlock(&rdev->pm.mutex);
8a227555 1536
da321c8a
AD		 1537}
1538
1539void radeon_pm_compute_clocks(struct radeon_device *rdev)
1540{
1541 if (rdev->pm.pm_method == PM_METHOD_DPM)
1542 radeon_pm_compute_clocks_dpm(rdev);
1543 else
1544 radeon_pm_compute_clocks_old(rdev);
1545}
1546
ce8f5370 1547static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1548{
75fa0b08 1549 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1550 bool in_vbl = true;
1551
75fa0b08
MK		 1552 /* Iterate over all active crtc's. All crtc's must be in vblank,
1553 * otherwise return in_vbl == false.
1554 */
1555 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1556 if (rdev->pm.active_crtcs & (1 << crtc)) {
abca9e45 1557 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
f5a80209 1558 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
3d3cbd84 1559 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
f735261b
DA		 1560 in_vbl = false;
1561 }
1562 }
f81f2024
MG		 1563
1564 return in_vbl;
1565}
1566
ce8f5370 1567static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1568{
1569 u32 stat_crtc = 0;
1570 bool in_vbl = radeon_pm_in_vbl(rdev);
1571
f735261b 1572 if (in_vbl == false)
d9fdaafb 1573 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1574 finish ? "exit" : "entry");
f735261b
DA		 1575 return in_vbl;
1576}
c913e23a 1577
ce8f5370 1578static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1579{
1580 struct radeon_device *rdev;
d9932a32 1581 int resched;
c913e23a 1582 rdev = container_of(work, struct radeon_device,
ce8f5370 1583 pm.dynpm_idle_work.work);
c913e23a 1584
d9932a32 1585 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1586 mutex_lock(&rdev->pm.mutex);
ce8f5370 1587 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1588 int not_processed = 0;
7465280c
AD		 1589 int i;
1590
7465280c 1591 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1592 struct radeon_ring *ring = &rdev->ring[i];
1593
1594 if (ring->ready) {
1595 not_processed += radeon_fence_count_emitted(rdev, i);
1596 if (not_processed >= 3)
1597 break;
1598 }
c913e23a 1599 }
c913e23a
RM		 1600
1601 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1602 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1603 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1604 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1605 rdev->pm.dynpm_can_upclock) {
1606 rdev->pm.dynpm_planned_action =
1607 DYNPM_ACTION_UPCLOCK;
1608 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1609 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1610 }
1611 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1612 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1613 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1614 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1615 rdev->pm.dynpm_can_downclock) {
1616 rdev->pm.dynpm_planned_action =
1617 DYNPM_ACTION_DOWNCLOCK;
1618 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1619 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1620 }
1621 }
1622
d7311171
AD		 1623 /* Note, radeon_pm_set_clocks is called with static_switch set
1624 * to false since we want to wait for vbl to avoid flicker.
1625 */
ce8f5370
AD		 1626 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1627 jiffies > rdev->pm.dynpm_action_timeout) {
1628 radeon_pm_get_dynpm_state(rdev);
1629 radeon_pm_set_clocks(rdev);
c913e23a 1630 }
3f53eb6f 1631
32c87fca
TH		 1632 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1633 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1634 }
1635 mutex_unlock(&rdev->pm.mutex);
d9932a32 1636 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1637}
1638
7433874e
RM		 1639/*
1640 * Debugfs info
1641 */
1642#if defined(CONFIG_DEBUG_FS)
1643
1644static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1645{
1646 struct drm_info_node *node = (struct drm_info_node *) m->private;
1647 struct drm_device *dev = node->minor->dev;
1648 struct radeon_device *rdev = dev->dev_private;
4f2f2039 1649 struct drm_device *ddev = rdev->ddev;
7433874e 1650
4f2f2039
AD		 1651 if ((rdev->flags & RADEON_IS_PX) &&
1652 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1653 seq_printf(m, "PX asic powered off\n");
1654 } else if (rdev->pm.dpm_enabled) {
1316b792
AD		 1655 mutex_lock(&rdev->pm.mutex);
1656 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1657 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1658 else
71375929 1659 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1660 mutex_unlock(&rdev->pm.mutex);
1661 } else {
1662 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1663 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1664 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1665 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1666 else
1667 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1668 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1669 if (rdev->asic->pm.get_memory_clock)
1670 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1671 if (rdev->pm.current_vddc)
1672 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1673 if (rdev->asic->pm.get_pcie_lanes)
1674 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1675 }
7433874e
RM		 1676
1677 return 0;
1678}
1679
1680static struct drm_info_list radeon_pm_info_list[] = {
1681 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1682};
1683#endif
1684
c913e23a 1685static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1686{
1687#if defined(CONFIG_DEBUG_FS)
1688 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1689#else
1690 return 0;
1691#endif
1692}
Linux kernel - Deliverables
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