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drm/radeon: rework fence handling, drop fence list v7
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370
AD		 27#ifdef CONFIG_ACPI
28#include <linux/acpi.h>
29#endif
30#include <linux/power_supply.h>
21a8122a
AD		 31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h>
7433874e 33
c913e23a
RM		 34#define RADEON_IDLE_LOOP_MS 100
35#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 36#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 37#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 38
f712d0c7
RM		 39static const char *radeon_pm_state_type_name[5] = {
40 "Default",
41 "Powersave",
42 "Battery",
43 "Balanced",
44 "Performance",
45};
46
ce8f5370 47static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 48static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 49static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51static void radeon_pm_update_profile(struct radeon_device *rdev);
52static void radeon_pm_set_clocks(struct radeon_device *rdev);
53
54#define ACPI_AC_CLASS "ac_adapter"
55
a4c9e2ee
AD		 56int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
58 int instance)
59{
60 int i;
61 int found_instance = -1;
62
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
65 found_instance++;
66 if (found_instance == instance)
67 return i;
68 }
69 }
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
72}
73
ce8f5370
AD		 74#ifdef CONFIG_ACPI
75static int radeon_acpi_event(struct notifier_block *nb,
76 unsigned long val,
77 void *data)
78{
79 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
80 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
81
82 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
83 if (power_supply_is_system_supplied() > 0)
d9fdaafb 84 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 85 else
d9fdaafb 86 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 87
88 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96 }
97
98 return NOTIFY_OK;
99}
100#endif
101
102static void radeon_pm_update_profile(struct radeon_device *rdev)
103{
104 switch (rdev->pm.profile) {
105 case PM_PROFILE_DEFAULT:
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
107 break;
108 case PM_PROFILE_AUTO:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
112 else
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
114 } else {
115 if (rdev->pm.active_crtc_count > 1)
c9e75b21 116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 117 else
c9e75b21 118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 119 }
120 break;
121 case PM_PROFILE_LOW:
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
124 else
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
126 break;
c9e75b21
AD		 127 case PM_PROFILE_MID:
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
130 else
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
132 break;
ce8f5370
AD		 133 case PM_PROFILE_HIGH:
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
136 else
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
138 break;
139 }
140
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
146 } else {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
151 }
152}
c913e23a 153
5876dd24
MG		 154static void radeon_unmap_vram_bos(struct radeon_device *rdev)
155{
156 struct radeon_bo *bo, *n;
157
158 if (list_empty(&rdev->gem.objects))
159 return;
160
161 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
163 ttm_bo_unmap_virtual(&bo->tbo);
164 }
5876dd24
MG		 165}
166
ce8f5370 167static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 168{
ce8f5370
AD		 169 if (rdev->pm.active_crtcs) {
170 rdev->pm.vblank_sync = false;
171 wait_event_timeout(
172 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
174 }
175}
176
177static void radeon_set_power_state(struct radeon_device *rdev)
178{
179 u32 sclk, mclk;
92645879 180 bool misc_after = false;
ce8f5370
AD		 181
182 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
183 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
184 return;
185
186 if (radeon_gui_idle(rdev)) {
187 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
188 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 189 if (sclk > rdev->pm.default_sclk)
190 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 191
192 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
193 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
ce8f5370 196
92645879
AD		 197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
ce8f5370 200
92645879 201 radeon_sync_with_vblank(rdev);
ce8f5370 202
92645879 203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 204 if (!radeon_pm_in_vbl(rdev))
205 return;
92645879 206 }
ce8f5370 207
92645879 208 radeon_pm_prepare(rdev);
ce8f5370 209
92645879
AD		 210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 221 }
222
223 /* set memory clock */
798bcf73 224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
d9fdaafb 229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 230 }
2aba631c 231
92645879
AD		 232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
ce8f5370
AD		 238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
d9fdaafb 241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 242}
243
244static void radeon_pm_set_clocks(struct radeon_device *rdev)
245{
246 int i;
c37d230a 247
4e186b2d
AD		 248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
612e06ce
MG		 253 mutex_lock(&rdev->ddev->struct_mutex);
254 mutex_lock(&rdev->vram_mutex);
d6999bc7 255 mutex_lock(&rdev->ring_lock);
4f3218cb
AD		 256
257 /* gui idle int has issues on older chips it seems */
258 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 259 if (rdev->irq.installed) {
260 /* wait for GPU idle */
261 rdev->pm.gui_idle = false;
262 rdev->irq.gui_idle = true;
263 radeon_irq_set(rdev);
264 wait_event_interruptible_timeout(
265 rdev->irq.idle_queue, rdev->pm.gui_idle,
266 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
267 rdev->irq.gui_idle = false;
268 radeon_irq_set(rdev);
269 }
01434b4b 270 } else {
e32eb50d
CK		 271 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
272 if (ring->ready) {
ce8f5370 273 struct radeon_fence *fence;
e32eb50d
CK		 274 radeon_ring_alloc(rdev, ring, 64);
275 radeon_fence_create(rdev, &fence, radeon_ring_index(rdev, ring));
ce8f5370 276 radeon_fence_emit(rdev, fence);
e32eb50d 277 radeon_ring_commit(rdev, ring);
ce8f5370
AD		 278 radeon_fence_wait(fence, false);
279 radeon_fence_unref(&fence);
280 }
4f3218cb 281 }
5876dd24
MG		 282 radeon_unmap_vram_bos(rdev);
283
ce8f5370 284 if (rdev->irq.installed) {
2aba631c
MG		 285 for (i = 0; i < rdev->num_crtc; i++) {
286 if (rdev->pm.active_crtcs & (1 << i)) {
287 rdev->pm.req_vblank |= (1 << i);
288 drm_vblank_get(rdev->ddev, i);
289 }
290 }
291 }
539d2418 292
ce8f5370 293 radeon_set_power_state(rdev);
2aba631c 294
ce8f5370 295 if (rdev->irq.installed) {
2aba631c
MG		 296 for (i = 0; i < rdev->num_crtc; i++) {
297 if (rdev->pm.req_vblank & (1 << i)) {
298 rdev->pm.req_vblank &= ~(1 << i);
299 drm_vblank_put(rdev->ddev, i);
300 }
301 }
302 }
5876dd24 303
a424816f
AD		 304 /* update display watermarks based on new power state */
305 radeon_update_bandwidth_info(rdev);
306 if (rdev->pm.active_crtc_count)
307 radeon_bandwidth_update(rdev);
308
ce8f5370 309 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 310
d6999bc7 311 mutex_unlock(&rdev->ring_lock);
612e06ce
MG		 312 mutex_unlock(&rdev->vram_mutex);
313 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 314}
315
f712d0c7
RM		 316static void radeon_pm_print_states(struct radeon_device *rdev)
317{
318 int i, j;
319 struct radeon_power_state *power_state;
320 struct radeon_pm_clock_info *clock_info;
321
d9fdaafb 322 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 323 for (i = 0; i < rdev->pm.num_power_states; i++) {
324 power_state = &rdev->pm.power_state[i];
d9fdaafb 325 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 326 radeon_pm_state_type_name[power_state->type]);
327 if (i == rdev->pm.default_power_state_index)
d9fdaafb 328 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 329 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 330 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 331 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 332 DRM_DEBUG_DRIVER("\tSingle display only\n");
333 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 334 for (j = 0; j < power_state->num_clock_modes; j++) {
335 clock_info = &(power_state->clock_info[j]);
336 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 337 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 338 j,
339 clock_info->sclk * 10,
340 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
341 else
d9fdaafb 342 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 343 j,
344 clock_info->sclk * 10,
345 clock_info->mclk * 10,
346 clock_info->voltage.voltage,
347 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
348 }
349 }
350}
351
ce8f5370
AD		 352static ssize_t radeon_get_pm_profile(struct device *dev,
353 struct device_attribute *attr,
354 char *buf)
a424816f
AD		 355{
356 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
357 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 358 int cp = rdev->pm.profile;
a424816f 359
ce8f5370
AD		 360 return snprintf(buf, PAGE_SIZE, "%s\n",
361 (cp == PM_PROFILE_AUTO) ? "auto" :
362 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 363 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 364 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 365}
366
ce8f5370
AD		 367static ssize_t radeon_set_pm_profile(struct device *dev,
368 struct device_attribute *attr,
369 const char *buf,
370 size_t count)
a424816f
AD		 371{
372 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
373 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 374
375 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 376 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
377 if (strncmp("default", buf, strlen("default")) == 0)
378 rdev->pm.profile = PM_PROFILE_DEFAULT;
379 else if (strncmp("auto", buf, strlen("auto")) == 0)
380 rdev->pm.profile = PM_PROFILE_AUTO;
381 else if (strncmp("low", buf, strlen("low")) == 0)
382 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 383 else if (strncmp("mid", buf, strlen("mid")) == 0)
384 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 385 else if (strncmp("high", buf, strlen("high")) == 0)
386 rdev->pm.profile = PM_PROFILE_HIGH;
387 else {
1783e4bf 388 count = -EINVAL;
ce8f5370 389 goto fail;
a424816f 390 }
ce8f5370
AD		 391 radeon_pm_update_profile(rdev);
392 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 393 } else
394 count = -EINVAL;
395
ce8f5370 396fail:
a424816f
AD		 397 mutex_unlock(&rdev->pm.mutex);
398
399 return count;
400}
401
ce8f5370
AD		 402static ssize_t radeon_get_pm_method(struct device *dev,
403 struct device_attribute *attr,
404 char *buf)
a424816f
AD		 405{
406 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
407 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 408 int pm = rdev->pm.pm_method;
a424816f
AD		 409
410 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 411 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 412}
413
ce8f5370
AD		 414static ssize_t radeon_set_pm_method(struct device *dev,
415 struct device_attribute *attr,
416 const char *buf,
417 size_t count)
a424816f
AD		 418{
419 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
420 struct radeon_device *rdev = ddev->dev_private;
a424816f 421
ce8f5370
AD		 422
423 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 424 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 425 rdev->pm.pm_method = PM_METHOD_DYNPM;
426 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
427 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 428 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 429 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
430 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 431 /* disable dynpm */
432 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
433 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 434 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 435 mutex_unlock(&rdev->pm.mutex);
32c87fca 436 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 437 } else {
1783e4bf 438 count = -EINVAL;
ce8f5370
AD		 439 goto fail;
440 }
441 radeon_pm_compute_clocks(rdev);
442fail:
a424816f
AD		 443 return count;
444}
445
ce8f5370
AD		 446static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
447static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 448
21a8122a
AD		 449static ssize_t radeon_hwmon_show_temp(struct device *dev,
450 struct device_attribute *attr,
451 char *buf)
452{
453 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
454 struct radeon_device *rdev = ddev->dev_private;
20d391d7 455 int temp;
21a8122a
AD		 456
457 switch (rdev->pm.int_thermal_type) {
458 case THERMAL_TYPE_RV6XX:
459 temp = rv6xx_get_temp(rdev);
460 break;
461 case THERMAL_TYPE_RV770:
462 temp = rv770_get_temp(rdev);
463 break;
464 case THERMAL_TYPE_EVERGREEN:
4fddba1f 465 case THERMAL_TYPE_NI:
21a8122a
AD		 466 temp = evergreen_get_temp(rdev);
467 break;
e33df25f
AD		 468 case THERMAL_TYPE_SUMO:
469 temp = sumo_get_temp(rdev);
470 break;
1bd47d2e
AD		 471 case THERMAL_TYPE_SI:
472 temp = si_get_temp(rdev);
473 break;
21a8122a
AD		 474 default:
475 temp = 0;
476 break;
477 }
478
479 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
480}
481
482static ssize_t radeon_hwmon_show_name(struct device *dev,
483 struct device_attribute *attr,
484 char *buf)
485{
486 return sprintf(buf, "radeon\n");
487}
488
489static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
490static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
491
492static struct attribute *hwmon_attributes[] = {
493 &sensor_dev_attr_temp1_input.dev_attr.attr,
494 &sensor_dev_attr_name.dev_attr.attr,
495 NULL
496};
497
498static const struct attribute_group hwmon_attrgroup = {
499 .attrs = hwmon_attributes,
500};
501
0d18abed 502static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 503{
0d18abed 504 int err = 0;
21a8122a
AD		 505
506 rdev->pm.int_hwmon_dev = NULL;
507
508 switch (rdev->pm.int_thermal_type) {
509 case THERMAL_TYPE_RV6XX:
510 case THERMAL_TYPE_RV770:
511 case THERMAL_TYPE_EVERGREEN:
457558ed 512 case THERMAL_TYPE_NI:
e33df25f 513 case THERMAL_TYPE_SUMO:
1bd47d2e 514 case THERMAL_TYPE_SI:
5d7486c7
AD		 515 /* No support for TN yet */
516 if (rdev->family == CHIP_ARUBA)
517 return err;
21a8122a 518 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 519 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
520 err = PTR_ERR(rdev->pm.int_hwmon_dev);
521 dev_err(rdev->dev,
522 "Unable to register hwmon device: %d\n", err);
523 break;
524 }
21a8122a
AD		 525 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
526 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
527 &hwmon_attrgroup);
0d18abed
DC		 528 if (err) {
529 dev_err(rdev->dev,
530 "Unable to create hwmon sysfs file: %d\n", err);
531 hwmon_device_unregister(rdev->dev);
532 }
21a8122a
AD		 533 break;
534 default:
535 break;
536 }
0d18abed
DC		 537
538 return err;
21a8122a
AD		 539}
540
541static void radeon_hwmon_fini(struct radeon_device *rdev)
542{
543 if (rdev->pm.int_hwmon_dev) {
544 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
545 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
546 }
547}
548
ce8f5370 549void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 550{
ce8f5370 551 mutex_lock(&rdev->pm.mutex);
3f53eb6f 552 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 553 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
554 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 555 }
ce8f5370 556 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 557
558 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 559}
560
ce8f5370 561void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 562{
ed18a360
AD		 563 /* set up the default clocks if the MC ucode is loaded */
564 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
565 if (rdev->pm.default_vddc)
8a83ec5e
AD		 566 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
567 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 568 if (rdev->pm.default_vddci)
569 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
570 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 571 if (rdev->pm.default_sclk)
572 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
573 if (rdev->pm.default_mclk)
574 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
575 }
f8ed8b4c
AD		 576 /* asic init will reset the default power state */
577 mutex_lock(&rdev->pm.mutex);
578 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
579 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 580 rdev->pm.current_sclk = rdev->pm.default_sclk;
581 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 582 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 583 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 584 if (rdev->pm.pm_method == PM_METHOD_DYNPM
585 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
586 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 587 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
588 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 589 }
f8ed8b4c 590 mutex_unlock(&rdev->pm.mutex);
ce8f5370 591 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 592}
593
7433874e
RM		 594int radeon_pm_init(struct radeon_device *rdev)
595{
26481fb1 596 int ret;
0d18abed 597
ce8f5370
AD		 598 /* default to profile method */
599 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 600 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 601 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
602 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
603 rdev->pm.dynpm_can_upclock = true;
604 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 605 rdev->pm.default_sclk = rdev->clock.default_sclk;
606 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 607 rdev->pm.current_sclk = rdev->clock.default_sclk;
608 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 609 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 610
56278a8e
AD		 611 if (rdev->bios) {
612 if (rdev->is_atom_bios)
613 radeon_atombios_get_power_modes(rdev);
614 else
615 radeon_combios_get_power_modes(rdev);
f712d0c7 616 radeon_pm_print_states(rdev);
ce8f5370 617 radeon_pm_init_profile(rdev);
ed18a360
AD		 618 /* set up the default clocks if the MC ucode is loaded */
619 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
620 if (rdev->pm.default_vddc)
8a83ec5e
AD		 621 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
622 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 623 if (rdev->pm.default_vddci)
624 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
625 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 626 if (rdev->pm.default_sclk)
627 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
628 if (rdev->pm.default_mclk)
629 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
630 }
56278a8e
AD		 631 }
632
21a8122a 633 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 634 ret = radeon_hwmon_init(rdev);
635 if (ret)
636 return ret;
32c87fca
TH		 637
638 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
639
ce8f5370 640 if (rdev->pm.num_power_states > 1) {
ce8f5370 641 /* where's the best place to put these? */
26481fb1
DA		 642 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
643 if (ret)
644 DRM_ERROR("failed to create device file for power profile\n");
645 ret = device_create_file(rdev->dev, &dev_attr_power_method);
646 if (ret)
647 DRM_ERROR("failed to create device file for power method\n");
a424816f 648
ce8f5370
AD		 649#ifdef CONFIG_ACPI
650 rdev->acpi_nb.notifier_call = radeon_acpi_event;
651 register_acpi_notifier(&rdev->acpi_nb);
652#endif
ce8f5370
AD		 653 if (radeon_debugfs_pm_init(rdev)) {
654 DRM_ERROR("Failed to register debugfs file for PM!\n");
655 }
c913e23a 656
ce8f5370
AD		 657 DRM_INFO("radeon: power management initialized\n");
658 }
c913e23a 659
7433874e
RM		 660 return 0;
661}
662
29fb52ca
AD		 663void radeon_pm_fini(struct radeon_device *rdev)
664{
ce8f5370 665 if (rdev->pm.num_power_states > 1) {
a424816f 666 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 667 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
668 rdev->pm.profile = PM_PROFILE_DEFAULT;
669 radeon_pm_update_profile(rdev);
670 radeon_pm_set_clocks(rdev);
671 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 672 /* reset default clocks */
673 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
674 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
675 radeon_pm_set_clocks(rdev);
676 }
a424816f 677 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 678
679 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 680
ce8f5370
AD		 681 device_remove_file(rdev->dev, &dev_attr_power_profile);
682 device_remove_file(rdev->dev, &dev_attr_power_method);
683#ifdef CONFIG_ACPI
684 unregister_acpi_notifier(&rdev->acpi_nb);
685#endif
686 }
a424816f 687
0975b162
AD		 688 if (rdev->pm.power_state)
689 kfree(rdev->pm.power_state);
690
21a8122a 691 radeon_hwmon_fini(rdev);
29fb52ca
AD		 692}
693
c913e23a
RM		 694void radeon_pm_compute_clocks(struct radeon_device *rdev)
695{
696 struct drm_device *ddev = rdev->ddev;
a48b9b4e 697 struct drm_crtc *crtc;
c913e23a 698 struct radeon_crtc *radeon_crtc;
c913e23a 699
ce8f5370
AD		 700 if (rdev->pm.num_power_states < 2)
701 return;
702
c913e23a
RM		 703 mutex_lock(&rdev->pm.mutex);
704
705 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 706 rdev->pm.active_crtc_count = 0;
707 list_for_each_entry(crtc,
708 &ddev->mode_config.crtc_list, head) {
709 radeon_crtc = to_radeon_crtc(crtc);
710 if (radeon_crtc->enabled) {
c913e23a 711 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 712 rdev->pm.active_crtc_count++;
c913e23a
RM		 713 }
714 }
715
ce8f5370
AD		 716 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
717 radeon_pm_update_profile(rdev);
718 radeon_pm_set_clocks(rdev);
719 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
720 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
721 if (rdev->pm.active_crtc_count > 1) {
722 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
723 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
724
725 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
726 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
727 radeon_pm_get_dynpm_state(rdev);
728 radeon_pm_set_clocks(rdev);
729
d9fdaafb 730 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 731 }
732 } else if (rdev->pm.active_crtc_count == 1) {
733 /* TODO: Increase clocks if needed for current mode */
734
735 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
736 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
737 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
738 radeon_pm_get_dynpm_state(rdev);
739 radeon_pm_set_clocks(rdev);
740
32c87fca
TH		 741 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
742 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 743 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
744 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 745 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
746 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 747 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 748 }
749 } else { /* count == 0 */
750 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
751 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
752
753 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
754 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
755 radeon_pm_get_dynpm_state(rdev);
756 radeon_pm_set_clocks(rdev);
757 }
758 }
c913e23a 759 }
c913e23a 760 }
73a6d3fc
RM		 761
762 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 763}
764
ce8f5370 765static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 766{
75fa0b08 767 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 768 bool in_vbl = true;
769
75fa0b08
MK		 770 /* Iterate over all active crtc's. All crtc's must be in vblank,
771 * otherwise return in_vbl == false.
772 */
773 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
774 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 775 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
776 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
777 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 778 in_vbl = false;
779 }
780 }
f81f2024
MG		 781
782 return in_vbl;
783}
784
ce8f5370 785static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 786{
787 u32 stat_crtc = 0;
788 bool in_vbl = radeon_pm_in_vbl(rdev);
789
f735261b 790 if (in_vbl == false)
d9fdaafb 791 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 792 finish ? "exit" : "entry");
f735261b
DA		 793 return in_vbl;
794}
c913e23a 795
ce8f5370 796static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 797{
798 struct radeon_device *rdev;
d9932a32 799 int resched;
c913e23a 800 rdev = container_of(work, struct radeon_device,
ce8f5370 801 pm.dynpm_idle_work.work);
c913e23a 802
d9932a32 803 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 804 mutex_lock(&rdev->pm.mutex);
ce8f5370 805 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 806 int not_processed = 0;
7465280c
AD		 807 int i;
808
7465280c 809 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
47492a23 810 not_processed += radeon_fence_count_emitted(rdev, i);
7465280c
AD		 811 if (not_processed >= 3)
812 break;
c913e23a 813 }
c913e23a
RM		 814
815 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 816 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
817 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
818 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
819 rdev->pm.dynpm_can_upclock) {
820 rdev->pm.dynpm_planned_action =
821 DYNPM_ACTION_UPCLOCK;
822 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 823 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
824 }
825 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 826 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
827 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
828 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
829 rdev->pm.dynpm_can_downclock) {
830 rdev->pm.dynpm_planned_action =
831 DYNPM_ACTION_DOWNCLOCK;
832 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 833 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
834 }
835 }
836
d7311171
AD		 837 /* Note, radeon_pm_set_clocks is called with static_switch set
838 * to false since we want to wait for vbl to avoid flicker.
839 */
ce8f5370
AD		 840 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
841 jiffies > rdev->pm.dynpm_action_timeout) {
842 radeon_pm_get_dynpm_state(rdev);
843 radeon_pm_set_clocks(rdev);
c913e23a 844 }
3f53eb6f 845
32c87fca
TH		 846 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
847 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 848 }
849 mutex_unlock(&rdev->pm.mutex);
d9932a32 850 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 851}
852
7433874e
RM		 853/*
854 * Debugfs info
855 */
856#if defined(CONFIG_DEBUG_FS)
857
858static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
859{
860 struct drm_info_node *node = (struct drm_info_node *) m->private;
861 struct drm_device *dev = node->minor->dev;
862 struct radeon_device *rdev = dev->dev_private;
863
9ace9f7b 864 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 865 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 866 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 867 if (rdev->asic->pm.get_memory_clock)
6234077d 868 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 869 if (rdev->pm.current_vddc)
870 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 871 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 872 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 873
874 return 0;
875}
876
877static struct drm_info_list radeon_pm_info_list[] = {
878 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
879};
880#endif
881
c913e23a 882static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 883{
884#if defined(CONFIG_DEBUG_FS)
885 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
886#else
887 return 0;
888#endif
889}
Linux kernel - Deliverables
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