projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370
AD		 27#ifdef CONFIG_ACPI
28#include <linux/acpi.h>
29#endif
30#include <linux/power_supply.h>
21a8122a
AD		 31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h>
7433874e 33
c913e23a
RM		 34#define RADEON_IDLE_LOOP_MS 100
35#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 36#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 37#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 38
f712d0c7
RM		 39static const char *radeon_pm_state_type_name[5] = {
40 "Default",
41 "Powersave",
42 "Battery",
43 "Balanced",
44 "Performance",
45};
46
ce8f5370 47static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 48static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 49static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51static void radeon_pm_update_profile(struct radeon_device *rdev);
52static void radeon_pm_set_clocks(struct radeon_device *rdev);
53
54#define ACPI_AC_CLASS "ac_adapter"
55
a4c9e2ee
AD		 56int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
58 int instance)
59{
60 int i;
61 int found_instance = -1;
62
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
65 found_instance++;
66 if (found_instance == instance)
67 return i;
68 }
69 }
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
72}
73
ce8f5370
AD		 74#ifdef CONFIG_ACPI
75static int radeon_acpi_event(struct notifier_block *nb,
76 unsigned long val,
77 void *data)
78{
79 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
80 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
81
82 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
83 if (power_supply_is_system_supplied() > 0)
d9fdaafb 84 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 85 else
d9fdaafb 86 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 87
88 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96 }
97
98 return NOTIFY_OK;
99}
100#endif
101
102static void radeon_pm_update_profile(struct radeon_device *rdev)
103{
104 switch (rdev->pm.profile) {
105 case PM_PROFILE_DEFAULT:
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
107 break;
108 case PM_PROFILE_AUTO:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
112 else
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
114 } else {
115 if (rdev->pm.active_crtc_count > 1)
c9e75b21 116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 117 else
c9e75b21 118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 119 }
120 break;
121 case PM_PROFILE_LOW:
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
124 else
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
126 break;
c9e75b21
AD		 127 case PM_PROFILE_MID:
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
130 else
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
132 break;
ce8f5370
AD		 133 case PM_PROFILE_HIGH:
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
136 else
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
138 break;
139 }
140
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
146 } else {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
151 }
152}
c913e23a 153
5876dd24
MG		 154static void radeon_unmap_vram_bos(struct radeon_device *rdev)
155{
156 struct radeon_bo *bo, *n;
157
158 if (list_empty(&rdev->gem.objects))
159 return;
160
161 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
163 ttm_bo_unmap_virtual(&bo->tbo);
164 }
5876dd24
MG		 165}
166
ce8f5370 167static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 168{
ce8f5370
AD		 169 if (rdev->pm.active_crtcs) {
170 rdev->pm.vblank_sync = false;
171 wait_event_timeout(
172 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
174 }
175}
176
177static void radeon_set_power_state(struct radeon_device *rdev)
178{
179 u32 sclk, mclk;
92645879 180 bool misc_after = false;
ce8f5370
AD		 181
182 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
183 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
184 return;
185
186 if (radeon_gui_idle(rdev)) {
187 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
188 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 189 if (sclk > rdev->pm.default_sclk)
190 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 191
192 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
193 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
ce8f5370 196
92645879
AD		 197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
ce8f5370 200
92645879 201 radeon_sync_with_vblank(rdev);
ce8f5370 202
92645879 203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 204 if (!radeon_pm_in_vbl(rdev))
205 return;
92645879 206 }
ce8f5370 207
92645879 208 radeon_pm_prepare(rdev);
ce8f5370 209
92645879
AD		 210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 221 }
222
223 /* set memory clock */
798bcf73 224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
d9fdaafb 229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 230 }
2aba631c 231
92645879
AD		 232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
ce8f5370
AD		 238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
d9fdaafb 241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 242}
243
244static void radeon_pm_set_clocks(struct radeon_device *rdev)
245{
246 int i;
c37d230a 247
4e186b2d
AD		 248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
612e06ce
MG		 253 mutex_lock(&rdev->ddev->struct_mutex);
254 mutex_lock(&rdev->vram_mutex);
d6999bc7 255 mutex_lock(&rdev->ring_lock);
4f3218cb
AD		 256
257 /* gui idle int has issues on older chips it seems */
258 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 259 if (rdev->irq.installed) {
260 /* wait for GPU idle */
261 rdev->pm.gui_idle = false;
262 rdev->irq.gui_idle = true;
263 radeon_irq_set(rdev);
264 wait_event_interruptible_timeout(
265 rdev->irq.idle_queue, rdev->pm.gui_idle,
266 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
267 rdev->irq.gui_idle = false;
268 radeon_irq_set(rdev);
269 }
01434b4b 270 } else {
e32eb50d
CK		 271 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
272 if (ring->ready) {
8a47cc9e 273 radeon_fence_wait_empty_locked(rdev, RADEON_RING_TYPE_GFX_INDEX);
ce8f5370 274 }
4f3218cb 275 }
5876dd24
MG		 276 radeon_unmap_vram_bos(rdev);
277
ce8f5370 278 if (rdev->irq.installed) {
2aba631c
MG		 279 for (i = 0; i < rdev->num_crtc; i++) {
280 if (rdev->pm.active_crtcs & (1 << i)) {
281 rdev->pm.req_vblank |= (1 << i);
282 drm_vblank_get(rdev->ddev, i);
283 }
284 }
285 }
539d2418 286
ce8f5370 287 radeon_set_power_state(rdev);
2aba631c 288
ce8f5370 289 if (rdev->irq.installed) {
2aba631c
MG		 290 for (i = 0; i < rdev->num_crtc; i++) {
291 if (rdev->pm.req_vblank & (1 << i)) {
292 rdev->pm.req_vblank &= ~(1 << i);
293 drm_vblank_put(rdev->ddev, i);
294 }
295 }
296 }
5876dd24 297
a424816f
AD		 298 /* update display watermarks based on new power state */
299 radeon_update_bandwidth_info(rdev);
300 if (rdev->pm.active_crtc_count)
301 radeon_bandwidth_update(rdev);
302
ce8f5370 303 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 304
d6999bc7 305 mutex_unlock(&rdev->ring_lock);
612e06ce
MG		 306 mutex_unlock(&rdev->vram_mutex);
307 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 308}
309
f712d0c7
RM		 310static void radeon_pm_print_states(struct radeon_device *rdev)
311{
312 int i, j;
313 struct radeon_power_state *power_state;
314 struct radeon_pm_clock_info *clock_info;
315
d9fdaafb 316 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 317 for (i = 0; i < rdev->pm.num_power_states; i++) {
318 power_state = &rdev->pm.power_state[i];
d9fdaafb 319 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 320 radeon_pm_state_type_name[power_state->type]);
321 if (i == rdev->pm.default_power_state_index)
d9fdaafb 322 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 323 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 324 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 325 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 326 DRM_DEBUG_DRIVER("\tSingle display only\n");
327 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 328 for (j = 0; j < power_state->num_clock_modes; j++) {
329 clock_info = &(power_state->clock_info[j]);
330 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 331 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 332 j,
333 clock_info->sclk * 10,
334 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
335 else
d9fdaafb 336 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 337 j,
338 clock_info->sclk * 10,
339 clock_info->mclk * 10,
340 clock_info->voltage.voltage,
341 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
342 }
343 }
344}
345
ce8f5370
AD		 346static ssize_t radeon_get_pm_profile(struct device *dev,
347 struct device_attribute *attr,
348 char *buf)
a424816f
AD		 349{
350 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
351 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 352 int cp = rdev->pm.profile;
a424816f 353
ce8f5370
AD		 354 return snprintf(buf, PAGE_SIZE, "%s\n",
355 (cp == PM_PROFILE_AUTO) ? "auto" :
356 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 357 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 358 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 359}
360
ce8f5370
AD		 361static ssize_t radeon_set_pm_profile(struct device *dev,
362 struct device_attribute *attr,
363 const char *buf,
364 size_t count)
a424816f
AD		 365{
366 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
367 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 368
369 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
371 if (strncmp("default", buf, strlen("default")) == 0)
372 rdev->pm.profile = PM_PROFILE_DEFAULT;
373 else if (strncmp("auto", buf, strlen("auto")) == 0)
374 rdev->pm.profile = PM_PROFILE_AUTO;
375 else if (strncmp("low", buf, strlen("low")) == 0)
376 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 377 else if (strncmp("mid", buf, strlen("mid")) == 0)
378 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 379 else if (strncmp("high", buf, strlen("high")) == 0)
380 rdev->pm.profile = PM_PROFILE_HIGH;
381 else {
1783e4bf 382 count = -EINVAL;
ce8f5370 383 goto fail;
a424816f 384 }
ce8f5370
AD		 385 radeon_pm_update_profile(rdev);
386 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 387 } else
388 count = -EINVAL;
389
ce8f5370 390fail:
a424816f
AD		 391 mutex_unlock(&rdev->pm.mutex);
392
393 return count;
394}
395
ce8f5370
AD		 396static ssize_t radeon_get_pm_method(struct device *dev,
397 struct device_attribute *attr,
398 char *buf)
a424816f
AD		 399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 402 int pm = rdev->pm.pm_method;
a424816f
AD		 403
404 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 405 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 406}
407
ce8f5370
AD		 408static ssize_t radeon_set_pm_method(struct device *dev,
409 struct device_attribute *attr,
410 const char *buf,
411 size_t count)
a424816f
AD		 412{
413 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
414 struct radeon_device *rdev = ddev->dev_private;
a424816f 415
ce8f5370
AD		 416
417 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 418 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 419 rdev->pm.pm_method = PM_METHOD_DYNPM;
420 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
421 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 422 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 423 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
424 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 425 /* disable dynpm */
426 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
427 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 428 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 429 mutex_unlock(&rdev->pm.mutex);
32c87fca 430 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 431 } else {
1783e4bf 432 count = -EINVAL;
ce8f5370
AD		 433 goto fail;
434 }
435 radeon_pm_compute_clocks(rdev);
436fail:
a424816f
AD		 437 return count;
438}
439
ce8f5370
AD		 440static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
441static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 442
21a8122a
AD		 443static ssize_t radeon_hwmon_show_temp(struct device *dev,
444 struct device_attribute *attr,
445 char *buf)
446{
447 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
448 struct radeon_device *rdev = ddev->dev_private;
20d391d7 449 int temp;
21a8122a
AD		 450
451 switch (rdev->pm.int_thermal_type) {
452 case THERMAL_TYPE_RV6XX:
453 temp = rv6xx_get_temp(rdev);
454 break;
455 case THERMAL_TYPE_RV770:
456 temp = rv770_get_temp(rdev);
457 break;
458 case THERMAL_TYPE_EVERGREEN:
4fddba1f 459 case THERMAL_TYPE_NI:
21a8122a
AD		 460 temp = evergreen_get_temp(rdev);
461 break;
e33df25f
AD		 462 case THERMAL_TYPE_SUMO:
463 temp = sumo_get_temp(rdev);
464 break;
1bd47d2e
AD		 465 case THERMAL_TYPE_SI:
466 temp = si_get_temp(rdev);
467 break;
21a8122a
AD		 468 default:
469 temp = 0;
470 break;
471 }
472
473 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
474}
475
476static ssize_t radeon_hwmon_show_name(struct device *dev,
477 struct device_attribute *attr,
478 char *buf)
479{
480 return sprintf(buf, "radeon\n");
481}
482
483static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
484static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
485
486static struct attribute *hwmon_attributes[] = {
487 &sensor_dev_attr_temp1_input.dev_attr.attr,
488 &sensor_dev_attr_name.dev_attr.attr,
489 NULL
490};
491
492static const struct attribute_group hwmon_attrgroup = {
493 .attrs = hwmon_attributes,
494};
495
0d18abed 496static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 497{
0d18abed 498 int err = 0;
21a8122a
AD		 499
500 rdev->pm.int_hwmon_dev = NULL;
501
502 switch (rdev->pm.int_thermal_type) {
503 case THERMAL_TYPE_RV6XX:
504 case THERMAL_TYPE_RV770:
505 case THERMAL_TYPE_EVERGREEN:
457558ed 506 case THERMAL_TYPE_NI:
e33df25f 507 case THERMAL_TYPE_SUMO:
1bd47d2e 508 case THERMAL_TYPE_SI:
5d7486c7
AD		 509 /* No support for TN yet */
510 if (rdev->family == CHIP_ARUBA)
511 return err;
21a8122a 512 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 513 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
514 err = PTR_ERR(rdev->pm.int_hwmon_dev);
515 dev_err(rdev->dev,
516 "Unable to register hwmon device: %d\n", err);
517 break;
518 }
21a8122a
AD		 519 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
520 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
521 &hwmon_attrgroup);
0d18abed
DC		 522 if (err) {
523 dev_err(rdev->dev,
524 "Unable to create hwmon sysfs file: %d\n", err);
525 hwmon_device_unregister(rdev->dev);
526 }
21a8122a
AD		 527 break;
528 default:
529 break;
530 }
0d18abed
DC		 531
532 return err;
21a8122a
AD		 533}
534
535static void radeon_hwmon_fini(struct radeon_device *rdev)
536{
537 if (rdev->pm.int_hwmon_dev) {
538 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
539 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
540 }
541}
542
ce8f5370 543void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 544{
ce8f5370 545 mutex_lock(&rdev->pm.mutex);
3f53eb6f 546 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 547 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
548 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 549 }
ce8f5370 550 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 551
552 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 553}
554
ce8f5370 555void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 556{
ed18a360
AD		 557 /* set up the default clocks if the MC ucode is loaded */
558 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
559 if (rdev->pm.default_vddc)
8a83ec5e
AD		 560 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
561 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 562 if (rdev->pm.default_vddci)
563 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
564 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 565 if (rdev->pm.default_sclk)
566 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
567 if (rdev->pm.default_mclk)
568 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
569 }
f8ed8b4c
AD		 570 /* asic init will reset the default power state */
571 mutex_lock(&rdev->pm.mutex);
572 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
573 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 574 rdev->pm.current_sclk = rdev->pm.default_sclk;
575 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 576 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 577 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 578 if (rdev->pm.pm_method == PM_METHOD_DYNPM
579 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
580 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 581 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
582 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 583 }
f8ed8b4c 584 mutex_unlock(&rdev->pm.mutex);
ce8f5370 585 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 586}
587
7433874e
RM		 588int radeon_pm_init(struct radeon_device *rdev)
589{
26481fb1 590 int ret;
0d18abed 591
ce8f5370
AD		 592 /* default to profile method */
593 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 594 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 595 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
596 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
597 rdev->pm.dynpm_can_upclock = true;
598 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 599 rdev->pm.default_sclk = rdev->clock.default_sclk;
600 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 601 rdev->pm.current_sclk = rdev->clock.default_sclk;
602 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 603 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 604
56278a8e
AD		 605 if (rdev->bios) {
606 if (rdev->is_atom_bios)
607 radeon_atombios_get_power_modes(rdev);
608 else
609 radeon_combios_get_power_modes(rdev);
f712d0c7 610 radeon_pm_print_states(rdev);
ce8f5370 611 radeon_pm_init_profile(rdev);
ed18a360
AD		 612 /* set up the default clocks if the MC ucode is loaded */
613 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
614 if (rdev->pm.default_vddc)
8a83ec5e
AD		 615 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
616 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 617 if (rdev->pm.default_vddci)
618 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
619 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 620 if (rdev->pm.default_sclk)
621 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
622 if (rdev->pm.default_mclk)
623 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
624 }
56278a8e
AD		 625 }
626
21a8122a 627 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 628 ret = radeon_hwmon_init(rdev);
629 if (ret)
630 return ret;
32c87fca
TH		 631
632 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
633
ce8f5370 634 if (rdev->pm.num_power_states > 1) {
ce8f5370 635 /* where's the best place to put these? */
26481fb1
DA		 636 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
637 if (ret)
638 DRM_ERROR("failed to create device file for power profile\n");
639 ret = device_create_file(rdev->dev, &dev_attr_power_method);
640 if (ret)
641 DRM_ERROR("failed to create device file for power method\n");
a424816f 642
ce8f5370
AD		 643#ifdef CONFIG_ACPI
644 rdev->acpi_nb.notifier_call = radeon_acpi_event;
645 register_acpi_notifier(&rdev->acpi_nb);
646#endif
ce8f5370
AD		 647 if (radeon_debugfs_pm_init(rdev)) {
648 DRM_ERROR("Failed to register debugfs file for PM!\n");
649 }
c913e23a 650
ce8f5370
AD		 651 DRM_INFO("radeon: power management initialized\n");
652 }
c913e23a 653
7433874e
RM		 654 return 0;
655}
656
29fb52ca
AD		 657void radeon_pm_fini(struct radeon_device *rdev)
658{
ce8f5370 659 if (rdev->pm.num_power_states > 1) {
a424816f 660 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 661 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
662 rdev->pm.profile = PM_PROFILE_DEFAULT;
663 radeon_pm_update_profile(rdev);
664 radeon_pm_set_clocks(rdev);
665 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 666 /* reset default clocks */
667 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
668 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
669 radeon_pm_set_clocks(rdev);
670 }
a424816f 671 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 672
673 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 674
ce8f5370
AD		 675 device_remove_file(rdev->dev, &dev_attr_power_profile);
676 device_remove_file(rdev->dev, &dev_attr_power_method);
677#ifdef CONFIG_ACPI
678 unregister_acpi_notifier(&rdev->acpi_nb);
679#endif
680 }
a424816f 681
0975b162
AD		 682 if (rdev->pm.power_state)
683 kfree(rdev->pm.power_state);
684
21a8122a 685 radeon_hwmon_fini(rdev);
29fb52ca
AD		 686}
687
c913e23a
RM		 688void radeon_pm_compute_clocks(struct radeon_device *rdev)
689{
690 struct drm_device *ddev = rdev->ddev;
a48b9b4e 691 struct drm_crtc *crtc;
c913e23a 692 struct radeon_crtc *radeon_crtc;
c913e23a 693
ce8f5370
AD		 694 if (rdev->pm.num_power_states < 2)
695 return;
696
c913e23a
RM		 697 mutex_lock(&rdev->pm.mutex);
698
699 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 700 rdev->pm.active_crtc_count = 0;
701 list_for_each_entry(crtc,
702 &ddev->mode_config.crtc_list, head) {
703 radeon_crtc = to_radeon_crtc(crtc);
704 if (radeon_crtc->enabled) {
c913e23a 705 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 706 rdev->pm.active_crtc_count++;
c913e23a
RM		 707 }
708 }
709
ce8f5370
AD		 710 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
711 radeon_pm_update_profile(rdev);
712 radeon_pm_set_clocks(rdev);
713 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
714 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
715 if (rdev->pm.active_crtc_count > 1) {
716 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
717 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
718
719 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
720 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
721 radeon_pm_get_dynpm_state(rdev);
722 radeon_pm_set_clocks(rdev);
723
d9fdaafb 724 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 725 }
726 } else if (rdev->pm.active_crtc_count == 1) {
727 /* TODO: Increase clocks if needed for current mode */
728
729 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
730 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
731 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
732 radeon_pm_get_dynpm_state(rdev);
733 radeon_pm_set_clocks(rdev);
734
32c87fca
TH		 735 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
736 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 737 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
738 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 739 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
740 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 741 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 742 }
743 } else { /* count == 0 */
744 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
745 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
746
747 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
748 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
749 radeon_pm_get_dynpm_state(rdev);
750 radeon_pm_set_clocks(rdev);
751 }
752 }
c913e23a 753 }
c913e23a 754 }
73a6d3fc
RM		 755
756 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 757}
758
ce8f5370 759static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 760{
75fa0b08 761 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 762 bool in_vbl = true;
763
75fa0b08
MK		 764 /* Iterate over all active crtc's. All crtc's must be in vblank,
765 * otherwise return in_vbl == false.
766 */
767 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
768 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 769 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
770 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
771 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 772 in_vbl = false;
773 }
774 }
f81f2024
MG		 775
776 return in_vbl;
777}
778
ce8f5370 779static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 780{
781 u32 stat_crtc = 0;
782 bool in_vbl = radeon_pm_in_vbl(rdev);
783
f735261b 784 if (in_vbl == false)
d9fdaafb 785 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 786 finish ? "exit" : "entry");
f735261b
DA		 787 return in_vbl;
788}
c913e23a 789
ce8f5370 790static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 791{
792 struct radeon_device *rdev;
d9932a32 793 int resched;
c913e23a 794 rdev = container_of(work, struct radeon_device,
ce8f5370 795 pm.dynpm_idle_work.work);
c913e23a 796
d9932a32 797 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 798 mutex_lock(&rdev->pm.mutex);
ce8f5370 799 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 800 int not_processed = 0;
7465280c
AD		 801 int i;
802
7465280c 803 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 804 struct radeon_ring *ring = &rdev->ring[i];
805
806 if (ring->ready) {
807 not_processed += radeon_fence_count_emitted(rdev, i);
808 if (not_processed >= 3)
809 break;
810 }
c913e23a 811 }
c913e23a
RM		 812
813 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 814 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
815 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
816 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
817 rdev->pm.dynpm_can_upclock) {
818 rdev->pm.dynpm_planned_action =
819 DYNPM_ACTION_UPCLOCK;
820 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 821 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
822 }
823 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 824 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
825 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
826 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
827 rdev->pm.dynpm_can_downclock) {
828 rdev->pm.dynpm_planned_action =
829 DYNPM_ACTION_DOWNCLOCK;
830 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 831 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
832 }
833 }
834
d7311171
AD		 835 /* Note, radeon_pm_set_clocks is called with static_switch set
836 * to false since we want to wait for vbl to avoid flicker.
837 */
ce8f5370
AD		 838 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
839 jiffies > rdev->pm.dynpm_action_timeout) {
840 radeon_pm_get_dynpm_state(rdev);
841 radeon_pm_set_clocks(rdev);
c913e23a 842 }
3f53eb6f 843
32c87fca
TH		 844 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
845 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 846 }
847 mutex_unlock(&rdev->pm.mutex);
d9932a32 848 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 849}
850
7433874e
RM		 851/*
852 * Debugfs info
853 */
854#if defined(CONFIG_DEBUG_FS)
855
856static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
857{
858 struct drm_info_node *node = (struct drm_info_node *) m->private;
859 struct drm_device *dev = node->minor->dev;
860 struct radeon_device *rdev = dev->dev_private;
861
9ace9f7b 862 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 863 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 864 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 865 if (rdev->asic->pm.get_memory_clock)
6234077d 866 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 867 if (rdev->pm.current_vddc)
868 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 869 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 870 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 871
872 return 0;
873}
874
875static struct drm_info_list radeon_pm_info_list[] = {
876 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
877};
878#endif
879
c913e23a 880static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 881{
882#if defined(CONFIG_DEBUG_FS)
883 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
884#else
885 return 0;
886#endif
887}
Linux kernel - Deliverables
This page took 0.193427 seconds and 5 git commands to generate.