[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c

/*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rafał Miłecki <zajec5@gmail.com>
 *          Alex Deucher <alexdeucher@gmail.com>
 */
#include "drmP.h"
#include "radeon.h"
#include "avivod.h"

#define RADEON_IDLE_LOOP_MS 100
#define RADEON_RECLOCK_DELAY_MS 200
#define RADEON_WAIT_VBLANK_TIMEOUT 200
#define RADEON_WAIT_IDLE_TIMEOUT 200

static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
static void radeon_pm_set_clocks(struct radeon_device *rdev);
static void radeon_pm_idle_work_handler(struct work_struct *work);
static int radeon_debugfs_pm_init(struct radeon_device *rdev);

static const char *pm_state_names[4] = {
	"PM_STATE_DISABLED",
	"PM_STATE_MINIMUM",
	"PM_STATE_PAUSED",
	"PM_STATE_ACTIVE"
};

static const char *pm_state_types[5] = {
	"",
	"Powersave",
	"Battery",
	"Balanced",
	"Performance",
};

static void radeon_print_power_mode_info(struct radeon_device *rdev)
{
	int i, j;
	bool is_default;

	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	for (i = 0; i < rdev->pm.num_power_states; i++) {
		if (rdev->pm.default_power_state_index == i)
			is_default = true;
		else
			is_default = false;
		DRM_INFO("State %d %s %s\n", i,
			 pm_state_types[rdev->pm.power_state[i].type],
			 is_default ? "(default)" : "");
		if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
			DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
		if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
			DRM_INFO("\tSingle display only\n");
		DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
		for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
			if (rdev->flags & RADEON_IS_IGP)
				DRM_INFO("\t\t%d engine: %d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10);
			else
				DRM_INFO("\t\t%d engine/memory: %d/%d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10,
					 rdev->pm.power_state[i].clock_info[j].mclk * 10);
		}
	}
}

void radeon_sync_with_vblank(struct radeon_device *rdev)
{
	if (rdev->pm.active_crtcs) {
		rdev->pm.vblank_sync = false;
		wait_event_timeout(
			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	}
}

int radeon_pm_init(struct radeon_device *rdev)
{
	rdev->pm.state = PM_STATE_DISABLED;
	rdev->pm.planned_action = PM_ACTION_NONE;
	rdev->pm.can_upclock = true;
	rdev->pm.can_downclock = true;

	if (rdev->bios) {
		if (rdev->is_atom_bios)
			radeon_atombios_get_power_modes(rdev);
		else
			radeon_combios_get_power_modes(rdev);
		radeon_print_power_mode_info(rdev);
	}

	if (radeon_debugfs_pm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for PM!\n");
	}

	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);

	if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
		rdev->pm.state = PM_STATE_PAUSED;
		DRM_INFO("radeon: dynamic power management enabled\n");
	}

	DRM_INFO("radeon: power management initialized\n");

	return 0;
}

void radeon_pm_fini(struct radeon_device *rdev)
{
	if (rdev->pm.state != PM_STATE_DISABLED) {
		/* cancel work */
		cancel_delayed_work_sync(&rdev->pm.idle_work);
		/* reset default clocks */
		rdev->pm.state = PM_STATE_DISABLED;
		rdev->pm.planned_action = PM_ACTION_DEFAULT;
		radeon_pm_set_clocks(rdev);
	}

	if (rdev->pm.i2c_bus)
		radeon_i2c_destroy(rdev->pm.i2c_bus);
}

void radeon_pm_compute_clocks(struct radeon_device *rdev)
{
	struct drm_device *ddev = rdev->ddev;
	struct drm_crtc *crtc;
	struct radeon_crtc *radeon_crtc;

	if (rdev->pm.state == PM_STATE_DISABLED)
		return;

	mutex_lock(&rdev->pm.mutex);

	rdev->pm.active_crtcs = 0;
	rdev->pm.active_crtc_count = 0;
	list_for_each_entry(crtc,
		&ddev->mode_config.crtc_list, head) {
		radeon_crtc = to_radeon_crtc(crtc);
		if (radeon_crtc->enabled) {
			rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
			rdev->pm.active_crtc_count++;
		}
	}

	if (rdev->pm.active_crtc_count > 1) {
		if (rdev->pm.state == PM_STATE_ACTIVE) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_PAUSED;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev);

			DRM_DEBUG("radeon: dynamic power management deactivated\n");
		}
	} else if (rdev->pm.active_crtc_count == 1) {
		/* TODO: Increase clocks if needed for current mode */

		if (rdev->pm.state == PM_STATE_MINIMUM) {
			rdev->pm.state = PM_STATE_ACTIVE;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev);

			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
		} else if (rdev->pm.state == PM_STATE_PAUSED) {
			rdev->pm.state = PM_STATE_ACTIVE;
			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
			DRM_DEBUG("radeon: dynamic power management activated\n");
		}
	} else { /* count == 0 */
		if (rdev->pm.state != PM_STATE_MINIMUM) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_MINIMUM;
			rdev->pm.planned_action = PM_ACTION_MINIMUM;
			radeon_pm_set_clocks(rdev);
		}
	}

	mutex_unlock(&rdev->pm.mutex);
}

bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
{
	u32 stat_crtc = 0;
	bool in_vbl = true;

	if (ASIC_IS_DCE4(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 2)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 3)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 4)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 5)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	} else if (ASIC_IS_AVIVO(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(D1CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(D2CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	} else {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(RADEON_CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	}
	if (in_vbl == false)
		DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
			 finish ? "exit" : "entry");
	return in_vbl;
}
static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
{
	/*radeon_fence_wait_last(rdev);*/

	radeon_set_power_state(rdev);
	rdev->pm.planned_action = PM_ACTION_NONE;
}

static void radeon_pm_set_clocks(struct radeon_device *rdev)
{
	int i;

	radeon_get_power_state(rdev, rdev->pm.planned_action);
	mutex_lock(&rdev->cp.mutex);

	/* wait for GPU idle */
	rdev->pm.gui_idle = false;
	rdev->irq.gui_idle = true;
	radeon_irq_set(rdev);
	wait_event_interruptible_timeout(
		rdev->irq.idle_queue, rdev->pm.gui_idle,
		msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	rdev->irq.gui_idle = false;
	radeon_irq_set(rdev);

	for (i = 0; i < rdev->num_crtc; i++) {
		if (rdev->pm.active_crtcs & (1 << i)) {
			rdev->pm.req_vblank |= (1 << i);
			drm_vblank_get(rdev->ddev, i);
		}
	}
	radeon_pm_set_clocks_locked(rdev);
	for (i = 0; i < rdev->num_crtc; i++) {
		if (rdev->pm.req_vblank & (1 << i)) {
			rdev->pm.req_vblank &= ~(1 << i);
			drm_vblank_put(rdev->ddev, i);
		}
	}

	/* update display watermarks based on new power state */
	radeon_update_bandwidth_info(rdev);
	if (rdev->pm.active_crtc_count)
		radeon_bandwidth_update(rdev);

	mutex_unlock(&rdev->cp.mutex);
}

static void radeon_pm_idle_work_handler(struct work_struct *work)
{
	struct radeon_device *rdev;
	rdev = container_of(work, struct radeon_device,
				pm.idle_work.work);

	mutex_lock(&rdev->pm.mutex);
	if (rdev->pm.state == PM_STATE_ACTIVE) {
		unsigned long irq_flags;
		int not_processed = 0;

		read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
		if (!list_empty(&rdev->fence_drv.emited)) {
			struct list_head *ptr;
			list_for_each(ptr, &rdev->fence_drv.emited) {
				/* count up to 3, that's enought info */
				if (++not_processed >= 3)
					break;
			}
		}
		read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);

		if (not_processed >= 3) { /* should upclock */
			if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				   rdev->pm.can_upclock) {
				rdev->pm.planned_action =
					PM_ACTION_UPCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		} else if (not_processed == 0) { /* should downclock */
			if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				   rdev->pm.can_downclock) {
				rdev->pm.planned_action =
					PM_ACTION_DOWNCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		}

		if (rdev->pm.planned_action != PM_ACTION_NONE &&
		    jiffies > rdev->pm.action_timeout) {
			radeon_pm_set_clocks(rdev);
		}
	}
	mutex_unlock(&rdev->pm.mutex);

	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;

	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	if (rdev->asic->get_memory_clock)
		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
	if (rdev->asic->get_pcie_lanes)
		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));

	return 0;
}

static struct drm_info_list radeon_pm_info_list[] = {
	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
};
#endif

static int radeon_debugfs_pm_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
#else
	return 0;
#endif
}
Commit	Line	Data
7433874e RM	1	/*
	2	* Permission is hereby granted, free of charge, to any person obtaining a
	3	* copy of this software and associated documentation files (the "Software"),
	4	* to deal in the Software without restriction, including without limitation
	5	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	6	* and/or sell copies of the Software, and to permit persons to whom the
	7	* Software is furnished to do so, subject to the following conditions:
	8	*
	9	* The above copyright notice and this permission notice shall be included in
	10	* all copies or substantial portions of the Software.
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	16	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	17	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	18	* OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e	21	* Alex Deucher <alexdeucher@gmail.com>
7433874e RM	22	*/
	23	#include "drmP.h"
	24	#include "radeon.h"
f735261b	25	#include "avivod.h"
7433874e	26
c913e23a RM	27	#define RADEON_IDLE_LOOP_MS 100
c913e23a RM	28	#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc	29	#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c	30	#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a	31
c913e23a RM	32	static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
c913e23a RM	33	static void radeon_pm_set_clocks(struct radeon_device *rdev);
c913e23a RM	34	static void radeon_pm_idle_work_handler(struct work_struct *work);
	35	static int radeon_debugfs_pm_init(struct radeon_device *rdev);
	36
	37	static const char *pm_state_names[4] = {
	38	"PM_STATE_DISABLED",
	39	"PM_STATE_MINIMUM",
	40	"PM_STATE_PAUSED",
	41	"PM_STATE_ACTIVE"
	42	};
7433874e	43
0ec0e74f	44	static const char *pm_state_types[5] = {
d91eeb78	45	"",
0ec0e74f AD	46	"Powersave",
	47	"Battery",
	48	"Balanced",
	49	"Performance",
	50	};
	51
56278a8e AD	52	static void radeon_print_power_mode_info(struct radeon_device *rdev)
	53	{
	54	int i, j;
	55	bool is_default;
	56
	57	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	58	for (i = 0; i < rdev->pm.num_power_states; i++) {
a48b9b4e	59	if (rdev->pm.default_power_state_index == i)
56278a8e AD	60	is_default = true;
	61	else
	62	is_default = false;
0ec0e74f AD	63	DRM_INFO("State %d %s %s\n", i,
	64	pm_state_types[rdev->pm.power_state[i].type],
	65	is_default ? "(default)" : "");
56278a8e	66	if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
79daedc9	67	DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
a48b9b4e AD	68	if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
a48b9b4e AD	69	DRM_INFO("\tSingle display only\n");
56278a8e AD	70	DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
	71	for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
	72	if (rdev->flags & RADEON_IS_IGP)
	73	DRM_INFO("\t\t%d engine: %d\n",
	74	j,
	75	rdev->pm.power_state[i].clock_info[j].sclk * 10);
	76	else
	77	DRM_INFO("\t\t%d engine/memory: %d/%d\n",
	78	j,
	79	rdev->pm.power_state[i].clock_info[j].sclk * 10,
	80	rdev->pm.power_state[i].clock_info[j].mclk * 10);
	81	}
	82	}
	83	}
	84
bae6b562	85	void radeon_sync_with_vblank(struct radeon_device *rdev)
d0d6cb81 RM	86	{
	87	if (rdev->pm.active_crtcs) {
	88	rdev->pm.vblank_sync = false;
	89	wait_event_timeout(
	90	rdev->irq.vblank_queue, rdev->pm.vblank_sync,
	91	msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	92	}
	93	}
	94
7433874e RM	95	int radeon_pm_init(struct radeon_device *rdev)
7433874e RM	96	{
c913e23a RM	97	rdev->pm.state = PM_STATE_DISABLED;
c913e23a RM	98	rdev->pm.planned_action = PM_ACTION_NONE;
a48b9b4e AD	99	rdev->pm.can_upclock = true;
a48b9b4e AD	100	rdev->pm.can_downclock = true;
c913e23a	101
56278a8e AD	102	if (rdev->bios) {
	103	if (rdev->is_atom_bios)
	104	radeon_atombios_get_power_modes(rdev);
	105	else
	106	radeon_combios_get_power_modes(rdev);
	107	radeon_print_power_mode_info(rdev);
	108	}
	109
7433874e	110	if (radeon_debugfs_pm_init(rdev)) {
c142c3e5	111	DRM_ERROR("Failed to register debugfs file for PM!\n");
7433874e RM	112	}
7433874e RM	113
c913e23a RM	114	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
c913e23a RM	115
90c39059	116	if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
c913e23a RM	117	rdev->pm.state = PM_STATE_PAUSED;
	118	DRM_INFO("radeon: dynamic power management enabled\n");
	119	}
	120
	121	DRM_INFO("radeon: power management initialized\n");
	122
7433874e RM	123	return 0;
	124	}
	125
29fb52ca AD	126	void radeon_pm_fini(struct radeon_device *rdev)
29fb52ca AD	127	{
58e21dff AD	128	if (rdev->pm.state != PM_STATE_DISABLED) {
	129	/* cancel work */
	130	cancel_delayed_work_sync(&rdev->pm.idle_work);
	131	/* reset default clocks */
	132	rdev->pm.state = PM_STATE_DISABLED;
	133	rdev->pm.planned_action = PM_ACTION_DEFAULT;
	134	radeon_pm_set_clocks(rdev);
	135	}
	136
29fb52ca AD	137	if (rdev->pm.i2c_bus)
	138	radeon_i2c_destroy(rdev->pm.i2c_bus);
	139	}
	140
c913e23a RM	141	void radeon_pm_compute_clocks(struct radeon_device *rdev)
	142	{
	143	struct drm_device *ddev = rdev->ddev;
a48b9b4e	144	struct drm_crtc *crtc;
c913e23a	145	struct radeon_crtc *radeon_crtc;
c913e23a RM	146
	147	if (rdev->pm.state == PM_STATE_DISABLED)
	148	return;
	149
	150	mutex_lock(&rdev->pm.mutex);
	151
	152	rdev->pm.active_crtcs = 0;
a48b9b4e AD	153	rdev->pm.active_crtc_count = 0;
	154	list_for_each_entry(crtc,
	155	&ddev->mode_config.crtc_list, head) {
	156	radeon_crtc = to_radeon_crtc(crtc);
	157	if (radeon_crtc->enabled) {
c913e23a	158	rdev->pm.active_crtcs \|= (1 << radeon_crtc->crtc_id);
a48b9b4e	159	rdev->pm.active_crtc_count++;
c913e23a RM	160	}
	161	}
	162
a48b9b4e	163	if (rdev->pm.active_crtc_count > 1) {
c913e23a	164	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	165	cancel_delayed_work(&rdev->pm.idle_work);
	166
	167	rdev->pm.state = PM_STATE_PAUSED;
	168	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
a48b9b4e	169	radeon_pm_set_clocks(rdev);
c913e23a RM	170
c913e23a RM	171	DRM_DEBUG("radeon: dynamic power management deactivated\n");
c913e23a	172	}
a48b9b4e	173	} else if (rdev->pm.active_crtc_count == 1) {
c913e23a RM	174	/* TODO: Increase clocks if needed for current mode */
	175
	176	if (rdev->pm.state == PM_STATE_MINIMUM) {
	177	rdev->pm.state = PM_STATE_ACTIVE;
	178	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
73a6d3fc	179	radeon_pm_set_clocks(rdev);
c913e23a RM	180
	181	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	182	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
a48b9b4e	183	} else if (rdev->pm.state == PM_STATE_PAUSED) {
c913e23a RM	184	rdev->pm.state = PM_STATE_ACTIVE;
	185	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	186	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	187	DRM_DEBUG("radeon: dynamic power management activated\n");
	188	}
a48b9b4e	189	} else { /* count == 0 */
c913e23a RM	190	if (rdev->pm.state != PM_STATE_MINIMUM) {
	191	cancel_delayed_work(&rdev->pm.idle_work);
	192
	193	rdev->pm.state = PM_STATE_MINIMUM;
	194	rdev->pm.planned_action = PM_ACTION_MINIMUM;
73a6d3fc	195	radeon_pm_set_clocks(rdev);
c913e23a	196	}
c913e23a	197	}
73a6d3fc RM	198
73a6d3fc RM	199	mutex_unlock(&rdev->pm.mutex);
c913e23a RM	200	}
c913e23a RM	201
bae6b562	202	bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f735261b	203	{
bae6b562	204	u32 stat_crtc = 0;
f735261b DA	205	bool in_vbl = true;
f735261b DA	206
bae6b562 AD	207	if (ASIC_IS_DCE4(rdev)) {
	208	if (rdev->pm.active_crtcs & (1 << 0)) {
	209	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
	210	if (!(stat_crtc & 1))
	211	in_vbl = false;
	212	}
	213	if (rdev->pm.active_crtcs & (1 << 1)) {
	214	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
	215	if (!(stat_crtc & 1))
	216	in_vbl = false;
	217	}
	218	if (rdev->pm.active_crtcs & (1 << 2)) {
	219	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
	220	if (!(stat_crtc & 1))
	221	in_vbl = false;
	222	}
	223	if (rdev->pm.active_crtcs & (1 << 3)) {
	224	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
	225	if (!(stat_crtc & 1))
	226	in_vbl = false;
	227	}
	228	if (rdev->pm.active_crtcs & (1 << 4)) {
	229	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
	230	if (!(stat_crtc & 1))
	231	in_vbl = false;
	232	}
	233	if (rdev->pm.active_crtcs & (1 << 5)) {
	234	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
	235	if (!(stat_crtc & 1))
	236	in_vbl = false;
	237	}
	238	} else if (ASIC_IS_AVIVO(rdev)) {
	239	if (rdev->pm.active_crtcs & (1 << 0)) {
	240	stat_crtc = RREG32(D1CRTC_STATUS);
	241	if (!(stat_crtc & 1))
	242	in_vbl = false;
	243	}
	244	if (rdev->pm.active_crtcs & (1 << 1)) {
	245	stat_crtc = RREG32(D2CRTC_STATUS);
	246	if (!(stat_crtc & 1))
	247	in_vbl = false;
	248	}
	249	} else {
f735261b	250	if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562 AD	251	stat_crtc = RREG32(RADEON_CRTC_STATUS);
bae6b562 AD	252	if (!(stat_crtc & 1))
f735261b DA	253	in_vbl = false;
	254	}
	255	if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562 AD	256	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
bae6b562 AD	257	if (!(stat_crtc & 1))
f735261b DA	258	in_vbl = false;
	259	}
	260	}
	261	if (in_vbl == false)
bae6b562 AD	262	DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 AD	263	finish ? "exit" : "entry");
f735261b DA	264	return in_vbl;
f735261b DA	265	}
c913e23a RM	266	static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
	267	{
	268	/radeon_fence_wait_last(rdev);/
f735261b	269
530079a8	270	radeon_set_power_state(rdev);
c913e23a RM	271	rdev->pm.planned_action = PM_ACTION_NONE;
	272	}
	273
	274	static void radeon_pm_set_clocks(struct radeon_device *rdev)
	275	{
8a56df63 AD	276	int i;
8a56df63 AD	277
73a6d3fc RM	278	radeon_get_power_state(rdev, rdev->pm.planned_action);
	279	mutex_lock(&rdev->cp.mutex);
	280
ef6e6cf5 AD	281	/* wait for GPU idle */
	282	rdev->pm.gui_idle = false;
	283	rdev->irq.gui_idle = true;
	284	radeon_irq_set(rdev);
	285	wait_event_interruptible_timeout(
	286	rdev->irq.idle_queue, rdev->pm.gui_idle,
	287	msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	288	rdev->irq.gui_idle = false;
	289	radeon_irq_set(rdev);
	290
8a56df63 AD	291	for (i = 0; i < rdev->num_crtc; i++) {
	292	if (rdev->pm.active_crtcs & (1 << i)) {
	293	rdev->pm.req_vblank \|= (1 << i);
	294	drm_vblank_get(rdev->ddev, i);
	295	}
73a6d3fc	296	}
d0d6cb81	297	radeon_pm_set_clocks_locked(rdev);
8a56df63 AD	298	for (i = 0; i < rdev->num_crtc; i++) {
	299	if (rdev->pm.req_vblank & (1 << i)) {
	300	rdev->pm.req_vblank &= ~(1 << i);
	301	drm_vblank_put(rdev->ddev, i);
	302	}
c913e23a	303	}
c913e23a	304
c00f53be AD	305	/* update display watermarks based on new power state */
	306	radeon_update_bandwidth_info(rdev);
	307	if (rdev->pm.active_crtc_count)
	308	radeon_bandwidth_update(rdev);
	309
73a6d3fc	310	mutex_unlock(&rdev->cp.mutex);
c913e23a RM	311	}
	312
	313	static void radeon_pm_idle_work_handler(struct work_struct *work)
	314	{
	315	struct radeon_device *rdev;
	316	rdev = container_of(work, struct radeon_device,
	317	pm.idle_work.work);
	318
	319	mutex_lock(&rdev->pm.mutex);
73a6d3fc	320	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	321	unsigned long irq_flags;
	322	int not_processed = 0;
	323
	324	read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
	325	if (!list_empty(&rdev->fence_drv.emited)) {
	326	struct list_head *ptr;
	327	list_for_each(ptr, &rdev->fence_drv.emited) {
	328	/* count up to 3, that's enought info */
	329	if (++not_processed >= 3)
	330	break;
	331	}
	332	}
	333	read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
	334
	335	if (not_processed >= 3) { /* should upclock */
	336	if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
	337	rdev->pm.planned_action = PM_ACTION_NONE;
	338	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
a48b9b4e	339	rdev->pm.can_upclock) {
c913e23a RM	340	rdev->pm.planned_action =
	341	PM_ACTION_UPCLOCK;
	342	rdev->pm.action_timeout = jiffies +
	343	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	344	}
	345	} else if (not_processed == 0) { /* should downclock */
	346	if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
	347	rdev->pm.planned_action = PM_ACTION_NONE;
	348	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
a48b9b4e	349	rdev->pm.can_downclock) {
c913e23a RM	350	rdev->pm.planned_action =
	351	PM_ACTION_DOWNCLOCK;
	352	rdev->pm.action_timeout = jiffies +
	353	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	354	}
	355	}
	356
	357	if (rdev->pm.planned_action != PM_ACTION_NONE &&
73a6d3fc RM	358	jiffies > rdev->pm.action_timeout) {
73a6d3fc RM	359	radeon_pm_set_clocks(rdev);
c913e23a RM	360	}
	361	}
	362	mutex_unlock(&rdev->pm.mutex);
	363
	364	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	365	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	366	}
	367
7433874e RM	368	/*
	369	* Debugfs info
	370	*/
	371	#if defined(CONFIG_DEBUG_FS)
	372
	373	static int radeon_debugfs_pm_info(struct seq_file m, void data)
	374	{
	375	struct drm_info_node node = (struct drm_info_node ) m->private;
	376	struct drm_device *dev = node->minor->dev;
	377	struct radeon_device *rdev = dev->dev_private;
	378
c913e23a	379	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
6234077d RM	380	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	381	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	382	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	383	if (rdev->asic->get_memory_clock)
	384	seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
aa5120d2 RM	385	if (rdev->asic->get_pcie_lanes)
aa5120d2 RM	386	seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e RM	387
	388	return 0;
	389	}
	390
	391	static struct drm_info_list radeon_pm_info_list[] = {
	392	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
	393	};
	394	#endif
	395
c913e23a	396	static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e RM	397	{
	398	#if defined(CONFIG_DEBUG_FS)
	399	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
	400	#else
	401	return 0;
	402	#endif
	403	}