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drm/radeon: fix surface setup on r1xx
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
c4917074
AD		 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 76 }
77 }
ce8f5370 78}
ce8f5370
AD		 79
80static void radeon_pm_update_profile(struct radeon_device *rdev)
81{
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
85 break;
86 case PM_PROFILE_AUTO:
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
90 else
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
92 } else {
93 if (rdev->pm.active_crtc_count > 1)
c9e75b21 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 95 else
c9e75b21 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 97 }
98 break;
99 case PM_PROFILE_LOW:
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
104 break;
c9e75b21
AD		 105 case PM_PROFILE_MID:
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
110 break;
ce8f5370
AD		 111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
116 break;
117 }
118
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
124 } else {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
129 }
130}
c913e23a 131
5876dd24
MG		 132static void radeon_unmap_vram_bos(struct radeon_device *rdev)
133{
134 struct radeon_bo *bo, *n;
135
136 if (list_empty(&rdev->gem.objects))
137 return;
138
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
142 }
5876dd24
MG		 143}
144
ce8f5370 145static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 146{
ce8f5370
AD		 147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
149 wait_event_timeout(
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
152 }
153}
154
155static void radeon_set_power_state(struct radeon_device *rdev)
156{
157 u32 sclk, mclk;
92645879 158 bool misc_after = false;
ce8f5370
AD		 159
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
162 return;
163
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
ce8f5370 169
27810fb2
AD		 170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 172 * mclk and vddci.
27810fb2
AD		 173 */
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
181 else
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
184
9ace9f7b
AD		 185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
ce8f5370 187
92645879
AD		 188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
190 misc_after = true;
ce8f5370 191
92645879 192 radeon_sync_with_vblank(rdev);
ce8f5370 193
92645879 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 195 if (!radeon_pm_in_vbl(rdev))
196 return;
92645879 197 }
ce8f5370 198
92645879 199 radeon_pm_prepare(rdev);
ce8f5370 200
92645879
AD		 201 if (!misc_after)
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
204
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
d9fdaafb 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 212 }
213
214 /* set memory clock */
798bcf73 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 221 }
2aba631c 222
92645879
AD		 223 if (misc_after)
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
226
227 radeon_pm_finish(rdev);
228
ce8f5370
AD		 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
231 } else
d9fdaafb 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 233}
234
235static void radeon_pm_set_clocks(struct radeon_device *rdev)
236{
5f8f635e 237 int i, r;
c37d230a 238
4e186b2d
AD		 239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
242 return;
243
612e06ce 244 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 245 down_write(&rdev->pm.mclk_lock);
d6999bc7 246 mutex_lock(&rdev->ring_lock);
4f3218cb 247
95f5a3ac
AD		 248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 251 if (!ring->ready) {
252 continue;
253 }
254 r = radeon_fence_wait_empty_locked(rdev, i);
255 if (r) {
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
260 return;
261 }
4f3218cb 262 }
95f5a3ac 263
5876dd24
MG		 264 radeon_unmap_vram_bos(rdev);
265
ce8f5370 266 if (rdev->irq.installed) {
2aba631c
MG		 267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
271 }
272 }
273 }
539d2418 274
ce8f5370 275 radeon_set_power_state(rdev);
2aba631c 276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
282 }
283 }
284 }
5876dd24 285
a424816f
AD		 286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
290
ce8f5370 291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 292
d6999bc7 293 mutex_unlock(&rdev->ring_lock);
db7fce39 294 up_write(&rdev->pm.mclk_lock);
612e06ce 295 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 296}
297
f712d0c7
RM		 298static void radeon_pm_print_states(struct radeon_device *rdev)
299{
300 int i, j;
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
303
d9fdaafb 304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
d9fdaafb 307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
d9fdaafb 310 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
320 j,
321 clock_info->sclk * 10);
f712d0c7 322 else
eb2c27a0
AD		 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
324 j,
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
f712d0c7
RM		 328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
1783e4bf 368 count = -EINVAL;
ce8f5370 369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 373 } else
374 count = -EINVAL;
375
ce8f5370 376fail:
a424816f
AD		 377 mutex_unlock(&rdev->pm.mutex);
378
379 return count;
380}
381
ce8f5370
AD		 382static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
384 char *buf)
a424816f
AD		 385{
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 388 int pm = rdev->pm.pm_method;
a424816f
AD		 389
390 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 391 (pm == PM_METHOD_DYNPM) ? "dynpm" :
392 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 393}
394
ce8f5370
AD		 395static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t count)
a424816f
AD		 399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
a424816f 402
da321c8a
AD		 403 /* we don't support the legacy modes with dpm */
404 if (rdev->pm.pm_method == PM_METHOD_DPM) {
405 count = -EINVAL;
406 goto fail;
407 }
ce8f5370
AD		 408
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 410 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 414 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 417 /* disable dynpm */
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 420 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 421 mutex_unlock(&rdev->pm.mutex);
32c87fca 422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 423 } else {
1783e4bf 424 count = -EINVAL;
ce8f5370
AD		 425 goto fail;
426 }
427 radeon_pm_compute_clocks(rdev);
428fail:
a424816f
AD		 429 return count;
430}
431
da321c8a
AD		 432static ssize_t radeon_get_dpm_state(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435{
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
438 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
439
440 return snprintf(buf, PAGE_SIZE, "%s\n",
441 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
443}
444
445static ssize_t radeon_set_dpm_state(struct device *dev,
446 struct device_attribute *attr,
447 const char *buf,
448 size_t count)
449{
450 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
451 struct radeon_device *rdev = ddev->dev_private;
452
453 mutex_lock(&rdev->pm.mutex);
454 if (strncmp("battery", buf, strlen("battery")) == 0)
455 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
456 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
457 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
458 else if (strncmp("performance", buf, strlen("performance")) == 0)
459 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
460 else {
461 mutex_unlock(&rdev->pm.mutex);
462 count = -EINVAL;
463 goto fail;
464 }
465 mutex_unlock(&rdev->pm.mutex);
466 radeon_pm_compute_clocks(rdev);
467fail:
468 return count;
469}
470
ce8f5370
AD		 471static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
472static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 473static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
a424816f 474
21a8122a
AD		 475static ssize_t radeon_hwmon_show_temp(struct device *dev,
476 struct device_attribute *attr,
477 char *buf)
478{
479 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
480 struct radeon_device *rdev = ddev->dev_private;
20d391d7 481 int temp;
21a8122a 482
6bd1c385
AD		 483 if (rdev->asic->pm.get_temperature)
484 temp = radeon_get_temperature(rdev);
485 else
21a8122a 486 temp = 0;
21a8122a
AD		 487
488 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
489}
490
491static ssize_t radeon_hwmon_show_name(struct device *dev,
492 struct device_attribute *attr,
493 char *buf)
494{
495 return sprintf(buf, "radeon\n");
496}
497
498static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
499static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
500
501static struct attribute *hwmon_attributes[] = {
502 &sensor_dev_attr_temp1_input.dev_attr.attr,
503 &sensor_dev_attr_name.dev_attr.attr,
504 NULL
505};
506
507static const struct attribute_group hwmon_attrgroup = {
508 .attrs = hwmon_attributes,
509};
510
0d18abed 511static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 512{
0d18abed 513 int err = 0;
21a8122a
AD		 514
515 rdev->pm.int_hwmon_dev = NULL;
516
517 switch (rdev->pm.int_thermal_type) {
518 case THERMAL_TYPE_RV6XX:
519 case THERMAL_TYPE_RV770:
520 case THERMAL_TYPE_EVERGREEN:
457558ed 521 case THERMAL_TYPE_NI:
e33df25f 522 case THERMAL_TYPE_SUMO:
1bd47d2e 523 case THERMAL_TYPE_SI:
6bd1c385 524 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 525 return err;
21a8122a 526 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 527 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
528 err = PTR_ERR(rdev->pm.int_hwmon_dev);
529 dev_err(rdev->dev,
530 "Unable to register hwmon device: %d\n", err);
531 break;
532 }
21a8122a
AD		 533 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
534 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
535 &hwmon_attrgroup);
0d18abed
DC		 536 if (err) {
537 dev_err(rdev->dev,
538 "Unable to create hwmon sysfs file: %d\n", err);
539 hwmon_device_unregister(rdev->dev);
540 }
21a8122a
AD		 541 break;
542 default:
543 break;
544 }
0d18abed
DC		 545
546 return err;
21a8122a
AD		 547}
548
549static void radeon_hwmon_fini(struct radeon_device *rdev)
550{
551 if (rdev->pm.int_hwmon_dev) {
552 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
553 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
554 }
555}
556
da321c8a
AD		 557static void radeon_dpm_thermal_work_handler(struct work_struct *work)
558{
559 struct radeon_device *rdev =
560 container_of(work, struct radeon_device,
561 pm.dpm.thermal.work);
562 /* switch to the thermal state */
563 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
564
565 if (!rdev->pm.dpm_enabled)
566 return;
567
568 if (rdev->asic->pm.get_temperature) {
569 int temp = radeon_get_temperature(rdev);
570
571 if (temp < rdev->pm.dpm.thermal.min_temp)
572 /* switch back the user state */
573 dpm_state = rdev->pm.dpm.user_state;
574 } else {
575 if (rdev->pm.dpm.thermal.high_to_low)
576 /* switch back the user state */
577 dpm_state = rdev->pm.dpm.user_state;
578 }
579 radeon_dpm_enable_power_state(rdev, dpm_state);
580}
581
582static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
583 enum radeon_pm_state_type dpm_state)
584{
585 int i;
586 struct radeon_ps *ps;
587 u32 ui_class;
588
edcaa5b1
AD		 589 /* certain older asics have a separare 3D performance state,
590 * so try that first if the user selected performance
591 */
592 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
593 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
da321c8a
AD		 594 /* balanced states don't exist at the moment */
595 if (dpm_state == POWER_STATE_TYPE_BALANCED)
596 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
597
edcaa5b1 598restart_search:
da321c8a
AD		 599 /* Pick the best power state based on current conditions */
600 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
601 ps = &rdev->pm.dpm.ps[i];
602 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
603 switch (dpm_state) {
604 /* user states */
605 case POWER_STATE_TYPE_BATTERY:
606 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
607 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
608 if (rdev->pm.dpm.new_active_crtc_count < 2)
609 return ps;
610 } else
611 return ps;
612 }
613 break;
614 case POWER_STATE_TYPE_BALANCED:
615 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
616 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
617 if (rdev->pm.dpm.new_active_crtc_count < 2)
618 return ps;
619 } else
620 return ps;
621 }
622 break;
623 case POWER_STATE_TYPE_PERFORMANCE:
624 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
625 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
626 if (rdev->pm.dpm.new_active_crtc_count < 2)
627 return ps;
628 } else
629 return ps;
630 }
631 break;
632 /* internal states */
633 case POWER_STATE_TYPE_INTERNAL_UVD:
634 return rdev->pm.dpm.uvd_ps;
635 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
636 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
637 return ps;
638 break;
639 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
640 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
641 return ps;
642 break;
643 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
644 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
645 return ps;
646 break;
647 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
648 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
649 return ps;
650 break;
651 case POWER_STATE_TYPE_INTERNAL_BOOT:
652 return rdev->pm.dpm.boot_ps;
653 case POWER_STATE_TYPE_INTERNAL_THERMAL:
654 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
655 return ps;
656 break;
657 case POWER_STATE_TYPE_INTERNAL_ACPI:
658 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
659 return ps;
660 break;
661 case POWER_STATE_TYPE_INTERNAL_ULV:
662 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
663 return ps;
664 break;
edcaa5b1
AD		 665 case POWER_STATE_TYPE_INTERNAL_3DPERF:
666 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
667 return ps;
668 break;
da321c8a
AD		 669 default:
670 break;
671 }
672 }
673 /* use a fallback state if we didn't match */
674 switch (dpm_state) {
675 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
676 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
677 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
678 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
679 return rdev->pm.dpm.uvd_ps;
680 case POWER_STATE_TYPE_INTERNAL_THERMAL:
681 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
682 goto restart_search;
683 case POWER_STATE_TYPE_INTERNAL_ACPI:
684 dpm_state = POWER_STATE_TYPE_BATTERY;
685 goto restart_search;
686 case POWER_STATE_TYPE_BATTERY:
edcaa5b1
AD		 687 case POWER_STATE_TYPE_BALANCED:
688 case POWER_STATE_TYPE_INTERNAL_3DPERF:
da321c8a
AD		 689 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
690 goto restart_search;
691 default:
692 break;
693 }
694
695 return NULL;
696}
697
698static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
699{
700 int i;
701 struct radeon_ps *ps;
702 enum radeon_pm_state_type dpm_state;
84dd1928 703 int ret;
da321c8a
AD		 704
705 /* if dpm init failed */
706 if (!rdev->pm.dpm_enabled)
707 return;
708
709 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
710 /* add other state override checks here */
8a227555
AD		 711 if ((!rdev->pm.dpm.thermal_active) &&
712 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 713 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
714 }
715 dpm_state = rdev->pm.dpm.state;
716
717 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
718 if (ps)
89c9bc56 719 rdev->pm.dpm.requested_ps = ps;
da321c8a
AD		 720 else
721 return;
722
d22b7e40 723 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 724 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
d22b7e40
AD		 725 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
726 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
727 * all we need to do is update the display configuration.
728 */
729 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
730 /* update display watermarks based on new power state */
731 radeon_bandwidth_update(rdev);
732 /* update displays */
733 radeon_dpm_display_configuration_changed(rdev);
734 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
735 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
736 }
737 return;
738 } else {
739 /* for BTC+ if the num crtcs hasn't changed and state is the same,
740 * nothing to do, if the num crtcs is > 1 and state is the same,
741 * update display configuration.
742 */
743 if (rdev->pm.dpm.new_active_crtcs ==
744 rdev->pm.dpm.current_active_crtcs) {
745 return;
746 } else {
747 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
748 (rdev->pm.dpm.new_active_crtc_count > 1)) {
749 /* update display watermarks based on new power state */
750 radeon_bandwidth_update(rdev);
751 /* update displays */
752 radeon_dpm_display_configuration_changed(rdev);
753 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
754 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
755 return;
756 }
757 }
da321c8a 758 }
da321c8a
AD		 759 }
760
761 printk("switching from power state:\n");
762 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
763 printk("switching to power state:\n");
764 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
765
766 mutex_lock(&rdev->ddev->struct_mutex);
767 down_write(&rdev->pm.mclk_lock);
768 mutex_lock(&rdev->ring_lock);
769
89c9bc56
AD		 770 ret = radeon_dpm_pre_set_power_state(rdev);
771 if (ret)
772 goto done;
84dd1928 773
da321c8a
AD		 774 /* update display watermarks based on new power state */
775 radeon_bandwidth_update(rdev);
776 /* update displays */
777 radeon_dpm_display_configuration_changed(rdev);
778
779 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
780 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
781
782 /* wait for the rings to drain */
783 for (i = 0; i < RADEON_NUM_RINGS; i++) {
784 struct radeon_ring *ring = &rdev->ring[i];
785 if (ring->ready)
786 radeon_fence_wait_empty_locked(rdev, i);
787 }
788
789 /* program the new power state */
790 radeon_dpm_set_power_state(rdev);
791
792 /* update current power state */
793 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
794
89c9bc56 795 radeon_dpm_post_set_power_state(rdev);
84dd1928
AD		 796
797done:
da321c8a
AD		 798 mutex_unlock(&rdev->ring_lock);
799 up_write(&rdev->pm.mclk_lock);
800 mutex_unlock(&rdev->ddev->struct_mutex);
801}
802
803void radeon_dpm_enable_power_state(struct radeon_device *rdev,
804 enum radeon_pm_state_type dpm_state)
805{
806 if (!rdev->pm.dpm_enabled)
807 return;
808
809 mutex_lock(&rdev->pm.mutex);
810 switch (dpm_state) {
811 case POWER_STATE_TYPE_INTERNAL_THERMAL:
812 rdev->pm.dpm.thermal_active = true;
813 break;
8a227555
AD		 814 case POWER_STATE_TYPE_INTERNAL_UVD:
815 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
816 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
817 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
818 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
819 rdev->pm.dpm.uvd_active = true;
820 break;
da321c8a
AD		 821 default:
822 rdev->pm.dpm.thermal_active = false;
8a227555 823 rdev->pm.dpm.uvd_active = false;
da321c8a
AD		 824 break;
825 }
826 rdev->pm.dpm.state = dpm_state;
827 mutex_unlock(&rdev->pm.mutex);
828 radeon_pm_compute_clocks(rdev);
829}
830
831static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 832{
ce8f5370 833 mutex_lock(&rdev->pm.mutex);
3f53eb6f 834 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 835 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
836 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 837 }
ce8f5370 838 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 839
840 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 841}
842
da321c8a
AD		 843static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
844{
845 mutex_lock(&rdev->pm.mutex);
846 /* disable dpm */
847 radeon_dpm_disable(rdev);
848 /* reset the power state */
849 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
850 rdev->pm.dpm_enabled = false;
851 mutex_unlock(&rdev->pm.mutex);
852}
853
854void radeon_pm_suspend(struct radeon_device *rdev)
855{
856 if (rdev->pm.pm_method == PM_METHOD_DPM)
857 radeon_pm_suspend_dpm(rdev);
858 else
859 radeon_pm_suspend_old(rdev);
860}
861
862static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 863{
ed18a360 864 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 865 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 866 (rdev->family <= CHIP_HAINAN) &&
2e3b3b10 867 rdev->mc_fw) {
ed18a360 868 if (rdev->pm.default_vddc)
8a83ec5e
AD		 869 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
870 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 871 if (rdev->pm.default_vddci)
872 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
873 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 874 if (rdev->pm.default_sclk)
875 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
876 if (rdev->pm.default_mclk)
877 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
878 }
f8ed8b4c
AD		 879 /* asic init will reset the default power state */
880 mutex_lock(&rdev->pm.mutex);
881 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
882 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 883 rdev->pm.current_sclk = rdev->pm.default_sclk;
884 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 885 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 886 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 887 if (rdev->pm.pm_method == PM_METHOD_DYNPM
888 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
889 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 890 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
891 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 892 }
f8ed8b4c 893 mutex_unlock(&rdev->pm.mutex);
ce8f5370 894 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 895}
896
da321c8a
AD		 897static void radeon_pm_resume_dpm(struct radeon_device *rdev)
898{
899 int ret;
900
901 /* asic init will reset to the boot state */
902 mutex_lock(&rdev->pm.mutex);
903 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
904 radeon_dpm_setup_asic(rdev);
905 ret = radeon_dpm_enable(rdev);
906 mutex_unlock(&rdev->pm.mutex);
907 if (ret) {
908 DRM_ERROR("radeon: dpm resume failed\n");
909 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 910 (rdev->family <= CHIP_HAINAN) &&
da321c8a
AD		 911 rdev->mc_fw) {
912 if (rdev->pm.default_vddc)
913 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
914 SET_VOLTAGE_TYPE_ASIC_VDDC);
915 if (rdev->pm.default_vddci)
916 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
917 SET_VOLTAGE_TYPE_ASIC_VDDCI);
918 if (rdev->pm.default_sclk)
919 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
920 if (rdev->pm.default_mclk)
921 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
922 }
923 } else {
924 rdev->pm.dpm_enabled = true;
925 radeon_pm_compute_clocks(rdev);
926 }
927}
928
929void radeon_pm_resume(struct radeon_device *rdev)
930{
931 if (rdev->pm.pm_method == PM_METHOD_DPM)
932 radeon_pm_resume_dpm(rdev);
933 else
934 radeon_pm_resume_old(rdev);
935}
936
937static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 938{
26481fb1 939 int ret;
0d18abed 940
f8ed8b4c 941 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 942 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
943 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
944 rdev->pm.dynpm_can_upclock = true;
945 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 946 rdev->pm.default_sclk = rdev->clock.default_sclk;
947 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 948 rdev->pm.current_sclk = rdev->clock.default_sclk;
949 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 950 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 951
56278a8e
AD		 952 if (rdev->bios) {
953 if (rdev->is_atom_bios)
954 radeon_atombios_get_power_modes(rdev);
955 else
956 radeon_combios_get_power_modes(rdev);
f712d0c7 957 radeon_pm_print_states(rdev);
ce8f5370 958 radeon_pm_init_profile(rdev);
ed18a360 959 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10 960 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 961 (rdev->family <= CHIP_HAINAN) &&
2e3b3b10 962 rdev->mc_fw) {
ed18a360 963 if (rdev->pm.default_vddc)
8a83ec5e
AD		 964 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
965 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 966 if (rdev->pm.default_vddci)
967 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
968 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 969 if (rdev->pm.default_sclk)
970 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
971 if (rdev->pm.default_mclk)
972 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
973 }
56278a8e
AD		 974 }
975
21a8122a 976 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 977 ret = radeon_hwmon_init(rdev);
978 if (ret)
979 return ret;
32c87fca
TH		 980
981 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
982
ce8f5370 983 if (rdev->pm.num_power_states > 1) {
ce8f5370 984 /* where's the best place to put these? */
26481fb1
DA		 985 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
986 if (ret)
987 DRM_ERROR("failed to create device file for power profile\n");
988 ret = device_create_file(rdev->dev, &dev_attr_power_method);
989 if (ret)
990 DRM_ERROR("failed to create device file for power method\n");
a424816f 991
ce8f5370
AD		 992 if (radeon_debugfs_pm_init(rdev)) {
993 DRM_ERROR("Failed to register debugfs file for PM!\n");
994 }
c913e23a 995
ce8f5370
AD		 996 DRM_INFO("radeon: power management initialized\n");
997 }
c913e23a 998
7433874e
RM		 999 return 0;
1000}
1001
da321c8a
AD		 1002static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1003{
1004 int i;
1005
1006 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1007 printk("== power state %d ==\n", i);
1008 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1009 }
1010}
1011
1012static int radeon_pm_init_dpm(struct radeon_device *rdev)
1013{
1014 int ret;
1015
1016 /* default to performance state */
edcaa5b1
AD		 1017 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1018 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
da321c8a
AD		 1019 rdev->pm.default_sclk = rdev->clock.default_sclk;
1020 rdev->pm.default_mclk = rdev->clock.default_mclk;
1021 rdev->pm.current_sclk = rdev->clock.default_sclk;
1022 rdev->pm.current_mclk = rdev->clock.default_mclk;
1023 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1024
1025 if (rdev->bios && rdev->is_atom_bios)
1026 radeon_atombios_get_power_modes(rdev);
1027 else
1028 return -EINVAL;
1029
1030 /* set up the internal thermal sensor if applicable */
1031 ret = radeon_hwmon_init(rdev);
1032 if (ret)
1033 return ret;
1034
1035 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1036 mutex_lock(&rdev->pm.mutex);
1037 radeon_dpm_init(rdev);
1038 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1039 radeon_dpm_print_power_states(rdev);
1040 radeon_dpm_setup_asic(rdev);
1041 ret = radeon_dpm_enable(rdev);
1042 mutex_unlock(&rdev->pm.mutex);
1043 if (ret) {
1044 rdev->pm.dpm_enabled = false;
1045 if ((rdev->family >= CHIP_BARTS) &&
c6cf7777 1046 (rdev->family <= CHIP_HAINAN) &&
da321c8a
AD		 1047 rdev->mc_fw) {
1048 if (rdev->pm.default_vddc)
1049 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1050 SET_VOLTAGE_TYPE_ASIC_VDDC);
1051 if (rdev->pm.default_vddci)
1052 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1053 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1054 if (rdev->pm.default_sclk)
1055 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1056 if (rdev->pm.default_mclk)
1057 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1058 }
1059 DRM_ERROR("radeon: dpm initialization failed\n");
1060 return ret;
1061 }
1062 rdev->pm.dpm_enabled = true;
1063 radeon_pm_compute_clocks(rdev);
1064
1065 if (rdev->pm.num_power_states > 1) {
1066 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1067 if (ret)
1068 DRM_ERROR("failed to create device file for dpm state\n");
1069 /* XXX: these are noops for dpm but are here for backwards compat */
1070 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1071 if (ret)
1072 DRM_ERROR("failed to create device file for power profile\n");
1073 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1074 if (ret)
1075 DRM_ERROR("failed to create device file for power method\n");
1316b792
AD		 1076
1077 if (radeon_debugfs_pm_init(rdev)) {
1078 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1079 }
1080
da321c8a
AD		 1081 DRM_INFO("radeon: dpm initialized\n");
1082 }
1083
1084 return 0;
1085}
1086
1087int radeon_pm_init(struct radeon_device *rdev)
1088{
1089 /* enable dpm on rv6xx+ */
1090 switch (rdev->family) {
4a6369e9
AD		 1091 case CHIP_RV610:
1092 case CHIP_RV630:
1093 case CHIP_RV620:
1094 case CHIP_RV635:
1095 case CHIP_RV670:
9d67006e
AD		 1096 case CHIP_RS780:
1097 case CHIP_RS880:
66229b20
AD		 1098 case CHIP_RV770:
1099 case CHIP_RV730:
1100 case CHIP_RV710:
1101 case CHIP_RV740:
dc50ba7f
AD		 1102 case CHIP_CEDAR:
1103 case CHIP_REDWOOD:
1104 case CHIP_JUNIPER:
1105 case CHIP_CYPRESS:
1106 case CHIP_HEMLOCK:
80ea2c12
AD		 1107 case CHIP_PALM:
1108 case CHIP_SUMO:
1109 case CHIP_SUMO2:
6596afd4
AD		 1110 case CHIP_BARTS:
1111 case CHIP_TURKS:
1112 case CHIP_CAICOS:
69e0b57a 1113 case CHIP_CAYMAN:
d70229f7 1114 case CHIP_ARUBA:
a9e61410
AD		 1115 case CHIP_TAHITI:
1116 case CHIP_PITCAIRN:
1117 case CHIP_VERDE:
1118 case CHIP_OLAND:
1119 case CHIP_HAINAN:
9d67006e
AD		 1120 if (radeon_dpm == 1)
1121 rdev->pm.pm_method = PM_METHOD_DPM;
1122 else
1123 rdev->pm.pm_method = PM_METHOD_PROFILE;
1124 break;
da321c8a
AD		 1125 default:
1126 /* default to profile method */
1127 rdev->pm.pm_method = PM_METHOD_PROFILE;
1128 break;
1129 }
1130
1131 if (rdev->pm.pm_method == PM_METHOD_DPM)
1132 return radeon_pm_init_dpm(rdev);
1133 else
1134 return radeon_pm_init_old(rdev);
1135}
1136
1137static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1138{
ce8f5370 1139 if (rdev->pm.num_power_states > 1) {
a424816f 1140 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1141 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1142 rdev->pm.profile = PM_PROFILE_DEFAULT;
1143 radeon_pm_update_profile(rdev);
1144 radeon_pm_set_clocks(rdev);
1145 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1146 /* reset default clocks */
1147 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1148 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1149 radeon_pm_set_clocks(rdev);
1150 }
a424816f 1151 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1152
1153 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1154
ce8f5370
AD		 1155 device_remove_file(rdev->dev, &dev_attr_power_profile);
1156 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1157 }
a424816f 1158
0975b162
AD		 1159 if (rdev->pm.power_state)
1160 kfree(rdev->pm.power_state);
1161
21a8122a 1162 radeon_hwmon_fini(rdev);
29fb52ca
AD		 1163}
1164
da321c8a
AD		 1165static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1166{
1167 if (rdev->pm.num_power_states > 1) {
1168 mutex_lock(&rdev->pm.mutex);
1169 radeon_dpm_disable(rdev);
1170 mutex_unlock(&rdev->pm.mutex);
1171
1172 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1173 /* XXX backwards compat */
1174 device_remove_file(rdev->dev, &dev_attr_power_profile);
1175 device_remove_file(rdev->dev, &dev_attr_power_method);
1176 }
1177 radeon_dpm_fini(rdev);
1178
1179 if (rdev->pm.power_state)
1180 kfree(rdev->pm.power_state);
1181
1182 radeon_hwmon_fini(rdev);
1183}
1184
1185void radeon_pm_fini(struct radeon_device *rdev)
1186{
1187 if (rdev->pm.pm_method == PM_METHOD_DPM)
1188 radeon_pm_fini_dpm(rdev);
1189 else
1190 radeon_pm_fini_old(rdev);
1191}
1192
1193static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1194{
1195 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1196 struct drm_crtc *crtc;
c913e23a 1197 struct radeon_crtc *radeon_crtc;
c913e23a 1198
ce8f5370
AD		 1199 if (rdev->pm.num_power_states < 2)
1200 return;
1201
4a6369e9 1202 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
c913e23a
RM		 1203 mutex_lock(&rdev->pm.mutex);
1204
1205 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 1206 rdev->pm.active_crtc_count = 0;
1207 list_for_each_entry(crtc,
1208 &ddev->mode_config.crtc_list, head) {
1209 radeon_crtc = to_radeon_crtc(crtc);
1210 if (radeon_crtc->enabled) {
c913e23a 1211 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 1212 rdev->pm.active_crtc_count++;
c913e23a
RM		 1213 }
1214 }
1215
ce8f5370
AD		 1216 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1217 radeon_pm_update_profile(rdev);
1218 radeon_pm_set_clocks(rdev);
1219 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1220 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1221 if (rdev->pm.active_crtc_count > 1) {
1222 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1223 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1224
1225 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1226 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1227 radeon_pm_get_dynpm_state(rdev);
1228 radeon_pm_set_clocks(rdev);
1229
d9fdaafb 1230 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1231 }
1232 } else if (rdev->pm.active_crtc_count == 1) {
1233 /* TODO: Increase clocks if needed for current mode */
1234
1235 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1236 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1237 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1238 radeon_pm_get_dynpm_state(rdev);
1239 radeon_pm_set_clocks(rdev);
1240
32c87fca
TH		 1241 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1242 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1243 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1244 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1245 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1246 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1247 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1248 }
1249 } else { /* count == 0 */
1250 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1251 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1252
1253 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1254 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1255 radeon_pm_get_dynpm_state(rdev);
1256 radeon_pm_set_clocks(rdev);
1257 }
1258 }
c913e23a 1259 }
c913e23a 1260 }
73a6d3fc
RM		 1261
1262 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1263}
1264
da321c8a
AD		 1265static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1266{
1267 struct drm_device *ddev = rdev->ddev;
1268 struct drm_crtc *crtc;
1269 struct radeon_crtc *radeon_crtc;
1270
1271 mutex_lock(&rdev->pm.mutex);
1272
5ca302f7 1273 /* update active crtc counts */
da321c8a
AD		 1274 rdev->pm.dpm.new_active_crtcs = 0;
1275 rdev->pm.dpm.new_active_crtc_count = 0;
1276 list_for_each_entry(crtc,
1277 &ddev->mode_config.crtc_list, head) {
1278 radeon_crtc = to_radeon_crtc(crtc);
1279 if (crtc->enabled) {
1280 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1281 rdev->pm.dpm.new_active_crtc_count++;
1282 }
1283 }
1284
5ca302f7
AD		 1285 /* update battery/ac status */
1286 if (power_supply_is_system_supplied() > 0)
1287 rdev->pm.dpm.ac_power = true;
1288 else
1289 rdev->pm.dpm.ac_power = false;
1290
da321c8a
AD		 1291 radeon_dpm_change_power_state_locked(rdev);
1292
1293 mutex_unlock(&rdev->pm.mutex);
8a227555 1294
da321c8a
AD		 1295}
1296
1297void radeon_pm_compute_clocks(struct radeon_device *rdev)
1298{
1299 if (rdev->pm.pm_method == PM_METHOD_DPM)
1300 radeon_pm_compute_clocks_dpm(rdev);
1301 else
1302 radeon_pm_compute_clocks_old(rdev);
1303}
1304
ce8f5370 1305static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1306{
75fa0b08 1307 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1308 bool in_vbl = true;
1309
75fa0b08
MK		 1310 /* Iterate over all active crtc's. All crtc's must be in vblank,
1311 * otherwise return in_vbl == false.
1312 */
1313 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1314 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 1315 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1316 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1317 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1318 in_vbl = false;
1319 }
1320 }
f81f2024
MG		 1321
1322 return in_vbl;
1323}
1324
ce8f5370 1325static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1326{
1327 u32 stat_crtc = 0;
1328 bool in_vbl = radeon_pm_in_vbl(rdev);
1329
f735261b 1330 if (in_vbl == false)
d9fdaafb 1331 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1332 finish ? "exit" : "entry");
f735261b
DA		 1333 return in_vbl;
1334}
c913e23a 1335
ce8f5370 1336static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1337{
1338 struct radeon_device *rdev;
d9932a32 1339 int resched;
c913e23a 1340 rdev = container_of(work, struct radeon_device,
ce8f5370 1341 pm.dynpm_idle_work.work);
c913e23a 1342
d9932a32 1343 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1344 mutex_lock(&rdev->pm.mutex);
ce8f5370 1345 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1346 int not_processed = 0;
7465280c
AD		 1347 int i;
1348
7465280c 1349 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1350 struct radeon_ring *ring = &rdev->ring[i];
1351
1352 if (ring->ready) {
1353 not_processed += radeon_fence_count_emitted(rdev, i);
1354 if (not_processed >= 3)
1355 break;
1356 }
c913e23a 1357 }
c913e23a
RM		 1358
1359 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1360 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1361 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1362 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1363 rdev->pm.dynpm_can_upclock) {
1364 rdev->pm.dynpm_planned_action =
1365 DYNPM_ACTION_UPCLOCK;
1366 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1367 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1368 }
1369 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1370 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1371 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1372 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1373 rdev->pm.dynpm_can_downclock) {
1374 rdev->pm.dynpm_planned_action =
1375 DYNPM_ACTION_DOWNCLOCK;
1376 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1377 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1378 }
1379 }
1380
d7311171
AD		 1381 /* Note, radeon_pm_set_clocks is called with static_switch set
1382 * to false since we want to wait for vbl to avoid flicker.
1383 */
ce8f5370
AD		 1384 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1385 jiffies > rdev->pm.dynpm_action_timeout) {
1386 radeon_pm_get_dynpm_state(rdev);
1387 radeon_pm_set_clocks(rdev);
c913e23a 1388 }
3f53eb6f 1389
32c87fca
TH		 1390 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1391 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1392 }
1393 mutex_unlock(&rdev->pm.mutex);
d9932a32 1394 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1395}
1396
7433874e
RM		 1397/*
1398 * Debugfs info
1399 */
1400#if defined(CONFIG_DEBUG_FS)
1401
1402static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1403{
1404 struct drm_info_node *node = (struct drm_info_node *) m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct radeon_device *rdev = dev->dev_private;
1407
1316b792
AD		 1408 if (rdev->pm.dpm_enabled) {
1409 mutex_lock(&rdev->pm.mutex);
1410 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1411 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1412 else
71375929 1413 seq_printf(m, "Debugfs support not implemented for this asic\n");
1316b792
AD		 1414 mutex_unlock(&rdev->pm.mutex);
1415 } else {
1416 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1417 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1418 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1419 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1420 else
1421 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1422 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1423 if (rdev->asic->pm.get_memory_clock)
1424 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1425 if (rdev->pm.current_vddc)
1426 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1427 if (rdev->asic->pm.get_pcie_lanes)
1428 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1429 }
7433874e
RM		 1430
1431 return 0;
1432}
1433
1434static struct drm_info_list radeon_pm_info_list[] = {
1435 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1436};
1437#endif
1438
c913e23a 1439static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1440{
1441#if defined(CONFIG_DEBUG_FS)
1442 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1443#else
1444 return 0;
1445#endif
1446}
Linux kernel - Deliverables
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