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drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
ce8f5370
AD		 26#ifdef CONFIG_ACPI
27#include <linux/acpi.h>
28#endif
29#include <linux/power_supply.h>
21a8122a
AD		 30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
7433874e 32
c913e23a
RM		 33#define RADEON_IDLE_LOOP_MS 100
34#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 35#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 36#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 37
f712d0c7
RM		 38static const char *radeon_pm_state_type_name[5] = {
39 "Default",
40 "Powersave",
41 "Battery",
42 "Balanced",
43 "Performance",
44};
45
ce8f5370 46static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 47static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 48static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50static void radeon_pm_update_profile(struct radeon_device *rdev);
51static void radeon_pm_set_clocks(struct radeon_device *rdev);
52
53#define ACPI_AC_CLASS "ac_adapter"
54
55#ifdef CONFIG_ACPI
56static int radeon_acpi_event(struct notifier_block *nb,
57 unsigned long val,
58 void *data)
59{
60 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
61 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
62
63 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
64 if (power_supply_is_system_supplied() > 0)
d9fdaafb 65 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 66 else
d9fdaafb 67 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 68
69 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
70 if (rdev->pm.profile == PM_PROFILE_AUTO) {
71 mutex_lock(&rdev->pm.mutex);
72 radeon_pm_update_profile(rdev);
73 radeon_pm_set_clocks(rdev);
74 mutex_unlock(&rdev->pm.mutex);
75 }
76 }
77 }
78
79 return NOTIFY_OK;
80}
81#endif
82
83static void radeon_pm_update_profile(struct radeon_device *rdev)
84{
85 switch (rdev->pm.profile) {
86 case PM_PROFILE_DEFAULT:
87 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
88 break;
89 case PM_PROFILE_AUTO:
90 if (power_supply_is_system_supplied() > 0) {
91 if (rdev->pm.active_crtc_count > 1)
92 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
93 else
94 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
95 } else {
96 if (rdev->pm.active_crtc_count > 1)
c9e75b21 97 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 98 else
c9e75b21 99 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 100 }
101 break;
102 case PM_PROFILE_LOW:
103 if (rdev->pm.active_crtc_count > 1)
104 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
105 else
106 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
107 break;
c9e75b21
AD		 108 case PM_PROFILE_MID:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
113 break;
ce8f5370
AD		 114 case PM_PROFILE_HIGH:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119 break;
120 }
121
122 if (rdev->pm.active_crtc_count == 0) {
123 rdev->pm.requested_power_state_index =
124 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
125 rdev->pm.requested_clock_mode_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
127 } else {
128 rdev->pm.requested_power_state_index =
129 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
130 rdev->pm.requested_clock_mode_index =
131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132 }
133}
c913e23a 134
5876dd24
MG		 135static void radeon_unmap_vram_bos(struct radeon_device *rdev)
136{
137 struct radeon_bo *bo, *n;
138
139 if (list_empty(&rdev->gem.objects))
140 return;
141
142 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
143 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
144 ttm_bo_unmap_virtual(&bo->tbo);
145 }
5876dd24
MG		 146}
147
ce8f5370 148static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 149{
ce8f5370
AD		 150 if (rdev->pm.active_crtcs) {
151 rdev->pm.vblank_sync = false;
152 wait_event_timeout(
153 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
154 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
155 }
156}
157
158static void radeon_set_power_state(struct radeon_device *rdev)
159{
160 u32 sclk, mclk;
92645879 161 bool misc_after = false;
ce8f5370
AD		 162
163 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
164 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
165 return;
166
167 if (radeon_gui_idle(rdev)) {
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 170 if (sclk > rdev->pm.default_sclk)
171 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 172
173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
174 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 175 if (mclk > rdev->pm.default_mclk)
176 mclk = rdev->pm.default_mclk;
ce8f5370 177
92645879
AD		 178 /* upvolt before raising clocks, downvolt after lowering clocks */
179 if (sclk < rdev->pm.current_sclk)
180 misc_after = true;
ce8f5370 181
92645879 182 radeon_sync_with_vblank(rdev);
ce8f5370 183
92645879 184 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 185 if (!radeon_pm_in_vbl(rdev))
186 return;
92645879 187 }
ce8f5370 188
92645879 189 radeon_pm_prepare(rdev);
ce8f5370 190
92645879
AD		 191 if (!misc_after)
192 /* voltage, pcie lanes, etc.*/
193 radeon_pm_misc(rdev);
194
195 /* set engine clock */
196 if (sclk != rdev->pm.current_sclk) {
197 radeon_pm_debug_check_in_vbl(rdev, false);
198 radeon_set_engine_clock(rdev, sclk);
199 radeon_pm_debug_check_in_vbl(rdev, true);
200 rdev->pm.current_sclk = sclk;
d9fdaafb 201 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 202 }
203
204 /* set memory clock */
205 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
206 radeon_pm_debug_check_in_vbl(rdev, false);
207 radeon_set_memory_clock(rdev, mclk);
208 radeon_pm_debug_check_in_vbl(rdev, true);
209 rdev->pm.current_mclk = mclk;
d9fdaafb 210 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 211 }
2aba631c 212
92645879
AD		 213 if (misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 radeon_pm_finish(rdev);
218
ce8f5370
AD		 219 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
220 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
221 } else
d9fdaafb 222 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 223}
224
225static void radeon_pm_set_clocks(struct radeon_device *rdev)
226{
227 int i;
c37d230a 228
4e186b2d
AD		 229 /* no need to take locks, etc. if nothing's going to change */
230 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
231 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
232 return;
233
612e06ce
MG		 234 mutex_lock(&rdev->ddev->struct_mutex);
235 mutex_lock(&rdev->vram_mutex);
a424816f 236 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 237
238 /* gui idle int has issues on older chips it seems */
239 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 240 if (rdev->irq.installed) {
241 /* wait for GPU idle */
242 rdev->pm.gui_idle = false;
243 rdev->irq.gui_idle = true;
244 radeon_irq_set(rdev);
245 wait_event_interruptible_timeout(
246 rdev->irq.idle_queue, rdev->pm.gui_idle,
247 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
248 rdev->irq.gui_idle = false;
249 radeon_irq_set(rdev);
250 }
01434b4b 251 } else {
ce8f5370
AD		 252 if (rdev->cp.ready) {
253 struct radeon_fence *fence;
254 radeon_ring_alloc(rdev, 64);
255 radeon_fence_create(rdev, &fence);
256 radeon_fence_emit(rdev, fence);
257 radeon_ring_commit(rdev);
258 radeon_fence_wait(fence, false);
259 radeon_fence_unref(&fence);
260 }
4f3218cb 261 }
5876dd24
MG		 262 radeon_unmap_vram_bos(rdev);
263
ce8f5370 264 if (rdev->irq.installed) {
2aba631c
MG		 265 for (i = 0; i < rdev->num_crtc; i++) {
266 if (rdev->pm.active_crtcs & (1 << i)) {
267 rdev->pm.req_vblank |= (1 << i);
268 drm_vblank_get(rdev->ddev, i);
269 }
270 }
271 }
539d2418 272
ce8f5370 273 radeon_set_power_state(rdev);
2aba631c 274
ce8f5370 275 if (rdev->irq.installed) {
2aba631c
MG		 276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.req_vblank & (1 << i)) {
278 rdev->pm.req_vblank &= ~(1 << i);
279 drm_vblank_put(rdev->ddev, i);
280 }
281 }
282 }
5876dd24 283
a424816f
AD		 284 /* update display watermarks based on new power state */
285 radeon_update_bandwidth_info(rdev);
286 if (rdev->pm.active_crtc_count)
287 radeon_bandwidth_update(rdev);
288
ce8f5370 289 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 290
a424816f 291 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 292 mutex_unlock(&rdev->vram_mutex);
293 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 294}
295
f712d0c7
RM		 296static void radeon_pm_print_states(struct radeon_device *rdev)
297{
298 int i, j;
299 struct radeon_power_state *power_state;
300 struct radeon_pm_clock_info *clock_info;
301
d9fdaafb 302 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 303 for (i = 0; i < rdev->pm.num_power_states; i++) {
304 power_state = &rdev->pm.power_state[i];
d9fdaafb 305 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 306 radeon_pm_state_type_name[power_state->type]);
307 if (i == rdev->pm.default_power_state_index)
d9fdaafb 308 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 309 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 310 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 311 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 312 DRM_DEBUG_DRIVER("\tSingle display only\n");
313 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 314 for (j = 0; j < power_state->num_clock_modes; j++) {
315 clock_info = &(power_state->clock_info[j]);
316 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 317 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 318 j,
319 clock_info->sclk * 10,
320 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
321 else
d9fdaafb 322 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 323 j,
324 clock_info->sclk * 10,
325 clock_info->mclk * 10,
326 clock_info->voltage.voltage,
327 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
368 DRM_ERROR("invalid power profile!\n");
369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
373 }
374fail:
a424816f
AD		 375 mutex_unlock(&rdev->pm.mutex);
376
377 return count;
378}
379
ce8f5370
AD		 380static ssize_t radeon_get_pm_method(struct device *dev,
381 struct device_attribute *attr,
382 char *buf)
a424816f
AD		 383{
384 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
385 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 386 int pm = rdev->pm.pm_method;
a424816f
AD		 387
388 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 389 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 390}
391
ce8f5370
AD		 392static ssize_t radeon_set_pm_method(struct device *dev,
393 struct device_attribute *attr,
394 const char *buf,
395 size_t count)
a424816f
AD		 396{
397 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
398 struct radeon_device *rdev = ddev->dev_private;
a424816f 399
ce8f5370
AD		 400
401 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 402 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 403 rdev->pm.pm_method = PM_METHOD_DYNPM;
404 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
405 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 406 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 407 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
408 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 409 /* disable dynpm */
410 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
411 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 412 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 413 mutex_unlock(&rdev->pm.mutex);
32c87fca 414 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370
AD		 415 } else {
416 DRM_ERROR("invalid power method!\n");
417 goto fail;
418 }
419 radeon_pm_compute_clocks(rdev);
420fail:
a424816f
AD		 421 return count;
422}
423
ce8f5370
AD		 424static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
425static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 426
21a8122a
AD		 427static ssize_t radeon_hwmon_show_temp(struct device *dev,
428 struct device_attribute *attr,
429 char *buf)
430{
431 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
432 struct radeon_device *rdev = ddev->dev_private;
433 u32 temp;
434
435 switch (rdev->pm.int_thermal_type) {
436 case THERMAL_TYPE_RV6XX:
437 temp = rv6xx_get_temp(rdev);
438 break;
439 case THERMAL_TYPE_RV770:
440 temp = rv770_get_temp(rdev);
441 break;
442 case THERMAL_TYPE_EVERGREEN:
4fddba1f 443 case THERMAL_TYPE_NI:
21a8122a
AD		 444 temp = evergreen_get_temp(rdev);
445 break;
e33df25f
AD		 446 case THERMAL_TYPE_SUMO:
447 temp = sumo_get_temp(rdev);
448 break;
21a8122a
AD		 449 default:
450 temp = 0;
451 break;
452 }
453
454 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
455}
456
457static ssize_t radeon_hwmon_show_name(struct device *dev,
458 struct device_attribute *attr,
459 char *buf)
460{
461 return sprintf(buf, "radeon\n");
462}
463
464static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
465static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
466
467static struct attribute *hwmon_attributes[] = {
468 &sensor_dev_attr_temp1_input.dev_attr.attr,
469 &sensor_dev_attr_name.dev_attr.attr,
470 NULL
471};
472
473static const struct attribute_group hwmon_attrgroup = {
474 .attrs = hwmon_attributes,
475};
476
0d18abed 477static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 478{
0d18abed 479 int err = 0;
21a8122a
AD		 480
481 rdev->pm.int_hwmon_dev = NULL;
482
483 switch (rdev->pm.int_thermal_type) {
484 case THERMAL_TYPE_RV6XX:
485 case THERMAL_TYPE_RV770:
486 case THERMAL_TYPE_EVERGREEN:
e33df25f 487 case THERMAL_TYPE_SUMO:
21a8122a 488 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 489 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
490 err = PTR_ERR(rdev->pm.int_hwmon_dev);
491 dev_err(rdev->dev,
492 "Unable to register hwmon device: %d\n", err);
493 break;
494 }
21a8122a
AD		 495 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
496 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
497 &hwmon_attrgroup);
0d18abed
DC		 498 if (err) {
499 dev_err(rdev->dev,
500 "Unable to create hwmon sysfs file: %d\n", err);
501 hwmon_device_unregister(rdev->dev);
502 }
21a8122a
AD		 503 break;
504 default:
505 break;
506 }
0d18abed
DC		 507
508 return err;
21a8122a
AD		 509}
510
511static void radeon_hwmon_fini(struct radeon_device *rdev)
512{
513 if (rdev->pm.int_hwmon_dev) {
514 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
515 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
516 }
517}
518
ce8f5370 519void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 520{
ce8f5370 521 mutex_lock(&rdev->pm.mutex);
3f53eb6f 522 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 523 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
524 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 525 }
ce8f5370 526 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 527
528 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 529}
530
ce8f5370 531void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 532{
f8ed8b4c
AD		 533 /* asic init will reset the default power state */
534 mutex_lock(&rdev->pm.mutex);
535 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
536 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 537 rdev->pm.current_sclk = rdev->pm.default_sclk;
538 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 539 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
3f53eb6f
RW		 540 if (rdev->pm.pm_method == PM_METHOD_DYNPM
541 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
542 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 543 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
544 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 545 }
f8ed8b4c 546 mutex_unlock(&rdev->pm.mutex);
ce8f5370 547 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 548}
549
7433874e
RM		 550int radeon_pm_init(struct radeon_device *rdev)
551{
26481fb1 552 int ret;
0d18abed 553
ce8f5370
AD		 554 /* default to profile method */
555 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 556 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 557 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
558 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
559 rdev->pm.dynpm_can_upclock = true;
560 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 561 rdev->pm.default_sclk = rdev->clock.default_sclk;
562 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 563 rdev->pm.current_sclk = rdev->clock.default_sclk;
564 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 565 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 566
56278a8e
AD		 567 if (rdev->bios) {
568 if (rdev->is_atom_bios)
569 radeon_atombios_get_power_modes(rdev);
570 else
571 radeon_combios_get_power_modes(rdev);
f712d0c7 572 radeon_pm_print_states(rdev);
ce8f5370 573 radeon_pm_init_profile(rdev);
56278a8e
AD		 574 }
575
21a8122a 576 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 577 ret = radeon_hwmon_init(rdev);
578 if (ret)
579 return ret;
32c87fca
TH		 580
581 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
582
ce8f5370 583 if (rdev->pm.num_power_states > 1) {
ce8f5370 584 /* where's the best place to put these? */
26481fb1
DA		 585 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
586 if (ret)
587 DRM_ERROR("failed to create device file for power profile\n");
588 ret = device_create_file(rdev->dev, &dev_attr_power_method);
589 if (ret)
590 DRM_ERROR("failed to create device file for power method\n");
a424816f 591
ce8f5370
AD		 592#ifdef CONFIG_ACPI
593 rdev->acpi_nb.notifier_call = radeon_acpi_event;
594 register_acpi_notifier(&rdev->acpi_nb);
595#endif
ce8f5370
AD		 596 if (radeon_debugfs_pm_init(rdev)) {
597 DRM_ERROR("Failed to register debugfs file for PM!\n");
598 }
c913e23a 599
ce8f5370
AD		 600 DRM_INFO("radeon: power management initialized\n");
601 }
c913e23a 602
7433874e
RM		 603 return 0;
604}
605
29fb52ca
AD		 606void radeon_pm_fini(struct radeon_device *rdev)
607{
ce8f5370 608 if (rdev->pm.num_power_states > 1) {
a424816f 609 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 610 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
611 rdev->pm.profile = PM_PROFILE_DEFAULT;
612 radeon_pm_update_profile(rdev);
613 radeon_pm_set_clocks(rdev);
614 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 615 /* reset default clocks */
616 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
617 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
618 radeon_pm_set_clocks(rdev);
619 }
a424816f 620 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 621
622 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 623
ce8f5370
AD		 624 device_remove_file(rdev->dev, &dev_attr_power_profile);
625 device_remove_file(rdev->dev, &dev_attr_power_method);
626#ifdef CONFIG_ACPI
627 unregister_acpi_notifier(&rdev->acpi_nb);
628#endif
629 }
a424816f 630
21a8122a 631 radeon_hwmon_fini(rdev);
29fb52ca
AD		 632}
633
c913e23a
RM		 634void radeon_pm_compute_clocks(struct radeon_device *rdev)
635{
636 struct drm_device *ddev = rdev->ddev;
a48b9b4e 637 struct drm_crtc *crtc;
c913e23a 638 struct radeon_crtc *radeon_crtc;
c913e23a 639
ce8f5370
AD		 640 if (rdev->pm.num_power_states < 2)
641 return;
642
c913e23a
RM		 643 mutex_lock(&rdev->pm.mutex);
644
645 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 646 rdev->pm.active_crtc_count = 0;
647 list_for_each_entry(crtc,
648 &ddev->mode_config.crtc_list, head) {
649 radeon_crtc = to_radeon_crtc(crtc);
650 if (radeon_crtc->enabled) {
c913e23a 651 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 652 rdev->pm.active_crtc_count++;
c913e23a
RM		 653 }
654 }
655
ce8f5370
AD		 656 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
657 radeon_pm_update_profile(rdev);
658 radeon_pm_set_clocks(rdev);
659 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
660 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
661 if (rdev->pm.active_crtc_count > 1) {
662 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
663 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
664
665 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
666 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
667 radeon_pm_get_dynpm_state(rdev);
668 radeon_pm_set_clocks(rdev);
669
d9fdaafb 670 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 671 }
672 } else if (rdev->pm.active_crtc_count == 1) {
673 /* TODO: Increase clocks if needed for current mode */
674
675 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
676 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
677 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
678 radeon_pm_get_dynpm_state(rdev);
679 radeon_pm_set_clocks(rdev);
680
32c87fca
TH		 681 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
682 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 683 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
684 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 685 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
686 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 687 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 688 }
689 } else { /* count == 0 */
690 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
691 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
692
693 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
694 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
695 radeon_pm_get_dynpm_state(rdev);
696 radeon_pm_set_clocks(rdev);
697 }
698 }
c913e23a 699 }
c913e23a 700 }
73a6d3fc
RM		 701
702 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 703}
704
ce8f5370 705static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 706{
75fa0b08 707 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 708 bool in_vbl = true;
709
75fa0b08
MK		 710 /* Iterate over all active crtc's. All crtc's must be in vblank,
711 * otherwise return in_vbl == false.
712 */
713 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
714 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 715 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
716 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
717 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 718 in_vbl = false;
719 }
720 }
f81f2024
MG		 721
722 return in_vbl;
723}
724
ce8f5370 725static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 726{
727 u32 stat_crtc = 0;
728 bool in_vbl = radeon_pm_in_vbl(rdev);
729
f735261b 730 if (in_vbl == false)
d9fdaafb 731 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 732 finish ? "exit" : "entry");
f735261b
DA		 733 return in_vbl;
734}
c913e23a 735
ce8f5370 736static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 737{
738 struct radeon_device *rdev;
d9932a32 739 int resched;
c913e23a 740 rdev = container_of(work, struct radeon_device,
ce8f5370 741 pm.dynpm_idle_work.work);
c913e23a 742
d9932a32 743 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 744 mutex_lock(&rdev->pm.mutex);
ce8f5370 745 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 746 unsigned long irq_flags;
747 int not_processed = 0;
748
749 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
750 if (!list_empty(&rdev->fence_drv.emited)) {
751 struct list_head *ptr;
752 list_for_each(ptr, &rdev->fence_drv.emited) {
753 /* count up to 3, that's enought info */
754 if (++not_processed >= 3)
755 break;
756 }
757 }
758 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
759
760 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 761 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
762 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
763 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
764 rdev->pm.dynpm_can_upclock) {
765 rdev->pm.dynpm_planned_action =
766 DYNPM_ACTION_UPCLOCK;
767 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 768 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
769 }
770 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 771 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
772 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
773 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
774 rdev->pm.dynpm_can_downclock) {
775 rdev->pm.dynpm_planned_action =
776 DYNPM_ACTION_DOWNCLOCK;
777 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 778 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
779 }
780 }
781
d7311171
AD		 782 /* Note, radeon_pm_set_clocks is called with static_switch set
783 * to false since we want to wait for vbl to avoid flicker.
784 */
ce8f5370
AD		 785 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
786 jiffies > rdev->pm.dynpm_action_timeout) {
787 radeon_pm_get_dynpm_state(rdev);
788 radeon_pm_set_clocks(rdev);
c913e23a 789 }
3f53eb6f 790
32c87fca
TH		 791 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
792 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 793 }
794 mutex_unlock(&rdev->pm.mutex);
d9932a32 795 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 796}
797
7433874e
RM		 798/*
799 * Debugfs info
800 */
801#if defined(CONFIG_DEBUG_FS)
802
803static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
804{
805 struct drm_info_node *node = (struct drm_info_node *) m->private;
806 struct drm_device *dev = node->minor->dev;
807 struct radeon_device *rdev = dev->dev_private;
808
9ace9f7b 809 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 810 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 811 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
6234077d
RM		 812 if (rdev->asic->get_memory_clock)
813 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 814 if (rdev->pm.current_vddc)
815 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 816 if (rdev->asic->get_pcie_lanes)
817 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 818
819 return 0;
820}
821
822static struct drm_info_list radeon_pm_info_list[] = {
823 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
824};
825#endif
826
c913e23a 827static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 828{
829#if defined(CONFIG_DEBUG_FS)
830 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
831#else
832 return 0;
833#endif
834}
Linux kernel - Deliverables
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