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drm/radeon/dpm: fixup dynamic state adjust for btc (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370 27#include <linux/power_supply.h>
21a8122a
AD		 28#include <linux/hwmon.h>
29#include <linux/hwmon-sysfs.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 34
f712d0c7 35static const char *radeon_pm_state_type_name[5] = {
eb2c27a0 36 "",
f712d0c7
RM		 37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41};
42
ce8f5370 43static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 44static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 45static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47static void radeon_pm_update_profile(struct radeon_device *rdev);
48static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
a4c9e2ee
AD		 50int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53{
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66}
67
c4917074 68void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
ce8f5370 69{
c4917074
AD		 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 76 }
77 }
ce8f5370 78}
ce8f5370
AD		 79
80static void radeon_pm_update_profile(struct radeon_device *rdev)
81{
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
85 break;
86 case PM_PROFILE_AUTO:
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
90 else
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
92 } else {
93 if (rdev->pm.active_crtc_count > 1)
c9e75b21 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 95 else
c9e75b21 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 97 }
98 break;
99 case PM_PROFILE_LOW:
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
104 break;
c9e75b21
AD		 105 case PM_PROFILE_MID:
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
110 break;
ce8f5370
AD		 111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
116 break;
117 }
118
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
124 } else {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
129 }
130}
c913e23a 131
5876dd24
MG		 132static void radeon_unmap_vram_bos(struct radeon_device *rdev)
133{
134 struct radeon_bo *bo, *n;
135
136 if (list_empty(&rdev->gem.objects))
137 return;
138
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
142 }
5876dd24
MG		 143}
144
ce8f5370 145static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 146{
ce8f5370
AD		 147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
149 wait_event_timeout(
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
152 }
153}
154
155static void radeon_set_power_state(struct radeon_device *rdev)
156{
157 u32 sclk, mclk;
92645879 158 bool misc_after = false;
ce8f5370
AD		 159
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
162 return;
163
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
ce8f5370 169
27810fb2
AD		 170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
7ae764b1 172 * mclk and vddci.
27810fb2
AD		 173 */
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
181 else
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
184
9ace9f7b
AD		 185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
ce8f5370 187
92645879
AD		 188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
190 misc_after = true;
ce8f5370 191
92645879 192 radeon_sync_with_vblank(rdev);
ce8f5370 193
92645879 194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 195 if (!radeon_pm_in_vbl(rdev))
196 return;
92645879 197 }
ce8f5370 198
92645879 199 radeon_pm_prepare(rdev);
ce8f5370 200
92645879
AD		 201 if (!misc_after)
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
204
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
d9fdaafb 211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 212 }
213
214 /* set memory clock */
798bcf73 215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 221 }
2aba631c 222
92645879
AD		 223 if (misc_after)
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
226
227 radeon_pm_finish(rdev);
228
ce8f5370
AD		 229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
231 } else
d9fdaafb 232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 233}
234
235static void radeon_pm_set_clocks(struct radeon_device *rdev)
236{
5f8f635e 237 int i, r;
c37d230a 238
4e186b2d
AD		 239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
242 return;
243
612e06ce 244 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 245 down_write(&rdev->pm.mclk_lock);
d6999bc7 246 mutex_lock(&rdev->ring_lock);
4f3218cb 247
95f5a3ac
AD		 248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
5f8f635e
JG		 251 if (!ring->ready) {
252 continue;
253 }
254 r = radeon_fence_wait_empty_locked(rdev, i);
255 if (r) {
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
260 return;
261 }
4f3218cb 262 }
95f5a3ac 263
5876dd24
MG		 264 radeon_unmap_vram_bos(rdev);
265
ce8f5370 266 if (rdev->irq.installed) {
2aba631c
MG		 267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
271 }
272 }
273 }
539d2418 274
ce8f5370 275 radeon_set_power_state(rdev);
2aba631c 276
ce8f5370 277 if (rdev->irq.installed) {
2aba631c
MG		 278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
282 }
283 }
284 }
5876dd24 285
a424816f
AD		 286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
290
ce8f5370 291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 292
d6999bc7 293 mutex_unlock(&rdev->ring_lock);
db7fce39 294 up_write(&rdev->pm.mclk_lock);
612e06ce 295 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 296}
297
f712d0c7
RM		 298static void radeon_pm_print_states(struct radeon_device *rdev)
299{
300 int i, j;
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
303
d9fdaafb 304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
d9fdaafb 307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
d9fdaafb 310 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
eb2c27a0
AD		 319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
320 j,
321 clock_info->sclk * 10);
f712d0c7 322 else
eb2c27a0
AD		 323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
324 j,
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
f712d0c7
RM		 328 }
329 }
330}
331
ce8f5370
AD		 332static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
334 char *buf)
a424816f
AD		 335{
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 338 int cp = rdev->pm.profile;
a424816f 339
ce8f5370
AD		 340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 343 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 345}
346
ce8f5370
AD		 347static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
349 const char *buf,
350 size_t count)
a424816f
AD		 351{
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 354
355 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
367 else {
1783e4bf 368 count = -EINVAL;
ce8f5370 369 goto fail;
a424816f 370 }
ce8f5370
AD		 371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 373 } else
374 count = -EINVAL;
375
ce8f5370 376fail:
a424816f
AD		 377 mutex_unlock(&rdev->pm.mutex);
378
379 return count;
380}
381
ce8f5370
AD		 382static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
384 char *buf)
a424816f
AD		 385{
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 388 int pm = rdev->pm.pm_method;
a424816f
AD		 389
390 return snprintf(buf, PAGE_SIZE, "%s\n",
da321c8a
AD		 391 (pm == PM_METHOD_DYNPM) ? "dynpm" :
392 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
a424816f
AD		 393}
394
ce8f5370
AD		 395static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t count)
a424816f
AD		 399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
a424816f 402
da321c8a
AD		 403 /* we don't support the legacy modes with dpm */
404 if (rdev->pm.pm_method == PM_METHOD_DPM) {
405 count = -EINVAL;
406 goto fail;
407 }
ce8f5370
AD		 408
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 410 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 414 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 417 /* disable dynpm */
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 420 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 421 mutex_unlock(&rdev->pm.mutex);
32c87fca 422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 423 } else {
1783e4bf 424 count = -EINVAL;
ce8f5370
AD		 425 goto fail;
426 }
427 radeon_pm_compute_clocks(rdev);
428fail:
a424816f
AD		 429 return count;
430}
431
da321c8a
AD		 432static ssize_t radeon_get_dpm_state(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435{
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
438 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
439
440 return snprintf(buf, PAGE_SIZE, "%s\n",
441 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
442 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
443}
444
445static ssize_t radeon_set_dpm_state(struct device *dev,
446 struct device_attribute *attr,
447 const char *buf,
448 size_t count)
449{
450 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
451 struct radeon_device *rdev = ddev->dev_private;
452
453 mutex_lock(&rdev->pm.mutex);
454 if (strncmp("battery", buf, strlen("battery")) == 0)
455 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
456 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
457 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
458 else if (strncmp("performance", buf, strlen("performance")) == 0)
459 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
460 else {
461 mutex_unlock(&rdev->pm.mutex);
462 count = -EINVAL;
463 goto fail;
464 }
465 mutex_unlock(&rdev->pm.mutex);
466 radeon_pm_compute_clocks(rdev);
467fail:
468 return count;
469}
470
ce8f5370
AD		 471static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
472static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
da321c8a 473static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
a424816f 474
21a8122a
AD		 475static ssize_t radeon_hwmon_show_temp(struct device *dev,
476 struct device_attribute *attr,
477 char *buf)
478{
479 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
480 struct radeon_device *rdev = ddev->dev_private;
20d391d7 481 int temp;
21a8122a 482
6bd1c385
AD		 483 if (rdev->asic->pm.get_temperature)
484 temp = radeon_get_temperature(rdev);
485 else
21a8122a 486 temp = 0;
21a8122a
AD		 487
488 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
489}
490
491static ssize_t radeon_hwmon_show_name(struct device *dev,
492 struct device_attribute *attr,
493 char *buf)
494{
495 return sprintf(buf, "radeon\n");
496}
497
498static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
499static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
500
501static struct attribute *hwmon_attributes[] = {
502 &sensor_dev_attr_temp1_input.dev_attr.attr,
503 &sensor_dev_attr_name.dev_attr.attr,
504 NULL
505};
506
507static const struct attribute_group hwmon_attrgroup = {
508 .attrs = hwmon_attributes,
509};
510
0d18abed 511static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 512{
0d18abed 513 int err = 0;
21a8122a
AD		 514
515 rdev->pm.int_hwmon_dev = NULL;
516
517 switch (rdev->pm.int_thermal_type) {
518 case THERMAL_TYPE_RV6XX:
519 case THERMAL_TYPE_RV770:
520 case THERMAL_TYPE_EVERGREEN:
457558ed 521 case THERMAL_TYPE_NI:
e33df25f 522 case THERMAL_TYPE_SUMO:
1bd47d2e 523 case THERMAL_TYPE_SI:
6bd1c385 524 if (rdev->asic->pm.get_temperature == NULL)
5d7486c7 525 return err;
21a8122a 526 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 527 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
528 err = PTR_ERR(rdev->pm.int_hwmon_dev);
529 dev_err(rdev->dev,
530 "Unable to register hwmon device: %d\n", err);
531 break;
532 }
21a8122a
AD		 533 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
534 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
535 &hwmon_attrgroup);
0d18abed
DC		 536 if (err) {
537 dev_err(rdev->dev,
538 "Unable to create hwmon sysfs file: %d\n", err);
539 hwmon_device_unregister(rdev->dev);
540 }
21a8122a
AD		 541 break;
542 default:
543 break;
544 }
0d18abed
DC		 545
546 return err;
21a8122a
AD		 547}
548
549static void radeon_hwmon_fini(struct radeon_device *rdev)
550{
551 if (rdev->pm.int_hwmon_dev) {
552 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
553 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
554 }
555}
556
da321c8a
AD		 557static void radeon_dpm_thermal_work_handler(struct work_struct *work)
558{
559 struct radeon_device *rdev =
560 container_of(work, struct radeon_device,
561 pm.dpm.thermal.work);
562 /* switch to the thermal state */
563 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
564
565 if (!rdev->pm.dpm_enabled)
566 return;
567
568 if (rdev->asic->pm.get_temperature) {
569 int temp = radeon_get_temperature(rdev);
570
571 if (temp < rdev->pm.dpm.thermal.min_temp)
572 /* switch back the user state */
573 dpm_state = rdev->pm.dpm.user_state;
574 } else {
575 if (rdev->pm.dpm.thermal.high_to_low)
576 /* switch back the user state */
577 dpm_state = rdev->pm.dpm.user_state;
578 }
579 radeon_dpm_enable_power_state(rdev, dpm_state);
580}
581
582static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
583 enum radeon_pm_state_type dpm_state)
584{
585 int i;
586 struct radeon_ps *ps;
587 u32 ui_class;
588
589restart_search:
590 /* balanced states don't exist at the moment */
591 if (dpm_state == POWER_STATE_TYPE_BALANCED)
592 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
593
594 /* Pick the best power state based on current conditions */
595 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
596 ps = &rdev->pm.dpm.ps[i];
597 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
598 switch (dpm_state) {
599 /* user states */
600 case POWER_STATE_TYPE_BATTERY:
601 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
602 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
603 if (rdev->pm.dpm.new_active_crtc_count < 2)
604 return ps;
605 } else
606 return ps;
607 }
608 break;
609 case POWER_STATE_TYPE_BALANCED:
610 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
611 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
612 if (rdev->pm.dpm.new_active_crtc_count < 2)
613 return ps;
614 } else
615 return ps;
616 }
617 break;
618 case POWER_STATE_TYPE_PERFORMANCE:
619 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
620 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
621 if (rdev->pm.dpm.new_active_crtc_count < 2)
622 return ps;
623 } else
624 return ps;
625 }
626 break;
627 /* internal states */
628 case POWER_STATE_TYPE_INTERNAL_UVD:
629 return rdev->pm.dpm.uvd_ps;
630 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
631 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
632 return ps;
633 break;
634 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
635 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
636 return ps;
637 break;
638 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
639 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
640 return ps;
641 break;
642 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
643 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
644 return ps;
645 break;
646 case POWER_STATE_TYPE_INTERNAL_BOOT:
647 return rdev->pm.dpm.boot_ps;
648 case POWER_STATE_TYPE_INTERNAL_THERMAL:
649 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
650 return ps;
651 break;
652 case POWER_STATE_TYPE_INTERNAL_ACPI:
653 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
654 return ps;
655 break;
656 case POWER_STATE_TYPE_INTERNAL_ULV:
657 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
658 return ps;
659 break;
660 default:
661 break;
662 }
663 }
664 /* use a fallback state if we didn't match */
665 switch (dpm_state) {
666 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
667 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
668 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
669 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
670 return rdev->pm.dpm.uvd_ps;
671 case POWER_STATE_TYPE_INTERNAL_THERMAL:
672 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
673 goto restart_search;
674 case POWER_STATE_TYPE_INTERNAL_ACPI:
675 dpm_state = POWER_STATE_TYPE_BATTERY;
676 goto restart_search;
677 case POWER_STATE_TYPE_BATTERY:
678 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
679 goto restart_search;
680 default:
681 break;
682 }
683
684 return NULL;
685}
686
7cf36de9
AD		 687static void radeon_dpm_update_requested_ps(struct radeon_device *rdev,
688 struct radeon_ps *ps)
689{
690 /* copy the ps to the hw ps and point the requested ps
691 * at the hw state in case the driver wants to modify
692 * the state dynamically.
693 */
694 rdev->pm.dpm.hw_ps = *ps;
695 rdev->pm.dpm.requested_ps = &rdev->pm.dpm.hw_ps;
696}
697
da321c8a
AD		 698static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
699{
700 int i;
701 struct radeon_ps *ps;
702 enum radeon_pm_state_type dpm_state;
703
704 /* if dpm init failed */
705 if (!rdev->pm.dpm_enabled)
706 return;
707
708 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
709 /* add other state override checks here */
8a227555
AD		 710 if ((!rdev->pm.dpm.thermal_active) &&
711 (!rdev->pm.dpm.uvd_active))
da321c8a
AD		 712 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
713 }
714 dpm_state = rdev->pm.dpm.state;
715
716 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
717 if (ps)
7cf36de9 718 radeon_dpm_update_requested_ps(rdev, ps);
da321c8a
AD		 719 else
720 return;
721
d22b7e40 722 /* no need to reprogram if nothing changed unless we are on BTC+ */
da321c8a 723 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
d22b7e40
AD		 724 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
725 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
726 * all we need to do is update the display configuration.
727 */
728 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
729 /* update display watermarks based on new power state */
730 radeon_bandwidth_update(rdev);
731 /* update displays */
732 radeon_dpm_display_configuration_changed(rdev);
733 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
734 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
735 }
736 return;
737 } else {
738 /* for BTC+ if the num crtcs hasn't changed and state is the same,
739 * nothing to do, if the num crtcs is > 1 and state is the same,
740 * update display configuration.
741 */
742 if (rdev->pm.dpm.new_active_crtcs ==
743 rdev->pm.dpm.current_active_crtcs) {
744 return;
745 } else {
746 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
747 (rdev->pm.dpm.new_active_crtc_count > 1)) {
748 /* update display watermarks based on new power state */
749 radeon_bandwidth_update(rdev);
750 /* update displays */
751 radeon_dpm_display_configuration_changed(rdev);
752 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
753 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
754 return;
755 }
756 }
da321c8a 757 }
da321c8a
AD		 758 }
759
760 printk("switching from power state:\n");
761 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
762 printk("switching to power state:\n");
763 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
764
765 mutex_lock(&rdev->ddev->struct_mutex);
766 down_write(&rdev->pm.mclk_lock);
767 mutex_lock(&rdev->ring_lock);
768
769 /* update display watermarks based on new power state */
770 radeon_bandwidth_update(rdev);
771 /* update displays */
772 radeon_dpm_display_configuration_changed(rdev);
773
774 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
775 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
776
777 /* wait for the rings to drain */
778 for (i = 0; i < RADEON_NUM_RINGS; i++) {
779 struct radeon_ring *ring = &rdev->ring[i];
780 if (ring->ready)
781 radeon_fence_wait_empty_locked(rdev, i);
782 }
783
784 /* program the new power state */
785 radeon_dpm_set_power_state(rdev);
786
787 /* update current power state */
788 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
789
790 mutex_unlock(&rdev->ring_lock);
791 up_write(&rdev->pm.mclk_lock);
792 mutex_unlock(&rdev->ddev->struct_mutex);
793}
794
795void radeon_dpm_enable_power_state(struct radeon_device *rdev,
796 enum radeon_pm_state_type dpm_state)
797{
798 if (!rdev->pm.dpm_enabled)
799 return;
800
801 mutex_lock(&rdev->pm.mutex);
802 switch (dpm_state) {
803 case POWER_STATE_TYPE_INTERNAL_THERMAL:
804 rdev->pm.dpm.thermal_active = true;
805 break;
8a227555
AD		 806 case POWER_STATE_TYPE_INTERNAL_UVD:
807 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
808 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
809 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
810 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
811 rdev->pm.dpm.uvd_active = true;
812 break;
da321c8a
AD		 813 default:
814 rdev->pm.dpm.thermal_active = false;
8a227555 815 rdev->pm.dpm.uvd_active = false;
da321c8a
AD		 816 break;
817 }
818 rdev->pm.dpm.state = dpm_state;
819 mutex_unlock(&rdev->pm.mutex);
820 radeon_pm_compute_clocks(rdev);
821}
822
823static void radeon_pm_suspend_old(struct radeon_device *rdev)
56278a8e 824{
ce8f5370 825 mutex_lock(&rdev->pm.mutex);
3f53eb6f 826 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 827 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
828 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 829 }
ce8f5370 830 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 831
832 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 833}
834
da321c8a
AD		 835static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
836{
837 mutex_lock(&rdev->pm.mutex);
838 /* disable dpm */
839 radeon_dpm_disable(rdev);
840 /* reset the power state */
841 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
842 rdev->pm.dpm_enabled = false;
843 mutex_unlock(&rdev->pm.mutex);
844}
845
846void radeon_pm_suspend(struct radeon_device *rdev)
847{
848 if (rdev->pm.pm_method == PM_METHOD_DPM)
849 radeon_pm_suspend_dpm(rdev);
850 else
851 radeon_pm_suspend_old(rdev);
852}
853
854static void radeon_pm_resume_old(struct radeon_device *rdev)
d0d6cb81 855{
ed18a360 856 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10
AD		 857 if ((rdev->family >= CHIP_BARTS) &&
858 (rdev->family <= CHIP_CAYMAN) &&
859 rdev->mc_fw) {
ed18a360 860 if (rdev->pm.default_vddc)
8a83ec5e
AD		 861 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
862 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 863 if (rdev->pm.default_vddci)
864 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
865 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 866 if (rdev->pm.default_sclk)
867 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
868 if (rdev->pm.default_mclk)
869 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
870 }
f8ed8b4c
AD		 871 /* asic init will reset the default power state */
872 mutex_lock(&rdev->pm.mutex);
873 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
874 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 875 rdev->pm.current_sclk = rdev->pm.default_sclk;
876 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 877 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 878 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 879 if (rdev->pm.pm_method == PM_METHOD_DYNPM
880 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
881 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 882 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
883 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 884 }
f8ed8b4c 885 mutex_unlock(&rdev->pm.mutex);
ce8f5370 886 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 887}
888
da321c8a
AD		 889static void radeon_pm_resume_dpm(struct radeon_device *rdev)
890{
891 int ret;
892
893 /* asic init will reset to the boot state */
894 mutex_lock(&rdev->pm.mutex);
895 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
896 radeon_dpm_setup_asic(rdev);
897 ret = radeon_dpm_enable(rdev);
898 mutex_unlock(&rdev->pm.mutex);
899 if (ret) {
900 DRM_ERROR("radeon: dpm resume failed\n");
901 if ((rdev->family >= CHIP_BARTS) &&
902 (rdev->family <= CHIP_CAYMAN) &&
903 rdev->mc_fw) {
904 if (rdev->pm.default_vddc)
905 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
906 SET_VOLTAGE_TYPE_ASIC_VDDC);
907 if (rdev->pm.default_vddci)
908 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
909 SET_VOLTAGE_TYPE_ASIC_VDDCI);
910 if (rdev->pm.default_sclk)
911 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
912 if (rdev->pm.default_mclk)
913 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
914 }
915 } else {
916 rdev->pm.dpm_enabled = true;
917 radeon_pm_compute_clocks(rdev);
918 }
919}
920
921void radeon_pm_resume(struct radeon_device *rdev)
922{
923 if (rdev->pm.pm_method == PM_METHOD_DPM)
924 radeon_pm_resume_dpm(rdev);
925 else
926 radeon_pm_resume_old(rdev);
927}
928
929static int radeon_pm_init_old(struct radeon_device *rdev)
7433874e 930{
26481fb1 931 int ret;
0d18abed 932
f8ed8b4c 933 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 934 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
935 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
936 rdev->pm.dynpm_can_upclock = true;
937 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 938 rdev->pm.default_sclk = rdev->clock.default_sclk;
939 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 940 rdev->pm.current_sclk = rdev->clock.default_sclk;
941 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 942 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 943
56278a8e
AD		 944 if (rdev->bios) {
945 if (rdev->is_atom_bios)
946 radeon_atombios_get_power_modes(rdev);
947 else
948 radeon_combios_get_power_modes(rdev);
f712d0c7 949 radeon_pm_print_states(rdev);
ce8f5370 950 radeon_pm_init_profile(rdev);
ed18a360 951 /* set up the default clocks if the MC ucode is loaded */
2e3b3b10
AD		 952 if ((rdev->family >= CHIP_BARTS) &&
953 (rdev->family <= CHIP_CAYMAN) &&
954 rdev->mc_fw) {
ed18a360 955 if (rdev->pm.default_vddc)
8a83ec5e
AD		 956 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
957 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 958 if (rdev->pm.default_vddci)
959 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
960 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 961 if (rdev->pm.default_sclk)
962 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
963 if (rdev->pm.default_mclk)
964 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
965 }
56278a8e
AD		 966 }
967
21a8122a 968 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 969 ret = radeon_hwmon_init(rdev);
970 if (ret)
971 return ret;
32c87fca
TH		 972
973 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
974
ce8f5370 975 if (rdev->pm.num_power_states > 1) {
ce8f5370 976 /* where's the best place to put these? */
26481fb1
DA		 977 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
978 if (ret)
979 DRM_ERROR("failed to create device file for power profile\n");
980 ret = device_create_file(rdev->dev, &dev_attr_power_method);
981 if (ret)
982 DRM_ERROR("failed to create device file for power method\n");
a424816f 983
ce8f5370
AD		 984 if (radeon_debugfs_pm_init(rdev)) {
985 DRM_ERROR("Failed to register debugfs file for PM!\n");
986 }
c913e23a 987
ce8f5370
AD		 988 DRM_INFO("radeon: power management initialized\n");
989 }
c913e23a 990
7433874e
RM		 991 return 0;
992}
993
da321c8a
AD		 994static void radeon_dpm_print_power_states(struct radeon_device *rdev)
995{
996 int i;
997
998 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
999 printk("== power state %d ==\n", i);
1000 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1001 }
1002}
1003
1004static int radeon_pm_init_dpm(struct radeon_device *rdev)
1005{
1006 int ret;
1007
1008 /* default to performance state */
1009 rdev->pm.dpm.state = POWER_STATE_TYPE_PERFORMANCE;
1010 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
1011 rdev->pm.default_sclk = rdev->clock.default_sclk;
1012 rdev->pm.default_mclk = rdev->clock.default_mclk;
1013 rdev->pm.current_sclk = rdev->clock.default_sclk;
1014 rdev->pm.current_mclk = rdev->clock.default_mclk;
1015 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1016
1017 if (rdev->bios && rdev->is_atom_bios)
1018 radeon_atombios_get_power_modes(rdev);
1019 else
1020 return -EINVAL;
1021
1022 /* set up the internal thermal sensor if applicable */
1023 ret = radeon_hwmon_init(rdev);
1024 if (ret)
1025 return ret;
1026
1027 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1028 mutex_lock(&rdev->pm.mutex);
1029 radeon_dpm_init(rdev);
1030 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1031 radeon_dpm_print_power_states(rdev);
1032 radeon_dpm_setup_asic(rdev);
1033 ret = radeon_dpm_enable(rdev);
1034 mutex_unlock(&rdev->pm.mutex);
1035 if (ret) {
1036 rdev->pm.dpm_enabled = false;
1037 if ((rdev->family >= CHIP_BARTS) &&
1038 (rdev->family <= CHIP_CAYMAN) &&
1039 rdev->mc_fw) {
1040 if (rdev->pm.default_vddc)
1041 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1042 SET_VOLTAGE_TYPE_ASIC_VDDC);
1043 if (rdev->pm.default_vddci)
1044 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1045 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1046 if (rdev->pm.default_sclk)
1047 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1048 if (rdev->pm.default_mclk)
1049 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1050 }
1051 DRM_ERROR("radeon: dpm initialization failed\n");
1052 return ret;
1053 }
1054 rdev->pm.dpm_enabled = true;
1055 radeon_pm_compute_clocks(rdev);
1056
1057 if (rdev->pm.num_power_states > 1) {
1058 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1059 if (ret)
1060 DRM_ERROR("failed to create device file for dpm state\n");
1061 /* XXX: these are noops for dpm but are here for backwards compat */
1062 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1063 if (ret)
1064 DRM_ERROR("failed to create device file for power profile\n");
1065 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1066 if (ret)
1067 DRM_ERROR("failed to create device file for power method\n");
1068 DRM_INFO("radeon: dpm initialized\n");
1069 }
1070
1071 return 0;
1072}
1073
1074int radeon_pm_init(struct radeon_device *rdev)
1075{
1076 /* enable dpm on rv6xx+ */
1077 switch (rdev->family) {
4a6369e9
AD		 1078 case CHIP_RV610:
1079 case CHIP_RV630:
1080 case CHIP_RV620:
1081 case CHIP_RV635:
1082 case CHIP_RV670:
9d67006e
AD		 1083 case CHIP_RS780:
1084 case CHIP_RS880:
66229b20
AD		 1085 case CHIP_RV770:
1086 case CHIP_RV730:
1087 case CHIP_RV710:
1088 case CHIP_RV740:
dc50ba7f
AD		 1089 case CHIP_CEDAR:
1090 case CHIP_REDWOOD:
1091 case CHIP_JUNIPER:
1092 case CHIP_CYPRESS:
1093 case CHIP_HEMLOCK:
80ea2c12
AD		 1094 case CHIP_PALM:
1095 case CHIP_SUMO:
1096 case CHIP_SUMO2:
6596afd4
AD		 1097 case CHIP_BARTS:
1098 case CHIP_TURKS:
1099 case CHIP_CAICOS:
d70229f7 1100 case CHIP_ARUBA:
9d67006e
AD		 1101 if (radeon_dpm == 1)
1102 rdev->pm.pm_method = PM_METHOD_DPM;
1103 else
1104 rdev->pm.pm_method = PM_METHOD_PROFILE;
1105 break;
da321c8a
AD		 1106 default:
1107 /* default to profile method */
1108 rdev->pm.pm_method = PM_METHOD_PROFILE;
1109 break;
1110 }
1111
1112 if (rdev->pm.pm_method == PM_METHOD_DPM)
1113 return radeon_pm_init_dpm(rdev);
1114 else
1115 return radeon_pm_init_old(rdev);
1116}
1117
1118static void radeon_pm_fini_old(struct radeon_device *rdev)
29fb52ca 1119{
ce8f5370 1120 if (rdev->pm.num_power_states > 1) {
a424816f 1121 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 1122 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1123 rdev->pm.profile = PM_PROFILE_DEFAULT;
1124 radeon_pm_update_profile(rdev);
1125 radeon_pm_set_clocks(rdev);
1126 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 1127 /* reset default clocks */
1128 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1129 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1130 radeon_pm_set_clocks(rdev);
1131 }
a424816f 1132 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 1133
1134 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 1135
ce8f5370
AD		 1136 device_remove_file(rdev->dev, &dev_attr_power_profile);
1137 device_remove_file(rdev->dev, &dev_attr_power_method);
ce8f5370 1138 }
a424816f 1139
0975b162
AD		 1140 if (rdev->pm.power_state)
1141 kfree(rdev->pm.power_state);
1142
21a8122a 1143 radeon_hwmon_fini(rdev);
29fb52ca
AD		 1144}
1145
da321c8a
AD		 1146static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1147{
1148 if (rdev->pm.num_power_states > 1) {
1149 mutex_lock(&rdev->pm.mutex);
1150 radeon_dpm_disable(rdev);
1151 mutex_unlock(&rdev->pm.mutex);
1152
1153 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1154 /* XXX backwards compat */
1155 device_remove_file(rdev->dev, &dev_attr_power_profile);
1156 device_remove_file(rdev->dev, &dev_attr_power_method);
1157 }
1158 radeon_dpm_fini(rdev);
1159
1160 if (rdev->pm.power_state)
1161 kfree(rdev->pm.power_state);
1162
1163 radeon_hwmon_fini(rdev);
1164}
1165
1166void radeon_pm_fini(struct radeon_device *rdev)
1167{
1168 if (rdev->pm.pm_method == PM_METHOD_DPM)
1169 radeon_pm_fini_dpm(rdev);
1170 else
1171 radeon_pm_fini_old(rdev);
1172}
1173
1174static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
c913e23a
RM		 1175{
1176 struct drm_device *ddev = rdev->ddev;
a48b9b4e 1177 struct drm_crtc *crtc;
c913e23a 1178 struct radeon_crtc *radeon_crtc;
c913e23a 1179
ce8f5370
AD		 1180 if (rdev->pm.num_power_states < 2)
1181 return;
1182
4a6369e9 1183 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
c913e23a
RM		 1184 mutex_lock(&rdev->pm.mutex);
1185
1186 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 1187 rdev->pm.active_crtc_count = 0;
1188 list_for_each_entry(crtc,
1189 &ddev->mode_config.crtc_list, head) {
1190 radeon_crtc = to_radeon_crtc(crtc);
1191 if (radeon_crtc->enabled) {
c913e23a 1192 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 1193 rdev->pm.active_crtc_count++;
c913e23a
RM		 1194 }
1195 }
1196
ce8f5370
AD		 1197 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1198 radeon_pm_update_profile(rdev);
1199 radeon_pm_set_clocks(rdev);
1200 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1201 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1202 if (rdev->pm.active_crtc_count > 1) {
1203 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1204 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1205
1206 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1207 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1208 radeon_pm_get_dynpm_state(rdev);
1209 radeon_pm_set_clocks(rdev);
1210
d9fdaafb 1211 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 1212 }
1213 } else if (rdev->pm.active_crtc_count == 1) {
1214 /* TODO: Increase clocks if needed for current mode */
1215
1216 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1217 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1218 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1219 radeon_pm_get_dynpm_state(rdev);
1220 radeon_pm_set_clocks(rdev);
1221
32c87fca
TH		 1222 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1223 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 1224 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1225 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 1226 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1227 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 1228 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 1229 }
1230 } else { /* count == 0 */
1231 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1232 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1233
1234 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1235 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1236 radeon_pm_get_dynpm_state(rdev);
1237 radeon_pm_set_clocks(rdev);
1238 }
1239 }
c913e23a 1240 }
c913e23a 1241 }
73a6d3fc
RM		 1242
1243 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 1244}
1245
da321c8a
AD		 1246static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1247{
1248 struct drm_device *ddev = rdev->ddev;
1249 struct drm_crtc *crtc;
1250 struct radeon_crtc *radeon_crtc;
1251
1252 mutex_lock(&rdev->pm.mutex);
1253
5ca302f7 1254 /* update active crtc counts */
da321c8a
AD		 1255 rdev->pm.dpm.new_active_crtcs = 0;
1256 rdev->pm.dpm.new_active_crtc_count = 0;
1257 list_for_each_entry(crtc,
1258 &ddev->mode_config.crtc_list, head) {
1259 radeon_crtc = to_radeon_crtc(crtc);
1260 if (crtc->enabled) {
1261 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1262 rdev->pm.dpm.new_active_crtc_count++;
1263 }
1264 }
1265
5ca302f7
AD		 1266 /* update battery/ac status */
1267 if (power_supply_is_system_supplied() > 0)
1268 rdev->pm.dpm.ac_power = true;
1269 else
1270 rdev->pm.dpm.ac_power = false;
1271
da321c8a
AD		 1272 radeon_dpm_change_power_state_locked(rdev);
1273
1274 mutex_unlock(&rdev->pm.mutex);
8a227555 1275
da321c8a
AD		 1276}
1277
1278void radeon_pm_compute_clocks(struct radeon_device *rdev)
1279{
1280 if (rdev->pm.pm_method == PM_METHOD_DPM)
1281 radeon_pm_compute_clocks_dpm(rdev);
1282 else
1283 radeon_pm_compute_clocks_old(rdev);
1284}
1285
ce8f5370 1286static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 1287{
75fa0b08 1288 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 1289 bool in_vbl = true;
1290
75fa0b08
MK		 1291 /* Iterate over all active crtc's. All crtc's must be in vblank,
1292 * otherwise return in_vbl == false.
1293 */
1294 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1295 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 1296 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1297 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1298 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 1299 in_vbl = false;
1300 }
1301 }
f81f2024
MG		 1302
1303 return in_vbl;
1304}
1305
ce8f5370 1306static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 1307{
1308 u32 stat_crtc = 0;
1309 bool in_vbl = radeon_pm_in_vbl(rdev);
1310
f735261b 1311 if (in_vbl == false)
d9fdaafb 1312 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 1313 finish ? "exit" : "entry");
f735261b
DA		 1314 return in_vbl;
1315}
c913e23a 1316
ce8f5370 1317static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 1318{
1319 struct radeon_device *rdev;
d9932a32 1320 int resched;
c913e23a 1321 rdev = container_of(work, struct radeon_device,
ce8f5370 1322 pm.dynpm_idle_work.work);
c913e23a 1323
d9932a32 1324 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 1325 mutex_lock(&rdev->pm.mutex);
ce8f5370 1326 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 1327 int not_processed = 0;
7465280c
AD		 1328 int i;
1329
7465280c 1330 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 1331 struct radeon_ring *ring = &rdev->ring[i];
1332
1333 if (ring->ready) {
1334 not_processed += radeon_fence_count_emitted(rdev, i);
1335 if (not_processed >= 3)
1336 break;
1337 }
c913e23a 1338 }
c913e23a
RM		 1339
1340 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 1341 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1342 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1343 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1344 rdev->pm.dynpm_can_upclock) {
1345 rdev->pm.dynpm_planned_action =
1346 DYNPM_ACTION_UPCLOCK;
1347 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1348 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1349 }
1350 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 1351 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1352 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1353 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1354 rdev->pm.dynpm_can_downclock) {
1355 rdev->pm.dynpm_planned_action =
1356 DYNPM_ACTION_DOWNCLOCK;
1357 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 1358 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1359 }
1360 }
1361
d7311171
AD		 1362 /* Note, radeon_pm_set_clocks is called with static_switch set
1363 * to false since we want to wait for vbl to avoid flicker.
1364 */
ce8f5370
AD		 1365 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1366 jiffies > rdev->pm.dynpm_action_timeout) {
1367 radeon_pm_get_dynpm_state(rdev);
1368 radeon_pm_set_clocks(rdev);
c913e23a 1369 }
3f53eb6f 1370
32c87fca
TH		 1371 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1372 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 1373 }
1374 mutex_unlock(&rdev->pm.mutex);
d9932a32 1375 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 1376}
1377
7433874e
RM		 1378/*
1379 * Debugfs info
1380 */
1381#if defined(CONFIG_DEBUG_FS)
1382
1383static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1384{
1385 struct drm_info_node *node = (struct drm_info_node *) m->private;
1386 struct drm_device *dev = node->minor->dev;
1387 struct radeon_device *rdev = dev->dev_private;
1388
9ace9f7b 1389 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
bf05d998
AD		 1390 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1391 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1392 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1393 else
1394 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 1395 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 1396 if (rdev->asic->pm.get_memory_clock)
6234077d 1397 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 1398 if (rdev->pm.current_vddc)
1399 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 1400 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 1401 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 1402
1403 return 0;
1404}
1405
1406static struct drm_info_list radeon_pm_info_list[] = {
1407 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1408};
1409#endif
1410
c913e23a 1411static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 1412{
1413#if defined(CONFIG_DEBUG_FS)
1414 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1415#else
1416 return 0;
1417#endif
1418}
Linux kernel - Deliverables
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