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drm/radeon: implement handler for ACPI event
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
fda4b25c 25#include "radeon_acpi.h"
f735261b 26#include "avivod.h"
8a83ec5e 27#include "atom.h"
ce8f5370
AD		 28#ifdef CONFIG_ACPI
29#include <linux/acpi.h>
30#endif
31#include <linux/power_supply.h>
21a8122a
AD		 32#include <linux/hwmon.h>
33#include <linux/hwmon-sysfs.h>
7433874e 34
c913e23a
RM		 35#define RADEON_IDLE_LOOP_MS 100
36#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 37#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 38
f712d0c7
RM		 39static const char *radeon_pm_state_type_name[5] = {
40 "Default",
41 "Powersave",
42 "Battery",
43 "Balanced",
44 "Performance",
45};
46
ce8f5370 47static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 48static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 49static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51static void radeon_pm_update_profile(struct radeon_device *rdev);
52static void radeon_pm_set_clocks(struct radeon_device *rdev);
53
54#define ACPI_AC_CLASS "ac_adapter"
55
a4c9e2ee
AD		 56int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
58 int instance)
59{
60 int i;
61 int found_instance = -1;
62
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
65 found_instance++;
66 if (found_instance == instance)
67 return i;
68 }
69 }
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
72}
73
ce8f5370
AD		 74#ifdef CONFIG_ACPI
75static int radeon_acpi_event(struct notifier_block *nb,
76 unsigned long val,
77 void *data)
78{
79 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
80 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
81
82 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
83 if (power_supply_is_system_supplied() > 0)
d9fdaafb 84 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 85 else
d9fdaafb 86 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 87
88 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96 }
97
fda4b25c
LT		 98 /* Check for pending SBIOS requests */
99 return radeon_atif_handler(rdev, entry);
ce8f5370
AD		 100}
101#endif
102
103static void radeon_pm_update_profile(struct radeon_device *rdev)
104{
105 switch (rdev->pm.profile) {
106 case PM_PROFILE_DEFAULT:
107 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
108 break;
109 case PM_PROFILE_AUTO:
110 if (power_supply_is_system_supplied() > 0) {
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
113 else
114 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
115 } else {
116 if (rdev->pm.active_crtc_count > 1)
c9e75b21 117 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 118 else
c9e75b21 119 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 120 }
121 break;
122 case PM_PROFILE_LOW:
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
125 else
126 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
127 break;
c9e75b21
AD		 128 case PM_PROFILE_MID:
129 if (rdev->pm.active_crtc_count > 1)
130 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
131 else
132 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
133 break;
ce8f5370
AD		 134 case PM_PROFILE_HIGH:
135 if (rdev->pm.active_crtc_count > 1)
136 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
137 else
138 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
139 break;
140 }
141
142 if (rdev->pm.active_crtc_count == 0) {
143 rdev->pm.requested_power_state_index =
144 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
145 rdev->pm.requested_clock_mode_index =
146 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
147 } else {
148 rdev->pm.requested_power_state_index =
149 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
150 rdev->pm.requested_clock_mode_index =
151 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
152 }
153}
c913e23a 154
5876dd24
MG		 155static void radeon_unmap_vram_bos(struct radeon_device *rdev)
156{
157 struct radeon_bo *bo, *n;
158
159 if (list_empty(&rdev->gem.objects))
160 return;
161
162 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
163 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
164 ttm_bo_unmap_virtual(&bo->tbo);
165 }
5876dd24
MG		 166}
167
ce8f5370 168static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 169{
ce8f5370
AD		 170 if (rdev->pm.active_crtcs) {
171 rdev->pm.vblank_sync = false;
172 wait_event_timeout(
173 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
174 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
175 }
176}
177
178static void radeon_set_power_state(struct radeon_device *rdev)
179{
180 u32 sclk, mclk;
92645879 181 bool misc_after = false;
ce8f5370
AD		 182
183 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
184 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
185 return;
186
187 if (radeon_gui_idle(rdev)) {
188 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 190 if (sclk > rdev->pm.default_sclk)
191 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 192
193 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
194 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 195 if (mclk > rdev->pm.default_mclk)
196 mclk = rdev->pm.default_mclk;
ce8f5370 197
92645879
AD		 198 /* upvolt before raising clocks, downvolt after lowering clocks */
199 if (sclk < rdev->pm.current_sclk)
200 misc_after = true;
ce8f5370 201
92645879 202 radeon_sync_with_vblank(rdev);
ce8f5370 203
92645879 204 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 205 if (!radeon_pm_in_vbl(rdev))
206 return;
92645879 207 }
ce8f5370 208
92645879 209 radeon_pm_prepare(rdev);
ce8f5370 210
92645879
AD		 211 if (!misc_after)
212 /* voltage, pcie lanes, etc.*/
213 radeon_pm_misc(rdev);
214
215 /* set engine clock */
216 if (sclk != rdev->pm.current_sclk) {
217 radeon_pm_debug_check_in_vbl(rdev, false);
218 radeon_set_engine_clock(rdev, sclk);
219 radeon_pm_debug_check_in_vbl(rdev, true);
220 rdev->pm.current_sclk = sclk;
d9fdaafb 221 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 222 }
223
224 /* set memory clock */
798bcf73 225 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 226 radeon_pm_debug_check_in_vbl(rdev, false);
227 radeon_set_memory_clock(rdev, mclk);
228 radeon_pm_debug_check_in_vbl(rdev, true);
229 rdev->pm.current_mclk = mclk;
d9fdaafb 230 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 231 }
2aba631c 232
92645879
AD		 233 if (misc_after)
234 /* voltage, pcie lanes, etc.*/
235 radeon_pm_misc(rdev);
236
237 radeon_pm_finish(rdev);
238
ce8f5370
AD		 239 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
240 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
241 } else
d9fdaafb 242 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 243}
244
245static void radeon_pm_set_clocks(struct radeon_device *rdev)
246{
247 int i;
c37d230a 248
4e186b2d
AD		 249 /* no need to take locks, etc. if nothing's going to change */
250 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
251 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
252 return;
253
612e06ce 254 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 255 down_write(&rdev->pm.mclk_lock);
d6999bc7 256 mutex_lock(&rdev->ring_lock);
4f3218cb 257
95f5a3ac
AD		 258 /* wait for the rings to drain */
259 for (i = 0; i < RADEON_NUM_RINGS; i++) {
260 struct radeon_ring *ring = &rdev->ring[i];
261 if (ring->ready)
262 radeon_fence_wait_empty_locked(rdev, i);
4f3218cb 263 }
95f5a3ac 264
5876dd24
MG		 265 radeon_unmap_vram_bos(rdev);
266
ce8f5370 267 if (rdev->irq.installed) {
2aba631c
MG		 268 for (i = 0; i < rdev->num_crtc; i++) {
269 if (rdev->pm.active_crtcs & (1 << i)) {
270 rdev->pm.req_vblank |= (1 << i);
271 drm_vblank_get(rdev->ddev, i);
272 }
273 }
274 }
539d2418 275
ce8f5370 276 radeon_set_power_state(rdev);
2aba631c 277
ce8f5370 278 if (rdev->irq.installed) {
2aba631c
MG		 279 for (i = 0; i < rdev->num_crtc; i++) {
280 if (rdev->pm.req_vblank & (1 << i)) {
281 rdev->pm.req_vblank &= ~(1 << i);
282 drm_vblank_put(rdev->ddev, i);
283 }
284 }
285 }
5876dd24 286
a424816f
AD		 287 /* update display watermarks based on new power state */
288 radeon_update_bandwidth_info(rdev);
289 if (rdev->pm.active_crtc_count)
290 radeon_bandwidth_update(rdev);
291
ce8f5370 292 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 293
d6999bc7 294 mutex_unlock(&rdev->ring_lock);
db7fce39 295 up_write(&rdev->pm.mclk_lock);
612e06ce 296 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 297}
298
f712d0c7
RM		 299static void radeon_pm_print_states(struct radeon_device *rdev)
300{
301 int i, j;
302 struct radeon_power_state *power_state;
303 struct radeon_pm_clock_info *clock_info;
304
d9fdaafb 305 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 306 for (i = 0; i < rdev->pm.num_power_states; i++) {
307 power_state = &rdev->pm.power_state[i];
d9fdaafb 308 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 309 radeon_pm_state_type_name[power_state->type]);
310 if (i == rdev->pm.default_power_state_index)
d9fdaafb 311 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 312 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 313 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 314 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 315 DRM_DEBUG_DRIVER("\tSingle display only\n");
316 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 317 for (j = 0; j < power_state->num_clock_modes; j++) {
318 clock_info = &(power_state->clock_info[j]);
319 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 320 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 321 j,
322 clock_info->sclk * 10,
323 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
324 else
d9fdaafb 325 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 326 j,
327 clock_info->sclk * 10,
328 clock_info->mclk * 10,
329 clock_info->voltage.voltage,
330 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
331 }
332 }
333}
334
ce8f5370
AD		 335static ssize_t radeon_get_pm_profile(struct device *dev,
336 struct device_attribute *attr,
337 char *buf)
a424816f
AD		 338{
339 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
340 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 341 int cp = rdev->pm.profile;
a424816f 342
ce8f5370
AD		 343 return snprintf(buf, PAGE_SIZE, "%s\n",
344 (cp == PM_PROFILE_AUTO) ? "auto" :
345 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 346 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 347 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 348}
349
ce8f5370
AD		 350static ssize_t radeon_set_pm_profile(struct device *dev,
351 struct device_attribute *attr,
352 const char *buf,
353 size_t count)
a424816f
AD		 354{
355 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
356 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 357
358 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 359 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
360 if (strncmp("default", buf, strlen("default")) == 0)
361 rdev->pm.profile = PM_PROFILE_DEFAULT;
362 else if (strncmp("auto", buf, strlen("auto")) == 0)
363 rdev->pm.profile = PM_PROFILE_AUTO;
364 else if (strncmp("low", buf, strlen("low")) == 0)
365 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 366 else if (strncmp("mid", buf, strlen("mid")) == 0)
367 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 368 else if (strncmp("high", buf, strlen("high")) == 0)
369 rdev->pm.profile = PM_PROFILE_HIGH;
370 else {
1783e4bf 371 count = -EINVAL;
ce8f5370 372 goto fail;
a424816f 373 }
ce8f5370
AD		 374 radeon_pm_update_profile(rdev);
375 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 376 } else
377 count = -EINVAL;
378
ce8f5370 379fail:
a424816f
AD		 380 mutex_unlock(&rdev->pm.mutex);
381
382 return count;
383}
384
ce8f5370
AD		 385static ssize_t radeon_get_pm_method(struct device *dev,
386 struct device_attribute *attr,
387 char *buf)
a424816f
AD		 388{
389 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
390 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 391 int pm = rdev->pm.pm_method;
a424816f
AD		 392
393 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 394 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 395}
396
ce8f5370
AD		 397static ssize_t radeon_set_pm_method(struct device *dev,
398 struct device_attribute *attr,
399 const char *buf,
400 size_t count)
a424816f
AD		 401{
402 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
403 struct radeon_device *rdev = ddev->dev_private;
a424816f 404
ce8f5370
AD		 405
406 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 407 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 408 rdev->pm.pm_method = PM_METHOD_DYNPM;
409 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
410 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 411 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 412 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
413 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 414 /* disable dynpm */
415 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
416 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 417 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 418 mutex_unlock(&rdev->pm.mutex);
32c87fca 419 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 420 } else {
1783e4bf 421 count = -EINVAL;
ce8f5370
AD		 422 goto fail;
423 }
424 radeon_pm_compute_clocks(rdev);
425fail:
a424816f
AD		 426 return count;
427}
428
ce8f5370
AD		 429static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
430static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 431
21a8122a
AD		 432static ssize_t radeon_hwmon_show_temp(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435{
436 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
437 struct radeon_device *rdev = ddev->dev_private;
20d391d7 438 int temp;
21a8122a
AD		 439
440 switch (rdev->pm.int_thermal_type) {
441 case THERMAL_TYPE_RV6XX:
442 temp = rv6xx_get_temp(rdev);
443 break;
444 case THERMAL_TYPE_RV770:
445 temp = rv770_get_temp(rdev);
446 break;
447 case THERMAL_TYPE_EVERGREEN:
4fddba1f 448 case THERMAL_TYPE_NI:
21a8122a
AD		 449 temp = evergreen_get_temp(rdev);
450 break;
e33df25f
AD		 451 case THERMAL_TYPE_SUMO:
452 temp = sumo_get_temp(rdev);
453 break;
1bd47d2e
AD		 454 case THERMAL_TYPE_SI:
455 temp = si_get_temp(rdev);
456 break;
21a8122a
AD		 457 default:
458 temp = 0;
459 break;
460 }
461
462 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
463}
464
465static ssize_t radeon_hwmon_show_name(struct device *dev,
466 struct device_attribute *attr,
467 char *buf)
468{
469 return sprintf(buf, "radeon\n");
470}
471
472static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
473static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
474
475static struct attribute *hwmon_attributes[] = {
476 &sensor_dev_attr_temp1_input.dev_attr.attr,
477 &sensor_dev_attr_name.dev_attr.attr,
478 NULL
479};
480
481static const struct attribute_group hwmon_attrgroup = {
482 .attrs = hwmon_attributes,
483};
484
0d18abed 485static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 486{
0d18abed 487 int err = 0;
21a8122a
AD		 488
489 rdev->pm.int_hwmon_dev = NULL;
490
491 switch (rdev->pm.int_thermal_type) {
492 case THERMAL_TYPE_RV6XX:
493 case THERMAL_TYPE_RV770:
494 case THERMAL_TYPE_EVERGREEN:
457558ed 495 case THERMAL_TYPE_NI:
e33df25f 496 case THERMAL_TYPE_SUMO:
1bd47d2e 497 case THERMAL_TYPE_SI:
5d7486c7
AD		 498 /* No support for TN yet */
499 if (rdev->family == CHIP_ARUBA)
500 return err;
21a8122a 501 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 502 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
503 err = PTR_ERR(rdev->pm.int_hwmon_dev);
504 dev_err(rdev->dev,
505 "Unable to register hwmon device: %d\n", err);
506 break;
507 }
21a8122a
AD		 508 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
509 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
510 &hwmon_attrgroup);
0d18abed
DC		 511 if (err) {
512 dev_err(rdev->dev,
513 "Unable to create hwmon sysfs file: %d\n", err);
514 hwmon_device_unregister(rdev->dev);
515 }
21a8122a
AD		 516 break;
517 default:
518 break;
519 }
0d18abed
DC		 520
521 return err;
21a8122a
AD		 522}
523
524static void radeon_hwmon_fini(struct radeon_device *rdev)
525{
526 if (rdev->pm.int_hwmon_dev) {
527 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
528 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
529 }
530}
531
ce8f5370 532void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 533{
ce8f5370 534 mutex_lock(&rdev->pm.mutex);
3f53eb6f 535 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 536 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
537 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 538 }
ce8f5370 539 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 540
541 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 542}
543
ce8f5370 544void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 545{
ed18a360
AD		 546 /* set up the default clocks if the MC ucode is loaded */
547 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
548 if (rdev->pm.default_vddc)
8a83ec5e
AD		 549 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
550 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 551 if (rdev->pm.default_vddci)
552 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
553 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 554 if (rdev->pm.default_sclk)
555 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
556 if (rdev->pm.default_mclk)
557 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
558 }
f8ed8b4c
AD		 559 /* asic init will reset the default power state */
560 mutex_lock(&rdev->pm.mutex);
561 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
562 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 563 rdev->pm.current_sclk = rdev->pm.default_sclk;
564 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 565 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 566 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 567 if (rdev->pm.pm_method == PM_METHOD_DYNPM
568 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
569 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 570 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
571 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 572 }
f8ed8b4c 573 mutex_unlock(&rdev->pm.mutex);
ce8f5370 574 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 575}
576
7433874e
RM		 577int radeon_pm_init(struct radeon_device *rdev)
578{
26481fb1 579 int ret;
0d18abed 580
ce8f5370
AD		 581 /* default to profile method */
582 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 583 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 584 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
585 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
586 rdev->pm.dynpm_can_upclock = true;
587 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 588 rdev->pm.default_sclk = rdev->clock.default_sclk;
589 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 590 rdev->pm.current_sclk = rdev->clock.default_sclk;
591 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 592 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 593
56278a8e
AD		 594 if (rdev->bios) {
595 if (rdev->is_atom_bios)
596 radeon_atombios_get_power_modes(rdev);
597 else
598 radeon_combios_get_power_modes(rdev);
f712d0c7 599 radeon_pm_print_states(rdev);
ce8f5370 600 radeon_pm_init_profile(rdev);
ed18a360
AD		 601 /* set up the default clocks if the MC ucode is loaded */
602 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
603 if (rdev->pm.default_vddc)
8a83ec5e
AD		 604 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
605 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 606 if (rdev->pm.default_vddci)
607 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
608 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 609 if (rdev->pm.default_sclk)
610 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
611 if (rdev->pm.default_mclk)
612 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
613 }
56278a8e
AD		 614 }
615
21a8122a 616 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 617 ret = radeon_hwmon_init(rdev);
618 if (ret)
619 return ret;
32c87fca
TH		 620
621 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
622
ce8f5370 623 if (rdev->pm.num_power_states > 1) {
ce8f5370 624 /* where's the best place to put these? */
26481fb1
DA		 625 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
626 if (ret)
627 DRM_ERROR("failed to create device file for power profile\n");
628 ret = device_create_file(rdev->dev, &dev_attr_power_method);
629 if (ret)
630 DRM_ERROR("failed to create device file for power method\n");
a424816f 631
ce8f5370
AD		 632#ifdef CONFIG_ACPI
633 rdev->acpi_nb.notifier_call = radeon_acpi_event;
634 register_acpi_notifier(&rdev->acpi_nb);
635#endif
ce8f5370
AD		 636 if (radeon_debugfs_pm_init(rdev)) {
637 DRM_ERROR("Failed to register debugfs file for PM!\n");
638 }
c913e23a 639
ce8f5370
AD		 640 DRM_INFO("radeon: power management initialized\n");
641 }
c913e23a 642
7433874e
RM		 643 return 0;
644}
645
29fb52ca
AD		 646void radeon_pm_fini(struct radeon_device *rdev)
647{
ce8f5370 648 if (rdev->pm.num_power_states > 1) {
a424816f 649 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 650 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
651 rdev->pm.profile = PM_PROFILE_DEFAULT;
652 radeon_pm_update_profile(rdev);
653 radeon_pm_set_clocks(rdev);
654 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 655 /* reset default clocks */
656 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
657 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
658 radeon_pm_set_clocks(rdev);
659 }
a424816f 660 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 661
662 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 663
ce8f5370
AD		 664 device_remove_file(rdev->dev, &dev_attr_power_profile);
665 device_remove_file(rdev->dev, &dev_attr_power_method);
666#ifdef CONFIG_ACPI
667 unregister_acpi_notifier(&rdev->acpi_nb);
668#endif
669 }
a424816f 670
0975b162
AD		 671 if (rdev->pm.power_state)
672 kfree(rdev->pm.power_state);
673
21a8122a 674 radeon_hwmon_fini(rdev);
29fb52ca
AD		 675}
676
c913e23a
RM		 677void radeon_pm_compute_clocks(struct radeon_device *rdev)
678{
679 struct drm_device *ddev = rdev->ddev;
a48b9b4e 680 struct drm_crtc *crtc;
c913e23a 681 struct radeon_crtc *radeon_crtc;
c913e23a 682
ce8f5370
AD		 683 if (rdev->pm.num_power_states < 2)
684 return;
685
c913e23a
RM		 686 mutex_lock(&rdev->pm.mutex);
687
688 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 689 rdev->pm.active_crtc_count = 0;
690 list_for_each_entry(crtc,
691 &ddev->mode_config.crtc_list, head) {
692 radeon_crtc = to_radeon_crtc(crtc);
693 if (radeon_crtc->enabled) {
c913e23a 694 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 695 rdev->pm.active_crtc_count++;
c913e23a
RM		 696 }
697 }
698
ce8f5370
AD		 699 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
700 radeon_pm_update_profile(rdev);
701 radeon_pm_set_clocks(rdev);
702 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
703 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
704 if (rdev->pm.active_crtc_count > 1) {
705 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
706 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
707
708 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
709 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
710 radeon_pm_get_dynpm_state(rdev);
711 radeon_pm_set_clocks(rdev);
712
d9fdaafb 713 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 714 }
715 } else if (rdev->pm.active_crtc_count == 1) {
716 /* TODO: Increase clocks if needed for current mode */
717
718 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
719 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
720 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
721 radeon_pm_get_dynpm_state(rdev);
722 radeon_pm_set_clocks(rdev);
723
32c87fca
TH		 724 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
725 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 726 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
727 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 728 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
729 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 730 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 731 }
732 } else { /* count == 0 */
733 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
734 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
735
736 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
737 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
738 radeon_pm_get_dynpm_state(rdev);
739 radeon_pm_set_clocks(rdev);
740 }
741 }
c913e23a 742 }
c913e23a 743 }
73a6d3fc
RM		 744
745 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 746}
747
ce8f5370 748static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 749{
75fa0b08 750 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 751 bool in_vbl = true;
752
75fa0b08
MK		 753 /* Iterate over all active crtc's. All crtc's must be in vblank,
754 * otherwise return in_vbl == false.
755 */
756 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
757 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 758 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
759 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
760 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 761 in_vbl = false;
762 }
763 }
f81f2024
MG		 764
765 return in_vbl;
766}
767
ce8f5370 768static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 769{
770 u32 stat_crtc = 0;
771 bool in_vbl = radeon_pm_in_vbl(rdev);
772
f735261b 773 if (in_vbl == false)
d9fdaafb 774 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 775 finish ? "exit" : "entry");
f735261b
DA		 776 return in_vbl;
777}
c913e23a 778
ce8f5370 779static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 780{
781 struct radeon_device *rdev;
d9932a32 782 int resched;
c913e23a 783 rdev = container_of(work, struct radeon_device,
ce8f5370 784 pm.dynpm_idle_work.work);
c913e23a 785
d9932a32 786 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 787 mutex_lock(&rdev->pm.mutex);
ce8f5370 788 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 789 int not_processed = 0;
7465280c
AD		 790 int i;
791
7465280c 792 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 793 struct radeon_ring *ring = &rdev->ring[i];
794
795 if (ring->ready) {
796 not_processed += radeon_fence_count_emitted(rdev, i);
797 if (not_processed >= 3)
798 break;
799 }
c913e23a 800 }
c913e23a
RM		 801
802 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 803 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
804 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
805 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
806 rdev->pm.dynpm_can_upclock) {
807 rdev->pm.dynpm_planned_action =
808 DYNPM_ACTION_UPCLOCK;
809 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 810 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
811 }
812 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 813 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
814 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
815 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
816 rdev->pm.dynpm_can_downclock) {
817 rdev->pm.dynpm_planned_action =
818 DYNPM_ACTION_DOWNCLOCK;
819 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
821 }
822 }
823
d7311171
AD		 824 /* Note, radeon_pm_set_clocks is called with static_switch set
825 * to false since we want to wait for vbl to avoid flicker.
826 */
ce8f5370
AD		 827 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
828 jiffies > rdev->pm.dynpm_action_timeout) {
829 radeon_pm_get_dynpm_state(rdev);
830 radeon_pm_set_clocks(rdev);
c913e23a 831 }
3f53eb6f 832
32c87fca
TH		 833 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
834 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 835 }
836 mutex_unlock(&rdev->pm.mutex);
d9932a32 837 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 838}
839
7433874e
RM		 840/*
841 * Debugfs info
842 */
843#if defined(CONFIG_DEBUG_FS)
844
845static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
846{
847 struct drm_info_node *node = (struct drm_info_node *) m->private;
848 struct drm_device *dev = node->minor->dev;
849 struct radeon_device *rdev = dev->dev_private;
850
9ace9f7b 851 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 852 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 853 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 854 if (rdev->asic->pm.get_memory_clock)
6234077d 855 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 856 if (rdev->pm.current_vddc)
857 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 858 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 859 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 860
861 return 0;
862}
863
864static struct drm_info_list radeon_pm_info_list[] = {
865 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
866};
867#endif
868
c913e23a 869static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 870{
871#if defined(CONFIG_DEBUG_FS)
872 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
873#else
874 return 0;
875#endif
876}
Linux kernel - Deliverables
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