Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
c507f7ef | 27 | * Christian König |
771fe6b9 JG |
28 | */ |
29 | #include <linux/seq_file.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
35 | #include "atom.h" | |
36 | ||
c507f7ef | 37 | /* |
75923280 AD |
38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
40 | * commands are stored. You can put a pointer to the IB in the | |
41 | * command ring and the hw will fetch the commands from the IB | |
42 | * and execute them. Generally userspace acceleration drivers | |
43 | * produce command buffers which are send to the kernel and | |
44 | * put in IBs for execution by the requested ring. | |
c507f7ef | 45 | */ |
1109ca09 | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
771fe6b9 | 47 | |
75923280 AD |
48 | /** |
49 | * radeon_ib_get - request an IB (Indirect Buffer) | |
50 | * | |
51 | * @rdev: radeon_device pointer | |
52 | * @ring: ring index the IB is associated with | |
53 | * @ib: IB object returned | |
54 | * @size: requested IB size | |
55 | * | |
56 | * Request an IB (all asics). IBs are allocated using the | |
57 | * suballocator. | |
58 | * Returns 0 on success, error on failure. | |
59 | */ | |
69e130a6 | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
61 | struct radeon_ib *ib, struct radeon_vm *vm, |
62 | unsigned size) | |
771fe6b9 | 63 | { |
1654b817 | 64 | int r; |
b15ba512 | 65 | |
4d152646 | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256); |
c507f7ef JG |
67 | if (r) { |
68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); | |
c507f7ef | 69 | return r; |
b15ba512 | 70 | } |
c507f7ef | 71 | |
220907d9 CK |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
73 | if (r) { | |
74 | return r; | |
75 | } | |
76 | ||
876dc9f3 CK |
77 | ib->ring = ring; |
78 | ib->fence = NULL; | |
f2e39221 | 79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
4bf3dd92 CK |
80 | ib->vm = vm; |
81 | if (vm) { | |
ca19f21e CK |
82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
83 | * space and soffset is the offset inside the pool bo | |
4bf3dd92 | 84 | */ |
ca19f21e | 85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
4bf3dd92 CK |
86 | } else { |
87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); | |
88 | } | |
f2e39221 | 89 | ib->is_const_ib = false; |
c507f7ef JG |
90 | |
91 | return 0; | |
771fe6b9 JG |
92 | } |
93 | ||
75923280 AD |
94 | /** |
95 | * radeon_ib_free - free an IB (Indirect Buffer) | |
96 | * | |
97 | * @rdev: radeon_device pointer | |
98 | * @ib: IB object to free | |
99 | * | |
100 | * Free an IB (all asics). | |
101 | */ | |
f2e39221 | 102 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
771fe6b9 | 103 | { |
220907d9 | 104 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
f2e39221 JG |
105 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
106 | radeon_fence_unref(&ib->fence); | |
771fe6b9 JG |
107 | } |
108 | ||
75923280 AD |
109 | /** |
110 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
111 | * | |
112 | * @rdev: radeon_device pointer | |
113 | * @ib: IB object to schedule | |
114 | * @const_ib: Const IB to schedule (SI only) | |
115 | * | |
116 | * Schedule an IB on the associated ring (all asics). | |
117 | * Returns 0 on success, error on failure. | |
118 | * | |
119 | * On SI, there are two parallel engines fed from the primary ring, | |
120 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
121 | * resource descriptors have moved to memory, the CE allows you to | |
122 | * prime the caches while the DE is updating register state so that | |
123 | * the resource descriptors will be already in cache when the draw is | |
124 | * processed. To accomplish this, the userspace driver submits two | |
125 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
126 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
127 | * to SI there was just a DE IB. | |
128 | */ | |
4ef72566 CK |
129 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
130 | struct radeon_ib *const_ib) | |
771fe6b9 | 131 | { |
876dc9f3 | 132 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
1654b817 | 133 | int r = 0; |
771fe6b9 | 134 | |
e32eb50d | 135 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 136 | /* TODO: Nothings in the ib we should report. */ |
c507f7ef | 137 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
771fe6b9 JG |
138 | return -EINVAL; |
139 | } | |
ecb114a1 | 140 | |
6cdf6585 | 141 | /* 64 dwords should be enough for fence too */ |
1c61eae4 | 142 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8); |
771fe6b9 | 143 | if (r) { |
c507f7ef | 144 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
145 | return r; |
146 | } | |
1654b817 | 147 | |
529364e0 CK |
148 | /* grab a vm id if necessary */ |
149 | if (ib->vm) { | |
150 | struct radeon_fence *vm_id_fence; | |
151 | vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring); | |
152 | radeon_semaphore_sync_to(ib->semaphore, vm_id_fence); | |
153 | } | |
154 | ||
1654b817 CK |
155 | /* sync with other rings */ |
156 | r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring); | |
157 | if (r) { | |
158 | dev_err(rdev->dev, "failed to sync rings (%d)\n", r); | |
159 | radeon_ring_unlock_undo(rdev, ring); | |
160 | return r; | |
220907d9 | 161 | } |
1654b817 | 162 | |
fa688343 CK |
163 | if (ib->vm) |
164 | radeon_vm_flush(rdev, ib->vm, ib->ring); | |
165 | ||
4ef72566 CK |
166 | if (const_ib) { |
167 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); | |
168 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); | |
169 | } | |
876dc9f3 CK |
170 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
171 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); | |
172 | if (r) { | |
173 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); | |
174 | radeon_ring_unlock_undo(rdev, ring); | |
175 | return r; | |
176 | } | |
4ef72566 CK |
177 | if (const_ib) { |
178 | const_ib->fence = radeon_fence_ref(ib->fence); | |
179 | } | |
fa688343 CK |
180 | |
181 | if (ib->vm) | |
182 | radeon_vm_fence(rdev, ib->vm, ib->fence); | |
183 | ||
e32eb50d | 184 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
185 | return 0; |
186 | } | |
187 | ||
75923280 AD |
188 | /** |
189 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool | |
190 | * | |
191 | * @rdev: radeon_device pointer | |
192 | * | |
193 | * Initialize the suballocator to manage a pool of memory | |
194 | * for use as IBs (all asics). | |
195 | * Returns 0 on success, error on failure. | |
196 | */ | |
771fe6b9 JG |
197 | int radeon_ib_pool_init(struct radeon_device *rdev) |
198 | { | |
c507f7ef | 199 | int r; |
771fe6b9 | 200 | |
c507f7ef | 201 | if (rdev->ib_pool_ready) { |
d54fbd49 JG |
202 | return 0; |
203 | } | |
c507f7ef | 204 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
c3b7fe8b | 205 | RADEON_IB_POOL_SIZE*64*1024, |
6c4f978b | 206 | RADEON_GPU_PAGE_SIZE, |
c3b7fe8b CK |
207 | RADEON_GEM_DOMAIN_GTT); |
208 | if (r) { | |
c3b7fe8b CK |
209 | return r; |
210 | } | |
2898c348 CK |
211 | |
212 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); | |
213 | if (r) { | |
214 | return r; | |
215 | } | |
216 | ||
c507f7ef JG |
217 | rdev->ib_pool_ready = true; |
218 | if (radeon_debugfs_sa_init(rdev)) { | |
219 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); | |
771fe6b9 | 220 | } |
b15ba512 | 221 | return 0; |
771fe6b9 JG |
222 | } |
223 | ||
75923280 AD |
224 | /** |
225 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
226 | * | |
227 | * @rdev: radeon_device pointer | |
228 | * | |
229 | * Tear down the suballocator managing the pool of memory | |
230 | * for use as IBs (all asics). | |
231 | */ | |
771fe6b9 JG |
232 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
233 | { | |
c507f7ef | 234 | if (rdev->ib_pool_ready) { |
2898c348 | 235 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
c507f7ef JG |
236 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
237 | rdev->ib_pool_ready = false; | |
771fe6b9 | 238 | } |
771fe6b9 JG |
239 | } |
240 | ||
75923280 AD |
241 | /** |
242 | * radeon_ib_ring_tests - test IBs on the rings | |
243 | * | |
244 | * @rdev: radeon_device pointer | |
245 | * | |
246 | * Test an IB (Indirect Buffer) on each ring. | |
247 | * If the test fails, disable the ring. | |
248 | * Returns 0 on success, error if the primary GFX ring | |
249 | * IB test fails. | |
250 | */ | |
7bd560e8 CK |
251 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
252 | { | |
253 | unsigned i; | |
254 | int r; | |
255 | ||
256 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
257 | struct radeon_ring *ring = &rdev->ring[i]; | |
258 | ||
259 | if (!ring->ready) | |
260 | continue; | |
261 | ||
262 | r = radeon_ib_test(rdev, i, ring); | |
263 | if (r) { | |
264 | ring->ready = false; | |
265 | ||
266 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
267 | /* oh, oh, that's really bad */ | |
268 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
269 | rdev->accel_working = false; | |
270 | return r; | |
271 | ||
272 | } else { | |
273 | /* still not good, but we can live with it */ | |
274 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
275 | } | |
276 | } | |
277 | } | |
278 | return 0; | |
279 | } | |
280 | ||
771fe6b9 | 281 | /* |
75923280 AD |
282 | * Rings |
283 | * Most engines on the GPU are fed via ring buffers. Ring | |
284 | * buffers are areas of GPU accessible memory that the host | |
285 | * writes commands into and the GPU reads commands out of. | |
286 | * There is a rptr (read pointer) that determines where the | |
287 | * GPU is currently reading, and a wptr (write pointer) | |
288 | * which determines where the host has written. When the | |
289 | * pointers are equal, the ring is idle. When the host | |
290 | * writes commands to the ring buffer, it increments the | |
291 | * wptr. The GPU then starts fetching commands and executes | |
292 | * them until the pointers are equal again. | |
771fe6b9 | 293 | */ |
1109ca09 | 294 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
c507f7ef | 295 | |
75923280 AD |
296 | /** |
297 | * radeon_ring_write - write a value to the ring | |
298 | * | |
299 | * @ring: radeon_ring structure holding ring information | |
300 | * @v: dword (dw) value to write | |
301 | * | |
302 | * Write a value to the requested ring buffer (all asics). | |
303 | */ | |
c507f7ef JG |
304 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
305 | { | |
306 | #if DRM_DEBUG_CODE | |
307 | if (ring->count_dw <= 0) { | |
8ad33cdf | 308 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
c507f7ef JG |
309 | } |
310 | #endif | |
311 | ring->ring[ring->wptr++] = v; | |
312 | ring->wptr &= ring->ptr_mask; | |
313 | ring->count_dw--; | |
314 | ring->ring_free_dw--; | |
315 | } | |
316 | ||
75923280 AD |
317 | /** |
318 | * radeon_ring_supports_scratch_reg - check if the ring supports | |
319 | * writing to scratch registers | |
320 | * | |
321 | * @rdev: radeon_device pointer | |
322 | * @ring: radeon_ring structure holding ring information | |
323 | * | |
324 | * Check if a specific ring supports writing to scratch registers (all asics). | |
325 | * Returns true if the ring supports writing to scratch regs, false if not. | |
326 | */ | |
89d35807 AD |
327 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
328 | struct radeon_ring *ring) | |
329 | { | |
330 | switch (ring->idx) { | |
331 | case RADEON_RING_TYPE_GFX_INDEX: | |
332 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
333 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
334 | return true; | |
335 | default: | |
336 | return false; | |
337 | } | |
338 | } | |
339 | ||
75923280 AD |
340 | /** |
341 | * radeon_ring_free_size - update the free size | |
342 | * | |
343 | * @rdev: radeon_device pointer | |
344 | * @ring: radeon_ring structure holding ring information | |
345 | * | |
346 | * Update the free dw slots in the ring buffer (all asics). | |
347 | */ | |
e32eb50d | 348 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 349 | { |
ff212f25 CK |
350 | uint32_t rptr = radeon_ring_get_rptr(rdev, ring); |
351 | ||
771fe6b9 | 352 | /* This works because ring_size is a power of 2 */ |
ff212f25 | 353 | ring->ring_free_dw = rptr + (ring->ring_size / 4); |
e32eb50d CK |
354 | ring->ring_free_dw -= ring->wptr; |
355 | ring->ring_free_dw &= ring->ptr_mask; | |
356 | if (!ring->ring_free_dw) { | |
82dc62a3 | 357 | /* this is an empty ring */ |
e32eb50d | 358 | ring->ring_free_dw = ring->ring_size / 4; |
82dc62a3 CK |
359 | /* update lockup info to avoid false positive */ |
360 | radeon_ring_lockup_update(rdev, ring); | |
771fe6b9 JG |
361 | } |
362 | } | |
363 | ||
75923280 AD |
364 | /** |
365 | * radeon_ring_alloc - allocate space on the ring buffer | |
366 | * | |
367 | * @rdev: radeon_device pointer | |
368 | * @ring: radeon_ring structure holding ring information | |
369 | * @ndw: number of dwords to allocate in the ring buffer | |
370 | * | |
371 | * Allocate @ndw dwords in the ring buffer (all asics). | |
372 | * Returns 0 on success, error on failure. | |
373 | */ | |
e32eb50d | 374 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
375 | { |
376 | int r; | |
377 | ||
fd5d93a0 AD |
378 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
379 | if (ndw > (ring->ring_size / 4)) | |
380 | return -ENOMEM; | |
771fe6b9 JG |
381 | /* Align requested size with padding so unlock_commit can |
382 | * pad safely */ | |
8444d5c6 | 383 | radeon_ring_free_size(rdev, ring); |
e32eb50d CK |
384 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
385 | while (ndw > (ring->ring_free_dw - 1)) { | |
386 | radeon_ring_free_size(rdev, ring); | |
387 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
388 | break; |
389 | } | |
37615527 | 390 | r = radeon_fence_wait_next(rdev, ring->idx); |
91700f3c | 391 | if (r) |
771fe6b9 | 392 | return r; |
771fe6b9 | 393 | } |
e32eb50d CK |
394 | ring->count_dw = ndw; |
395 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
396 | return 0; |
397 | } | |
398 | ||
75923280 AD |
399 | /** |
400 | * radeon_ring_lock - lock the ring and allocate space on it | |
401 | * | |
402 | * @rdev: radeon_device pointer | |
403 | * @ring: radeon_ring structure holding ring information | |
404 | * @ndw: number of dwords to allocate in the ring buffer | |
405 | * | |
406 | * Lock the ring and allocate @ndw dwords in the ring buffer | |
407 | * (all asics). | |
408 | * Returns 0 on success, error on failure. | |
409 | */ | |
e32eb50d | 410 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
411 | { |
412 | int r; | |
413 | ||
d6999bc7 | 414 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 415 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 416 | if (r) { |
d6999bc7 | 417 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
418 | return r; |
419 | } | |
420 | return 0; | |
421 | } | |
422 | ||
75923280 AD |
423 | /** |
424 | * radeon_ring_commit - tell the GPU to execute the new | |
425 | * commands on the ring buffer | |
426 | * | |
427 | * @rdev: radeon_device pointer | |
428 | * @ring: radeon_ring structure holding ring information | |
429 | * | |
430 | * Update the wptr (write pointer) to tell the GPU to | |
431 | * execute new commands on the ring buffer (all asics). | |
432 | */ | |
e32eb50d | 433 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 434 | { |
771fe6b9 | 435 | /* We pad to match fetch size */ |
07a71330 | 436 | while (ring->wptr & ring->align_mask) { |
78c5560a | 437 | radeon_ring_write(ring, ring->nop); |
771fe6b9 | 438 | } |
85b2331b | 439 | mb(); |
f93bdefe | 440 | radeon_ring_set_wptr(rdev, ring); |
91700f3c MG |
441 | } |
442 | ||
75923280 AD |
443 | /** |
444 | * radeon_ring_unlock_commit - tell the GPU to execute the new | |
445 | * commands on the ring buffer and unlock it | |
446 | * | |
447 | * @rdev: radeon_device pointer | |
448 | * @ring: radeon_ring structure holding ring information | |
449 | * | |
450 | * Call radeon_ring_commit() then unlock the ring (all asics). | |
451 | */ | |
e32eb50d | 452 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 453 | { |
e32eb50d | 454 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 455 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
456 | } |
457 | ||
75923280 AD |
458 | /** |
459 | * radeon_ring_undo - reset the wptr | |
460 | * | |
461 | * @ring: radeon_ring structure holding ring information | |
462 | * | |
501f9d4c | 463 | * Reset the driver's copy of the wptr (all asics). |
75923280 | 464 | */ |
d6999bc7 | 465 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 466 | { |
e32eb50d | 467 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
468 | } |
469 | ||
75923280 AD |
470 | /** |
471 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring | |
472 | * | |
473 | * @ring: radeon_ring structure holding ring information | |
474 | * | |
475 | * Call radeon_ring_undo() then unlock the ring (all asics). | |
476 | */ | |
d6999bc7 CK |
477 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
478 | { | |
479 | radeon_ring_undo(ring); | |
480 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
481 | } |
482 | ||
75923280 | 483 | /** |
501f9d4c | 484 | * radeon_ring_lockup_update - update lockup variables |
75923280 AD |
485 | * |
486 | * @ring: radeon_ring structure holding ring information | |
487 | * | |
488 | * Update the last rptr value and timestamp (all asics). | |
489 | */ | |
ff212f25 CK |
490 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
491 | struct radeon_ring *ring) | |
069211e5 | 492 | { |
aee4aa73 CK |
493 | atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring)); |
494 | atomic64_set(&ring->last_activity, jiffies_64); | |
069211e5 CK |
495 | } |
496 | ||
497 | /** | |
498 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
499 | * @rdev: radeon device structure | |
500 | * @ring: radeon_ring structure holding ring information | |
501 | * | |
2d2fe3f9 | 502 | */ |
069211e5 CK |
503 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
504 | { | |
ff212f25 | 505 | uint32_t rptr = radeon_ring_get_rptr(rdev, ring); |
aee4aa73 CK |
506 | uint64_t last = atomic64_read(&ring->last_activity); |
507 | uint64_t elapsed; | |
069211e5 | 508 | |
aee4aa73 CK |
509 | if (rptr != atomic_read(&ring->last_rptr)) { |
510 | /* ring is still working, no lockup */ | |
ff212f25 | 511 | radeon_ring_lockup_update(rdev, ring); |
069211e5 CK |
512 | return false; |
513 | } | |
aee4aa73 CK |
514 | |
515 | elapsed = jiffies_to_msecs(jiffies_64 - last); | |
3368ff0c | 516 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
aee4aa73 CK |
517 | dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n", |
518 | ring->idx, elapsed); | |
069211e5 CK |
519 | return true; |
520 | } | |
521 | /* give a chance to the GPU ... */ | |
522 | return false; | |
523 | } | |
524 | ||
55d7c221 CK |
525 | /** |
526 | * radeon_ring_backup - Back up the content of a ring | |
527 | * | |
528 | * @rdev: radeon_device pointer | |
529 | * @ring: the ring we want to back up | |
530 | * | |
531 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
532 | */ | |
533 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, | |
534 | uint32_t **data) | |
535 | { | |
536 | unsigned size, ptr, i; | |
55d7c221 CK |
537 | |
538 | /* just in case lock the ring */ | |
539 | mutex_lock(&rdev->ring_lock); | |
540 | *data = NULL; | |
541 | ||
89d35807 | 542 | if (ring->ring_obj == NULL) { |
55d7c221 CK |
543 | mutex_unlock(&rdev->ring_lock); |
544 | return 0; | |
545 | } | |
546 | ||
547 | /* it doesn't make sense to save anything if all fences are signaled */ | |
8b25ed34 | 548 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
55d7c221 CK |
549 | mutex_unlock(&rdev->ring_lock); |
550 | return 0; | |
551 | } | |
552 | ||
553 | /* calculate the number of dw on the ring */ | |
89d35807 AD |
554 | if (ring->rptr_save_reg) |
555 | ptr = RREG32(ring->rptr_save_reg); | |
556 | else if (rdev->wb.enabled) | |
557 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
558 | else { | |
559 | /* no way to read back the next rptr */ | |
560 | mutex_unlock(&rdev->ring_lock); | |
561 | return 0; | |
562 | } | |
563 | ||
55d7c221 CK |
564 | size = ring->wptr + (ring->ring_size / 4); |
565 | size -= ptr; | |
566 | size &= ring->ptr_mask; | |
567 | if (size == 0) { | |
568 | mutex_unlock(&rdev->ring_lock); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | /* and then save the content of the ring */ | |
1e179d4e DC |
573 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
574 | if (!*data) { | |
575 | mutex_unlock(&rdev->ring_lock); | |
576 | return 0; | |
577 | } | |
55d7c221 CK |
578 | for (i = 0; i < size; ++i) { |
579 | (*data)[i] = ring->ring[ptr++]; | |
580 | ptr &= ring->ptr_mask; | |
581 | } | |
582 | ||
583 | mutex_unlock(&rdev->ring_lock); | |
584 | return size; | |
585 | } | |
586 | ||
587 | /** | |
588 | * radeon_ring_restore - append saved commands to the ring again | |
589 | * | |
590 | * @rdev: radeon_device pointer | |
591 | * @ring: ring to append commands to | |
592 | * @size: number of dwords we want to write | |
593 | * @data: saved commands | |
594 | * | |
595 | * Allocates space on the ring and restore the previously saved commands. | |
596 | */ | |
597 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
598 | unsigned size, uint32_t *data) | |
599 | { | |
600 | int i, r; | |
601 | ||
602 | if (!size || !data) | |
603 | return 0; | |
604 | ||
605 | /* restore the saved ring content */ | |
606 | r = radeon_ring_lock(rdev, ring, size); | |
607 | if (r) | |
608 | return r; | |
609 | ||
610 | for (i = 0; i < size; ++i) { | |
611 | radeon_ring_write(ring, data[i]); | |
612 | } | |
613 | ||
614 | radeon_ring_unlock_commit(rdev, ring); | |
615 | kfree(data); | |
616 | return 0; | |
617 | } | |
618 | ||
75923280 AD |
619 | /** |
620 | * radeon_ring_init - init driver ring struct. | |
621 | * | |
622 | * @rdev: radeon_device pointer | |
623 | * @ring: radeon_ring structure holding ring information | |
624 | * @ring_size: size of the ring | |
625 | * @rptr_offs: offset of the rptr writeback location in the WB buffer | |
75923280 AD |
626 | * @nop: nop packet for this ring |
627 | * | |
628 | * Initialize the driver information for the selected ring (all asics). | |
629 | * Returns 0 on success, error on failure. | |
630 | */ | |
e32eb50d | 631 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
ea31bf69 | 632 | unsigned rptr_offs, u32 nop) |
771fe6b9 JG |
633 | { |
634 | int r; | |
635 | ||
e32eb50d CK |
636 | ring->ring_size = ring_size; |
637 | ring->rptr_offs = rptr_offs; | |
78c5560a | 638 | ring->nop = nop; |
771fe6b9 | 639 | /* Allocate ring buffer */ |
e32eb50d CK |
640 | if (ring->ring_obj == NULL) { |
641 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
40f5cf99 AD |
642 | RADEON_GEM_DOMAIN_GTT, |
643 | NULL, &ring->ring_obj); | |
771fe6b9 | 644 | if (r) { |
4c788679 | 645 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
646 | return r; |
647 | } | |
e32eb50d | 648 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
649 | if (unlikely(r != 0)) |
650 | return r; | |
e32eb50d CK |
651 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
652 | &ring->gpu_addr); | |
771fe6b9 | 653 | if (r) { |
e32eb50d | 654 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 655 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
656 | return r; |
657 | } | |
e32eb50d CK |
658 | r = radeon_bo_kmap(ring->ring_obj, |
659 | (void **)&ring->ring); | |
660 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 661 | if (r) { |
4c788679 | 662 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
663 | return r; |
664 | } | |
665 | } | |
e32eb50d CK |
666 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
667 | ring->ring_free_dw = ring->ring_size / 4; | |
89d35807 AD |
668 | if (rdev->wb.enabled) { |
669 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); | |
670 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; | |
671 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; | |
672 | } | |
ec1a6cce CK |
673 | if (radeon_debugfs_ring_init(rdev, ring)) { |
674 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
675 | } | |
ff212f25 | 676 | radeon_ring_lockup_update(rdev, ring); |
771fe6b9 JG |
677 | return 0; |
678 | } | |
679 | ||
75923280 AD |
680 | /** |
681 | * radeon_ring_fini - tear down the driver ring struct. | |
682 | * | |
683 | * @rdev: radeon_device pointer | |
684 | * @ring: radeon_ring structure holding ring information | |
685 | * | |
686 | * Tear down the driver information for the selected ring (all asics). | |
687 | */ | |
e32eb50d | 688 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 689 | { |
4c788679 | 690 | int r; |
ca2af923 | 691 | struct radeon_bo *ring_obj; |
4c788679 | 692 | |
d6999bc7 | 693 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 694 | ring_obj = ring->ring_obj; |
d6999bc7 | 695 | ring->ready = false; |
e32eb50d CK |
696 | ring->ring = NULL; |
697 | ring->ring_obj = NULL; | |
d6999bc7 | 698 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
699 | |
700 | if (ring_obj) { | |
701 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 702 | if (likely(r == 0)) { |
ca2af923 AD |
703 | radeon_bo_kunmap(ring_obj); |
704 | radeon_bo_unpin(ring_obj); | |
705 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 706 | } |
ca2af923 | 707 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 708 | } |
771fe6b9 JG |
709 | } |
710 | ||
771fe6b9 JG |
711 | /* |
712 | * Debugfs info | |
713 | */ | |
714 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
715 | |
716 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
717 | { | |
718 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
719 | struct drm_device *dev = node->minor->dev; | |
720 | struct radeon_device *rdev = dev->dev_private; | |
721 | int ridx = *(int*)node->info_ent->data; | |
722 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
df893a25 CK |
723 | |
724 | uint32_t rptr, wptr, rptr_next; | |
af9720f4 CK |
725 | unsigned count, i, j; |
726 | ||
727 | radeon_ring_free_size(rdev, ring); | |
728 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
df893a25 CK |
729 | |
730 | wptr = radeon_ring_get_wptr(rdev, ring); | |
ea31bf69 AD |
731 | seq_printf(m, "wptr: 0x%08x [%5d]\n", |
732 | wptr, wptr); | |
df893a25 CK |
733 | |
734 | rptr = radeon_ring_get_rptr(rdev, ring); | |
ea31bf69 AD |
735 | seq_printf(m, "rptr: 0x%08x [%5d]\n", |
736 | rptr, rptr); | |
df893a25 | 737 | |
45df6803 | 738 | if (ring->rptr_save_reg) { |
df893a25 CK |
739 | rptr_next = RREG32(ring->rptr_save_reg); |
740 | seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n", | |
741 | ring->rptr_save_reg, rptr_next, rptr_next); | |
742 | } else | |
743 | rptr_next = ~0; | |
744 | ||
745 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", | |
746 | ring->wptr, ring->wptr); | |
df893a25 CK |
747 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", |
748 | ring->last_semaphore_signal_addr); | |
749 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", | |
750 | ring->last_semaphore_wait_addr); | |
af9720f4 CK |
751 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
752 | seq_printf(m, "%u dwords in ring\n", count); | |
df893a25 CK |
753 | |
754 | if (!ring->ready) | |
755 | return 0; | |
756 | ||
4d009190 JG |
757 | /* print 8 dw before current rptr as often it's the last executed |
758 | * packet that is the root issue | |
759 | */ | |
df893a25 CK |
760 | i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; |
761 | for (j = 0; j <= (count + 32); j++) { | |
762 | seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); | |
763 | if (rptr == i) | |
764 | seq_puts(m, " *"); | |
765 | if (rptr_next == i) | |
766 | seq_puts(m, " #"); | |
767 | seq_puts(m, "\n"); | |
768 | i = (i + 1) & ring->ptr_mask; | |
af9720f4 CK |
769 | } |
770 | return 0; | |
771 | } | |
772 | ||
f2ba57b5 CK |
773 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
774 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
775 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
776 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; | |
777 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; | |
778 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; | |
d93f7937 CK |
779 | static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX; |
780 | static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX; | |
af9720f4 CK |
781 | |
782 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
f2ba57b5 CK |
783 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
784 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, | |
785 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, | |
786 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, | |
787 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, | |
788 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, | |
d93f7937 CK |
789 | {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index}, |
790 | {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index}, | |
af9720f4 CK |
791 | }; |
792 | ||
711a9729 CK |
793 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
794 | { | |
795 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
796 | struct drm_device *dev = node->minor->dev; | |
797 | struct radeon_device *rdev = dev->dev_private; | |
798 | ||
c507f7ef | 799 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
711a9729 CK |
800 | |
801 | return 0; | |
802 | ||
803 | } | |
804 | ||
805 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
806 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
807 | }; | |
808 | ||
771fe6b9 JG |
809 | #endif |
810 | ||
1109ca09 | 811 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
812 | { |
813 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
814 | unsigned i; |
815 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
816 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
817 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
818 | unsigned r; | |
819 | ||
820 | if (&rdev->ring[ridx] != ring) | |
821 | continue; | |
822 | ||
823 | r = radeon_debugfs_add_files(rdev, info, 1); | |
824 | if (r) | |
825 | return r; | |
826 | } | |
af9720f4 | 827 | #endif |
ec1a6cce | 828 | return 0; |
af9720f4 CK |
829 | } |
830 | ||
1109ca09 | 831 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
771fe6b9 JG |
832 | { |
833 | #if defined(CONFIG_DEBUG_FS) | |
c507f7ef | 834 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
771fe6b9 JG |
835 | #else |
836 | return 0; | |
837 | #endif | |
838 | } |