drm/radeon: rework ring syncing code
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_ring.c
CommitLineData
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
c507f7ef 27 * Christian König
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28 */
29#include <linux/seq_file.h>
5a0e3ad6 30#include <linux/slab.h>
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31#include "drmP.h"
32#include "radeon_drm.h"
33#include "radeon_reg.h"
34#include "radeon.h"
35#include "atom.h"
36
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37/*
38 * IB.
39 */
40int radeon_debugfs_sa_init(struct radeon_device *rdev);
771fe6b9 41
69e130a6 42int radeon_ib_get(struct radeon_device *rdev, int ring,
f2e39221 43 struct radeon_ib *ib, unsigned size)
771fe6b9 44{
220907d9 45 int i, r;
b15ba512 46
f2e39221 47 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
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48 if (r) {
49 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
c507f7ef 50 return r;
b15ba512 51 }
c507f7ef 52
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53 r = radeon_semaphore_create(rdev, &ib->semaphore);
54 if (r) {
55 return r;
56 }
57
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58 ib->ring = ring;
59 ib->fence = NULL;
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60 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
61 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
62 ib->vm_id = 0;
63 ib->is_const_ib = false;
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64 for (i = 0; i < RADEON_NUM_RINGS; ++i)
65 ib->sync_to[i] = NULL;
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66
67 return 0;
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68}
69
f2e39221 70void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
771fe6b9 71{
220907d9 72 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
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73 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
74 radeon_fence_unref(&ib->fence);
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75}
76
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77int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
78{
876dc9f3 79 struct radeon_ring *ring = &rdev->ring[ib->ring];
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80 bool need_sync = false;
81 int i, r = 0;
771fe6b9 82
e32eb50d 83 if (!ib->length_dw || !ring->ready) {
771fe6b9 84 /* TODO: Nothings in the ib we should report. */
c507f7ef 85 dev_err(rdev->dev, "couldn't schedule ib\n");
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86 return -EINVAL;
87 }
ecb114a1 88
6cdf6585 89 /* 64 dwords should be enough for fence too */
220907d9 90 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
771fe6b9 91 if (r) {
c507f7ef 92 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
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93 return r;
94 }
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95 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
96 struct radeon_fence *fence = ib->sync_to[i];
97 if (radeon_fence_need_sync(fence, ib->ring)) {
98 need_sync = true;
99 radeon_semaphore_sync_rings(rdev, ib->semaphore,
100 fence->ring, ib->ring);
101 radeon_fence_note_sync(fence, ib->ring);
102 }
103 }
104 /* immediately free semaphore when we don't need to sync */
105 if (!need_sync) {
106 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
107 }
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108 radeon_ring_ib_execute(rdev, ib->ring, ib);
109 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
110 if (r) {
111 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
112 radeon_ring_unlock_undo(rdev, ring);
113 return r;
114 }
e32eb50d 115 radeon_ring_unlock_commit(rdev, ring);
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116 return 0;
117}
118
119int radeon_ib_pool_init(struct radeon_device *rdev)
120{
c507f7ef 121 int r;
771fe6b9 122
c507f7ef 123 if (rdev->ib_pool_ready) {
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124 return 0;
125 }
c507f7ef 126 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
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127 RADEON_IB_POOL_SIZE*64*1024,
128 RADEON_GEM_DOMAIN_GTT);
129 if (r) {
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130 return r;
131 }
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132 rdev->ib_pool_ready = true;
133 if (radeon_debugfs_sa_init(rdev)) {
134 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
771fe6b9 135 }
b15ba512 136 return 0;
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137}
138
139void radeon_ib_pool_fini(struct radeon_device *rdev)
140{
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141 if (rdev->ib_pool_ready) {
142 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
143 rdev->ib_pool_ready = false;
771fe6b9 144 }
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145}
146
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147int radeon_ib_pool_start(struct radeon_device *rdev)
148{
c507f7ef 149 return radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
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150}
151
152int radeon_ib_pool_suspend(struct radeon_device *rdev)
153{
c507f7ef 154 return radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
b15ba512 155}
771fe6b9 156
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157int radeon_ib_ring_tests(struct radeon_device *rdev)
158{
159 unsigned i;
160 int r;
161
162 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
163 struct radeon_ring *ring = &rdev->ring[i];
164
165 if (!ring->ready)
166 continue;
167
168 r = radeon_ib_test(rdev, i, ring);
169 if (r) {
170 ring->ready = false;
171
172 if (i == RADEON_RING_TYPE_GFX_INDEX) {
173 /* oh, oh, that's really bad */
174 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
175 rdev->accel_working = false;
176 return r;
177
178 } else {
179 /* still not good, but we can live with it */
180 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
181 }
182 }
183 }
184 return 0;
185}
186
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187/*
188 * Ring.
189 */
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190int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
191
192void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
193{
194#if DRM_DEBUG_CODE
195 if (ring->count_dw <= 0) {
196 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
197 }
198#endif
199 ring->ring[ring->wptr++] = v;
200 ring->wptr &= ring->ptr_mask;
201 ring->count_dw--;
202 ring->ring_free_dw--;
203}
204
e32eb50d 205int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring)
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206{
207 /* r1xx-r5xx only has CP ring */
208 if (rdev->family < CHIP_R600)
209 return RADEON_RING_TYPE_GFX_INDEX;
210
211 if (rdev->family >= CHIP_CAYMAN) {
e32eb50d 212 if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
bf852799 213 return CAYMAN_RING_TYPE_CP1_INDEX;
e32eb50d 214 else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
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215 return CAYMAN_RING_TYPE_CP2_INDEX;
216 }
217 return RADEON_RING_TYPE_GFX_INDEX;
218}
219
e32eb50d 220void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 221{
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222 u32 rptr;
223
724c80e1 224 if (rdev->wb.enabled)
78c5560a 225 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
5596a9db 226 else
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227 rptr = RREG32(ring->rptr_reg);
228 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
771fe6b9 229 /* This works because ring_size is a power of 2 */
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230 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
231 ring->ring_free_dw -= ring->wptr;
232 ring->ring_free_dw &= ring->ptr_mask;
233 if (!ring->ring_free_dw) {
234 ring->ring_free_dw = ring->ring_size / 4;
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235 }
236}
237
7b1f2485 238
e32eb50d 239int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
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240{
241 int r;
242
243 /* Align requested size with padding so unlock_commit can
244 * pad safely */
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245 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
246 while (ndw > (ring->ring_free_dw - 1)) {
247 radeon_ring_free_size(rdev, ring);
248 if (ndw < ring->ring_free_dw) {
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249 break;
250 }
8a47cc9e 251 r = radeon_fence_wait_next_locked(rdev, radeon_ring_index(rdev, ring));
91700f3c 252 if (r)
771fe6b9 253 return r;
771fe6b9 254 }
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255 ring->count_dw = ndw;
256 ring->wptr_old = ring->wptr;
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257 return 0;
258}
259
e32eb50d 260int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
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261{
262 int r;
263
d6999bc7 264 mutex_lock(&rdev->ring_lock);
e32eb50d 265 r = radeon_ring_alloc(rdev, ring, ndw);
91700f3c 266 if (r) {
d6999bc7 267 mutex_unlock(&rdev->ring_lock);
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268 return r;
269 }
270 return 0;
271}
272
e32eb50d 273void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
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274{
275 unsigned count_dw_pad;
276 unsigned i;
277
278 /* We pad to match fetch size */
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279 count_dw_pad = (ring->align_mask + 1) -
280 (ring->wptr & ring->align_mask);
771fe6b9 281 for (i = 0; i < count_dw_pad; i++) {
78c5560a 282 radeon_ring_write(ring, ring->nop);
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283 }
284 DRM_MEMORYBARRIER();
78c5560a 285 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
e32eb50d 286 (void)RREG32(ring->wptr_reg);
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287}
288
e32eb50d 289void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
91700f3c 290{
e32eb50d 291 radeon_ring_commit(rdev, ring);
d6999bc7 292 mutex_unlock(&rdev->ring_lock);
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293}
294
d6999bc7 295void radeon_ring_undo(struct radeon_ring *ring)
771fe6b9 296{
e32eb50d 297 ring->wptr = ring->wptr_old;
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298}
299
300void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
301{
302 radeon_ring_undo(ring);
303 mutex_unlock(&rdev->ring_lock);
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304}
305
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306void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
307{
308 int r;
309
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310 radeon_ring_free_size(rdev, ring);
311 if (ring->rptr == ring->wptr) {
312 r = radeon_ring_alloc(rdev, ring, 1);
313 if (!r) {
314 radeon_ring_write(ring, ring->nop);
315 radeon_ring_commit(rdev, ring);
316 }
317 }
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318}
319
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320void radeon_ring_lockup_update(struct radeon_ring *ring)
321{
322 ring->last_rptr = ring->rptr;
323 ring->last_activity = jiffies;
324}
325
326/**
327 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
328 * @rdev: radeon device structure
329 * @ring: radeon_ring structure holding ring information
330 *
331 * We don't need to initialize the lockup tracking information as we will either
332 * have CP rptr to a different value of jiffies wrap around which will force
333 * initialization of the lockup tracking informations.
334 *
335 * A possible false positivie is if we get call after while and last_cp_rptr ==
336 * the current CP rptr, even if it's unlikely it might happen. To avoid this
337 * if the elapsed time since last call is bigger than 2 second than we return
338 * false and update the tracking information. Due to this the caller must call
339 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
340 * the fencing code should be cautious about that.
341 *
342 * Caller should write to the ring to force CP to do something so we don't get
343 * false positive when CP is just gived nothing to do.
344 *
345 **/
346bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
347{
348 unsigned long cjiffies, elapsed;
349 uint32_t rptr;
350
351 cjiffies = jiffies;
352 if (!time_after(cjiffies, ring->last_activity)) {
353 /* likely a wrap around */
354 radeon_ring_lockup_update(ring);
355 return false;
356 }
357 rptr = RREG32(ring->rptr_reg);
358 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
359 if (ring->rptr != ring->last_rptr) {
360 /* CP is still working no lockup */
361 radeon_ring_lockup_update(ring);
362 return false;
363 }
364 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
3368ff0c 365 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
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366 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
367 return true;
368 }
369 /* give a chance to the GPU ... */
370 return false;
371}
372
e32eb50d 373int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
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374 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
375 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
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376{
377 int r;
378
e32eb50d
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379 ring->ring_size = ring_size;
380 ring->rptr_offs = rptr_offs;
381 ring->rptr_reg = rptr_reg;
382 ring->wptr_reg = wptr_reg;
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383 ring->ptr_reg_shift = ptr_reg_shift;
384 ring->ptr_reg_mask = ptr_reg_mask;
385 ring->nop = nop;
771fe6b9 386 /* Allocate ring buffer */
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387 if (ring->ring_obj == NULL) {
388 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
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AD
389 RADEON_GEM_DOMAIN_GTT,
390 NULL, &ring->ring_obj);
771fe6b9 391 if (r) {
4c788679 392 dev_err(rdev->dev, "(%d) ring create failed\n", r);
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393 return r;
394 }
e32eb50d 395 r = radeon_bo_reserve(ring->ring_obj, false);
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396 if (unlikely(r != 0))
397 return r;
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398 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
399 &ring->gpu_addr);
771fe6b9 400 if (r) {
e32eb50d 401 radeon_bo_unreserve(ring->ring_obj);
4c788679 402 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
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403 return r;
404 }
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405 r = radeon_bo_kmap(ring->ring_obj,
406 (void **)&ring->ring);
407 radeon_bo_unreserve(ring->ring_obj);
771fe6b9 408 if (r) {
4c788679 409 dev_err(rdev->dev, "(%d) ring map failed\n", r);
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410 return r;
411 }
412 }
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413 ring->ptr_mask = (ring->ring_size / 4) - 1;
414 ring->ring_free_dw = ring->ring_size / 4;
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415 if (radeon_debugfs_ring_init(rdev, ring)) {
416 DRM_ERROR("Failed to register debugfs file for rings !\n");
417 }
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418 return 0;
419}
420
e32eb50d 421void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 422{
4c788679 423 int r;
ca2af923 424 struct radeon_bo *ring_obj;
4c788679 425
d6999bc7 426 mutex_lock(&rdev->ring_lock);
e32eb50d 427 ring_obj = ring->ring_obj;
d6999bc7 428 ring->ready = false;
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429 ring->ring = NULL;
430 ring->ring_obj = NULL;
d6999bc7 431 mutex_unlock(&rdev->ring_lock);
ca2af923
AD
432
433 if (ring_obj) {
434 r = radeon_bo_reserve(ring_obj, false);
4c788679 435 if (likely(r == 0)) {
ca2af923
AD
436 radeon_bo_kunmap(ring_obj);
437 radeon_bo_unpin(ring_obj);
438 radeon_bo_unreserve(ring_obj);
4c788679 439 }
ca2af923 440 radeon_bo_unref(&ring_obj);
771fe6b9 441 }
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442}
443
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444/*
445 * Debugfs info
446 */
447#if defined(CONFIG_DEBUG_FS)
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448
449static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
450{
451 struct drm_info_node *node = (struct drm_info_node *) m->private;
452 struct drm_device *dev = node->minor->dev;
453 struct radeon_device *rdev = dev->dev_private;
454 int ridx = *(int*)node->info_ent->data;
455 struct radeon_ring *ring = &rdev->ring[ridx];
456 unsigned count, i, j;
457
458 radeon_ring_free_size(rdev, ring);
459 count = (ring->ring_size / 4) - ring->ring_free_dw;
460 seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
461 seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
462 seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
463 seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
464 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
465 seq_printf(m, "%u dwords in ring\n", count);
466 i = ring->rptr;
467 for (j = 0; j <= count; j++) {
468 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
469 i = (i + 1) & ring->ptr_mask;
470 }
471 return 0;
472}
473
474static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
475static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
476static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
477
478static struct drm_info_list radeon_debugfs_ring_info_list[] = {
479 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
480 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
481 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
482};
483
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CK
484static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
485{
486 struct drm_info_node *node = (struct drm_info_node *) m->private;
487 struct drm_device *dev = node->minor->dev;
488 struct radeon_device *rdev = dev->dev_private;
489
c507f7ef 490 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
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491
492 return 0;
493
494}
495
496static struct drm_info_list radeon_debugfs_sa_list[] = {
497 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
498};
499
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500#endif
501
ec1a6cce 502int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
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503{
504#if defined(CONFIG_DEBUG_FS)
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505 unsigned i;
506 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
507 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
508 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
509 unsigned r;
510
511 if (&rdev->ring[ridx] != ring)
512 continue;
513
514 r = radeon_debugfs_add_files(rdev, info, 1);
515 if (r)
516 return r;
517 }
af9720f4 518#endif
ec1a6cce 519 return 0;
af9720f4
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520}
521
c507f7ef 522int radeon_debugfs_sa_init(struct radeon_device *rdev)
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523{
524#if defined(CONFIG_DEBUG_FS)
c507f7ef 525 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
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526#else
527 return 0;
528#endif
529}
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