Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
c507f7ef | 27 | * Christian König |
771fe6b9 JG |
28 | */ |
29 | #include <linux/seq_file.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
35 | #include "atom.h" | |
36 | ||
c507f7ef | 37 | /* |
75923280 AD |
38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
40 | * commands are stored. You can put a pointer to the IB in the | |
41 | * command ring and the hw will fetch the commands from the IB | |
42 | * and execute them. Generally userspace acceleration drivers | |
43 | * produce command buffers which are send to the kernel and | |
44 | * put in IBs for execution by the requested ring. | |
c507f7ef | 45 | */ |
1109ca09 | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
771fe6b9 | 47 | |
75923280 AD |
48 | /** |
49 | * radeon_ib_get - request an IB (Indirect Buffer) | |
50 | * | |
51 | * @rdev: radeon_device pointer | |
52 | * @ring: ring index the IB is associated with | |
53 | * @ib: IB object returned | |
54 | * @size: requested IB size | |
55 | * | |
56 | * Request an IB (all asics). IBs are allocated using the | |
57 | * suballocator. | |
58 | * Returns 0 on success, error on failure. | |
59 | */ | |
69e130a6 | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
61 | struct radeon_ib *ib, struct radeon_vm *vm, |
62 | unsigned size) | |
771fe6b9 | 63 | { |
220907d9 | 64 | int i, r; |
b15ba512 | 65 | |
f2e39221 | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
c507f7ef JG |
67 | if (r) { |
68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); | |
c507f7ef | 69 | return r; |
b15ba512 | 70 | } |
c507f7ef | 71 | |
220907d9 CK |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
73 | if (r) { | |
74 | return r; | |
75 | } | |
76 | ||
876dc9f3 CK |
77 | ib->ring = ring; |
78 | ib->fence = NULL; | |
f2e39221 | 79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
4bf3dd92 CK |
80 | ib->vm = vm; |
81 | if (vm) { | |
ca19f21e CK |
82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
83 | * space and soffset is the offset inside the pool bo | |
4bf3dd92 | 84 | */ |
ca19f21e | 85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
4bf3dd92 CK |
86 | } else { |
87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); | |
88 | } | |
f2e39221 | 89 | ib->is_const_ib = false; |
220907d9 CK |
90 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
91 | ib->sync_to[i] = NULL; | |
c507f7ef JG |
92 | |
93 | return 0; | |
771fe6b9 JG |
94 | } |
95 | ||
75923280 AD |
96 | /** |
97 | * radeon_ib_free - free an IB (Indirect Buffer) | |
98 | * | |
99 | * @rdev: radeon_device pointer | |
100 | * @ib: IB object to free | |
101 | * | |
102 | * Free an IB (all asics). | |
103 | */ | |
f2e39221 | 104 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
771fe6b9 | 105 | { |
220907d9 | 106 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
f2e39221 JG |
107 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
108 | radeon_fence_unref(&ib->fence); | |
771fe6b9 JG |
109 | } |
110 | ||
43f1214a AD |
111 | /** |
112 | * radeon_ib_sync_to - sync to fence before executing the IB | |
113 | * | |
114 | * @ib: IB object to add fence to | |
115 | * @fence: fence to sync to | |
116 | * | |
117 | * Sync to the fence before executing the IB | |
118 | */ | |
119 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence) | |
120 | { | |
121 | struct radeon_fence *other; | |
122 | ||
123 | if (!fence) | |
124 | return; | |
125 | ||
126 | other = ib->sync_to[fence->ring]; | |
127 | ib->sync_to[fence->ring] = radeon_fence_later(fence, other); | |
128 | } | |
129 | ||
75923280 AD |
130 | /** |
131 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
132 | * | |
133 | * @rdev: radeon_device pointer | |
134 | * @ib: IB object to schedule | |
135 | * @const_ib: Const IB to schedule (SI only) | |
136 | * | |
137 | * Schedule an IB on the associated ring (all asics). | |
138 | * Returns 0 on success, error on failure. | |
139 | * | |
140 | * On SI, there are two parallel engines fed from the primary ring, | |
141 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
142 | * resource descriptors have moved to memory, the CE allows you to | |
143 | * prime the caches while the DE is updating register state so that | |
144 | * the resource descriptors will be already in cache when the draw is | |
145 | * processed. To accomplish this, the userspace driver submits two | |
146 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
147 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
148 | * to SI there was just a DE IB. | |
149 | */ | |
4ef72566 CK |
150 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
151 | struct radeon_ib *const_ib) | |
771fe6b9 | 152 | { |
876dc9f3 | 153 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
220907d9 CK |
154 | bool need_sync = false; |
155 | int i, r = 0; | |
771fe6b9 | 156 | |
e32eb50d | 157 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 158 | /* TODO: Nothings in the ib we should report. */ |
c507f7ef | 159 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
771fe6b9 JG |
160 | return -EINVAL; |
161 | } | |
ecb114a1 | 162 | |
6cdf6585 | 163 | /* 64 dwords should be enough for fence too */ |
220907d9 | 164 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
771fe6b9 | 165 | if (r) { |
c507f7ef | 166 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
167 | return r; |
168 | } | |
220907d9 CK |
169 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
170 | struct radeon_fence *fence = ib->sync_to[i]; | |
171 | if (radeon_fence_need_sync(fence, ib->ring)) { | |
172 | need_sync = true; | |
173 | radeon_semaphore_sync_rings(rdev, ib->semaphore, | |
174 | fence->ring, ib->ring); | |
175 | radeon_fence_note_sync(fence, ib->ring); | |
176 | } | |
177 | } | |
178 | /* immediately free semaphore when we don't need to sync */ | |
179 | if (!need_sync) { | |
180 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); | |
181 | } | |
9b40e5d8 CK |
182 | /* if we can't remember our last VM flush then flush now! */ |
183 | if (ib->vm && !ib->vm->last_flush) { | |
498522b4 | 184 | radeon_ring_vm_flush(rdev, ib->ring, ib->vm); |
9b40e5d8 | 185 | } |
4ef72566 CK |
186 | if (const_ib) { |
187 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); | |
188 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); | |
189 | } | |
876dc9f3 CK |
190 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
191 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); | |
192 | if (r) { | |
193 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); | |
194 | radeon_ring_unlock_undo(rdev, ring); | |
195 | return r; | |
196 | } | |
4ef72566 CK |
197 | if (const_ib) { |
198 | const_ib->fence = radeon_fence_ref(ib->fence); | |
199 | } | |
9b40e5d8 CK |
200 | /* we just flushed the VM, remember that */ |
201 | if (ib->vm && !ib->vm->last_flush) { | |
202 | ib->vm->last_flush = radeon_fence_ref(ib->fence); | |
203 | } | |
e32eb50d | 204 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
205 | return 0; |
206 | } | |
207 | ||
75923280 AD |
208 | /** |
209 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool | |
210 | * | |
211 | * @rdev: radeon_device pointer | |
212 | * | |
213 | * Initialize the suballocator to manage a pool of memory | |
214 | * for use as IBs (all asics). | |
215 | * Returns 0 on success, error on failure. | |
216 | */ | |
771fe6b9 JG |
217 | int radeon_ib_pool_init(struct radeon_device *rdev) |
218 | { | |
c507f7ef | 219 | int r; |
771fe6b9 | 220 | |
c507f7ef | 221 | if (rdev->ib_pool_ready) { |
d54fbd49 JG |
222 | return 0; |
223 | } | |
c507f7ef | 224 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
c3b7fe8b CK |
225 | RADEON_IB_POOL_SIZE*64*1024, |
226 | RADEON_GEM_DOMAIN_GTT); | |
227 | if (r) { | |
c3b7fe8b CK |
228 | return r; |
229 | } | |
2898c348 CK |
230 | |
231 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); | |
232 | if (r) { | |
233 | return r; | |
234 | } | |
235 | ||
c507f7ef JG |
236 | rdev->ib_pool_ready = true; |
237 | if (radeon_debugfs_sa_init(rdev)) { | |
238 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); | |
771fe6b9 | 239 | } |
b15ba512 | 240 | return 0; |
771fe6b9 JG |
241 | } |
242 | ||
75923280 AD |
243 | /** |
244 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
245 | * | |
246 | * @rdev: radeon_device pointer | |
247 | * | |
248 | * Tear down the suballocator managing the pool of memory | |
249 | * for use as IBs (all asics). | |
250 | */ | |
771fe6b9 JG |
251 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
252 | { | |
c507f7ef | 253 | if (rdev->ib_pool_ready) { |
2898c348 | 254 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
c507f7ef JG |
255 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
256 | rdev->ib_pool_ready = false; | |
771fe6b9 | 257 | } |
771fe6b9 JG |
258 | } |
259 | ||
75923280 AD |
260 | /** |
261 | * radeon_ib_ring_tests - test IBs on the rings | |
262 | * | |
263 | * @rdev: radeon_device pointer | |
264 | * | |
265 | * Test an IB (Indirect Buffer) on each ring. | |
266 | * If the test fails, disable the ring. | |
267 | * Returns 0 on success, error if the primary GFX ring | |
268 | * IB test fails. | |
269 | */ | |
7bd560e8 CK |
270 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
271 | { | |
272 | unsigned i; | |
273 | int r; | |
274 | ||
275 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
276 | struct radeon_ring *ring = &rdev->ring[i]; | |
277 | ||
278 | if (!ring->ready) | |
279 | continue; | |
280 | ||
281 | r = radeon_ib_test(rdev, i, ring); | |
282 | if (r) { | |
283 | ring->ready = false; | |
284 | ||
285 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
286 | /* oh, oh, that's really bad */ | |
287 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
288 | rdev->accel_working = false; | |
289 | return r; | |
290 | ||
291 | } else { | |
292 | /* still not good, but we can live with it */ | |
293 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
294 | } | |
295 | } | |
296 | } | |
297 | return 0; | |
298 | } | |
299 | ||
771fe6b9 | 300 | /* |
75923280 AD |
301 | * Rings |
302 | * Most engines on the GPU are fed via ring buffers. Ring | |
303 | * buffers are areas of GPU accessible memory that the host | |
304 | * writes commands into and the GPU reads commands out of. | |
305 | * There is a rptr (read pointer) that determines where the | |
306 | * GPU is currently reading, and a wptr (write pointer) | |
307 | * which determines where the host has written. When the | |
308 | * pointers are equal, the ring is idle. When the host | |
309 | * writes commands to the ring buffer, it increments the | |
310 | * wptr. The GPU then starts fetching commands and executes | |
311 | * them until the pointers are equal again. | |
771fe6b9 | 312 | */ |
1109ca09 | 313 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
c507f7ef | 314 | |
75923280 AD |
315 | /** |
316 | * radeon_ring_write - write a value to the ring | |
317 | * | |
318 | * @ring: radeon_ring structure holding ring information | |
319 | * @v: dword (dw) value to write | |
320 | * | |
321 | * Write a value to the requested ring buffer (all asics). | |
322 | */ | |
c507f7ef JG |
323 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
324 | { | |
325 | #if DRM_DEBUG_CODE | |
326 | if (ring->count_dw <= 0) { | |
8ad33cdf | 327 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
c507f7ef JG |
328 | } |
329 | #endif | |
330 | ring->ring[ring->wptr++] = v; | |
331 | ring->wptr &= ring->ptr_mask; | |
332 | ring->count_dw--; | |
333 | ring->ring_free_dw--; | |
334 | } | |
335 | ||
75923280 AD |
336 | /** |
337 | * radeon_ring_supports_scratch_reg - check if the ring supports | |
338 | * writing to scratch registers | |
339 | * | |
340 | * @rdev: radeon_device pointer | |
341 | * @ring: radeon_ring structure holding ring information | |
342 | * | |
343 | * Check if a specific ring supports writing to scratch registers (all asics). | |
344 | * Returns true if the ring supports writing to scratch regs, false if not. | |
345 | */ | |
89d35807 AD |
346 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
347 | struct radeon_ring *ring) | |
348 | { | |
349 | switch (ring->idx) { | |
350 | case RADEON_RING_TYPE_GFX_INDEX: | |
351 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
352 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
353 | return true; | |
354 | default: | |
355 | return false; | |
356 | } | |
357 | } | |
358 | ||
75923280 AD |
359 | /** |
360 | * radeon_ring_free_size - update the free size | |
361 | * | |
362 | * @rdev: radeon_device pointer | |
363 | * @ring: radeon_ring structure holding ring information | |
364 | * | |
365 | * Update the free dw slots in the ring buffer (all asics). | |
366 | */ | |
e32eb50d | 367 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 368 | { |
78c5560a AD |
369 | u32 rptr; |
370 | ||
f2ba57b5 | 371 | if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX]) |
78c5560a | 372 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
5596a9db | 373 | else |
78c5560a AD |
374 | rptr = RREG32(ring->rptr_reg); |
375 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
771fe6b9 | 376 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
377 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
378 | ring->ring_free_dw -= ring->wptr; | |
379 | ring->ring_free_dw &= ring->ptr_mask; | |
380 | if (!ring->ring_free_dw) { | |
381 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
382 | } |
383 | } | |
384 | ||
75923280 AD |
385 | /** |
386 | * radeon_ring_alloc - allocate space on the ring buffer | |
387 | * | |
388 | * @rdev: radeon_device pointer | |
389 | * @ring: radeon_ring structure holding ring information | |
390 | * @ndw: number of dwords to allocate in the ring buffer | |
391 | * | |
392 | * Allocate @ndw dwords in the ring buffer (all asics). | |
393 | * Returns 0 on success, error on failure. | |
394 | */ | |
e32eb50d | 395 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
396 | { |
397 | int r; | |
398 | ||
fd5d93a0 AD |
399 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
400 | if (ndw > (ring->ring_size / 4)) | |
401 | return -ENOMEM; | |
771fe6b9 JG |
402 | /* Align requested size with padding so unlock_commit can |
403 | * pad safely */ | |
e32eb50d CK |
404 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
405 | while (ndw > (ring->ring_free_dw - 1)) { | |
406 | radeon_ring_free_size(rdev, ring); | |
407 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
408 | break; |
409 | } | |
8b25ed34 | 410 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
91700f3c | 411 | if (r) |
771fe6b9 | 412 | return r; |
771fe6b9 | 413 | } |
e32eb50d CK |
414 | ring->count_dw = ndw; |
415 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
416 | return 0; |
417 | } | |
418 | ||
75923280 AD |
419 | /** |
420 | * radeon_ring_lock - lock the ring and allocate space on it | |
421 | * | |
422 | * @rdev: radeon_device pointer | |
423 | * @ring: radeon_ring structure holding ring information | |
424 | * @ndw: number of dwords to allocate in the ring buffer | |
425 | * | |
426 | * Lock the ring and allocate @ndw dwords in the ring buffer | |
427 | * (all asics). | |
428 | * Returns 0 on success, error on failure. | |
429 | */ | |
e32eb50d | 430 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
431 | { |
432 | int r; | |
433 | ||
d6999bc7 | 434 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 435 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 436 | if (r) { |
d6999bc7 | 437 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
438 | return r; |
439 | } | |
440 | return 0; | |
441 | } | |
442 | ||
75923280 AD |
443 | /** |
444 | * radeon_ring_commit - tell the GPU to execute the new | |
445 | * commands on the ring buffer | |
446 | * | |
447 | * @rdev: radeon_device pointer | |
448 | * @ring: radeon_ring structure holding ring information | |
449 | * | |
450 | * Update the wptr (write pointer) to tell the GPU to | |
451 | * execute new commands on the ring buffer (all asics). | |
452 | */ | |
e32eb50d | 453 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 454 | { |
771fe6b9 | 455 | /* We pad to match fetch size */ |
07a71330 | 456 | while (ring->wptr & ring->align_mask) { |
78c5560a | 457 | radeon_ring_write(ring, ring->nop); |
771fe6b9 JG |
458 | } |
459 | DRM_MEMORYBARRIER(); | |
78c5560a | 460 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
e32eb50d | 461 | (void)RREG32(ring->wptr_reg); |
91700f3c MG |
462 | } |
463 | ||
75923280 AD |
464 | /** |
465 | * radeon_ring_unlock_commit - tell the GPU to execute the new | |
466 | * commands on the ring buffer and unlock it | |
467 | * | |
468 | * @rdev: radeon_device pointer | |
469 | * @ring: radeon_ring structure holding ring information | |
470 | * | |
471 | * Call radeon_ring_commit() then unlock the ring (all asics). | |
472 | */ | |
e32eb50d | 473 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 474 | { |
e32eb50d | 475 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 476 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
477 | } |
478 | ||
75923280 AD |
479 | /** |
480 | * radeon_ring_undo - reset the wptr | |
481 | * | |
482 | * @ring: radeon_ring structure holding ring information | |
483 | * | |
501f9d4c | 484 | * Reset the driver's copy of the wptr (all asics). |
75923280 | 485 | */ |
d6999bc7 | 486 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 487 | { |
e32eb50d | 488 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
489 | } |
490 | ||
75923280 AD |
491 | /** |
492 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring | |
493 | * | |
494 | * @ring: radeon_ring structure holding ring information | |
495 | * | |
496 | * Call radeon_ring_undo() then unlock the ring (all asics). | |
497 | */ | |
d6999bc7 CK |
498 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
499 | { | |
500 | radeon_ring_undo(ring); | |
501 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
502 | } |
503 | ||
75923280 AD |
504 | /** |
505 | * radeon_ring_force_activity - add some nop packets to the ring | |
506 | * | |
507 | * @rdev: radeon_device pointer | |
508 | * @ring: radeon_ring structure holding ring information | |
509 | * | |
510 | * Add some nop packets to the ring to force activity (all asics). | |
511 | * Used for lockup detection to see if the rptr is advancing. | |
512 | */ | |
7b9ef16b CK |
513 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
514 | { | |
515 | int r; | |
516 | ||
7b9ef16b CK |
517 | radeon_ring_free_size(rdev, ring); |
518 | if (ring->rptr == ring->wptr) { | |
519 | r = radeon_ring_alloc(rdev, ring, 1); | |
520 | if (!r) { | |
521 | radeon_ring_write(ring, ring->nop); | |
522 | radeon_ring_commit(rdev, ring); | |
523 | } | |
524 | } | |
7b9ef16b CK |
525 | } |
526 | ||
75923280 | 527 | /** |
501f9d4c | 528 | * radeon_ring_lockup_update - update lockup variables |
75923280 AD |
529 | * |
530 | * @ring: radeon_ring structure holding ring information | |
531 | * | |
532 | * Update the last rptr value and timestamp (all asics). | |
533 | */ | |
069211e5 CK |
534 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
535 | { | |
536 | ring->last_rptr = ring->rptr; | |
537 | ring->last_activity = jiffies; | |
538 | } | |
539 | ||
540 | /** | |
541 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
542 | * @rdev: radeon device structure | |
543 | * @ring: radeon_ring structure holding ring information | |
544 | * | |
545 | * We don't need to initialize the lockup tracking information as we will either | |
546 | * have CP rptr to a different value of jiffies wrap around which will force | |
547 | * initialization of the lockup tracking informations. | |
548 | * | |
549 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
550 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
551 | * if the elapsed time since last call is bigger than 2 second than we return | |
552 | * false and update the tracking information. Due to this the caller must call | |
553 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported | |
554 | * the fencing code should be cautious about that. | |
555 | * | |
556 | * Caller should write to the ring to force CP to do something so we don't get | |
557 | * false positive when CP is just gived nothing to do. | |
558 | * | |
559 | **/ | |
560 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
561 | { | |
562 | unsigned long cjiffies, elapsed; | |
563 | uint32_t rptr; | |
564 | ||
565 | cjiffies = jiffies; | |
566 | if (!time_after(cjiffies, ring->last_activity)) { | |
567 | /* likely a wrap around */ | |
568 | radeon_ring_lockup_update(ring); | |
569 | return false; | |
570 | } | |
571 | rptr = RREG32(ring->rptr_reg); | |
572 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
573 | if (ring->rptr != ring->last_rptr) { | |
574 | /* CP is still working no lockup */ | |
575 | radeon_ring_lockup_update(ring); | |
576 | return false; | |
577 | } | |
578 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); | |
3368ff0c | 579 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
069211e5 CK |
580 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
581 | return true; | |
582 | } | |
583 | /* give a chance to the GPU ... */ | |
584 | return false; | |
585 | } | |
586 | ||
55d7c221 CK |
587 | /** |
588 | * radeon_ring_backup - Back up the content of a ring | |
589 | * | |
590 | * @rdev: radeon_device pointer | |
591 | * @ring: the ring we want to back up | |
592 | * | |
593 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
594 | */ | |
595 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, | |
596 | uint32_t **data) | |
597 | { | |
598 | unsigned size, ptr, i; | |
55d7c221 CK |
599 | |
600 | /* just in case lock the ring */ | |
601 | mutex_lock(&rdev->ring_lock); | |
602 | *data = NULL; | |
603 | ||
89d35807 | 604 | if (ring->ring_obj == NULL) { |
55d7c221 CK |
605 | mutex_unlock(&rdev->ring_lock); |
606 | return 0; | |
607 | } | |
608 | ||
609 | /* it doesn't make sense to save anything if all fences are signaled */ | |
8b25ed34 | 610 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
55d7c221 CK |
611 | mutex_unlock(&rdev->ring_lock); |
612 | return 0; | |
613 | } | |
614 | ||
615 | /* calculate the number of dw on the ring */ | |
89d35807 AD |
616 | if (ring->rptr_save_reg) |
617 | ptr = RREG32(ring->rptr_save_reg); | |
618 | else if (rdev->wb.enabled) | |
619 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
620 | else { | |
621 | /* no way to read back the next rptr */ | |
622 | mutex_unlock(&rdev->ring_lock); | |
623 | return 0; | |
624 | } | |
625 | ||
55d7c221 CK |
626 | size = ring->wptr + (ring->ring_size / 4); |
627 | size -= ptr; | |
628 | size &= ring->ptr_mask; | |
629 | if (size == 0) { | |
630 | mutex_unlock(&rdev->ring_lock); | |
631 | return 0; | |
632 | } | |
633 | ||
634 | /* and then save the content of the ring */ | |
1e179d4e DC |
635 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
636 | if (!*data) { | |
637 | mutex_unlock(&rdev->ring_lock); | |
638 | return 0; | |
639 | } | |
55d7c221 CK |
640 | for (i = 0; i < size; ++i) { |
641 | (*data)[i] = ring->ring[ptr++]; | |
642 | ptr &= ring->ptr_mask; | |
643 | } | |
644 | ||
645 | mutex_unlock(&rdev->ring_lock); | |
646 | return size; | |
647 | } | |
648 | ||
649 | /** | |
650 | * radeon_ring_restore - append saved commands to the ring again | |
651 | * | |
652 | * @rdev: radeon_device pointer | |
653 | * @ring: ring to append commands to | |
654 | * @size: number of dwords we want to write | |
655 | * @data: saved commands | |
656 | * | |
657 | * Allocates space on the ring and restore the previously saved commands. | |
658 | */ | |
659 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
660 | unsigned size, uint32_t *data) | |
661 | { | |
662 | int i, r; | |
663 | ||
664 | if (!size || !data) | |
665 | return 0; | |
666 | ||
667 | /* restore the saved ring content */ | |
668 | r = radeon_ring_lock(rdev, ring, size); | |
669 | if (r) | |
670 | return r; | |
671 | ||
672 | for (i = 0; i < size; ++i) { | |
673 | radeon_ring_write(ring, data[i]); | |
674 | } | |
675 | ||
676 | radeon_ring_unlock_commit(rdev, ring); | |
677 | kfree(data); | |
678 | return 0; | |
679 | } | |
680 | ||
75923280 AD |
681 | /** |
682 | * radeon_ring_init - init driver ring struct. | |
683 | * | |
684 | * @rdev: radeon_device pointer | |
685 | * @ring: radeon_ring structure holding ring information | |
686 | * @ring_size: size of the ring | |
687 | * @rptr_offs: offset of the rptr writeback location in the WB buffer | |
688 | * @rptr_reg: MMIO offset of the rptr register | |
689 | * @wptr_reg: MMIO offset of the wptr register | |
690 | * @ptr_reg_shift: bit offset of the rptr/wptr values | |
691 | * @ptr_reg_mask: bit mask of the rptr/wptr values | |
692 | * @nop: nop packet for this ring | |
693 | * | |
694 | * Initialize the driver information for the selected ring (all asics). | |
695 | * Returns 0 on success, error on failure. | |
696 | */ | |
e32eb50d | 697 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
78c5560a AD |
698 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
699 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) | |
771fe6b9 JG |
700 | { |
701 | int r; | |
702 | ||
e32eb50d CK |
703 | ring->ring_size = ring_size; |
704 | ring->rptr_offs = rptr_offs; | |
705 | ring->rptr_reg = rptr_reg; | |
706 | ring->wptr_reg = wptr_reg; | |
78c5560a AD |
707 | ring->ptr_reg_shift = ptr_reg_shift; |
708 | ring->ptr_reg_mask = ptr_reg_mask; | |
709 | ring->nop = nop; | |
771fe6b9 | 710 | /* Allocate ring buffer */ |
e32eb50d CK |
711 | if (ring->ring_obj == NULL) { |
712 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
40f5cf99 AD |
713 | RADEON_GEM_DOMAIN_GTT, |
714 | NULL, &ring->ring_obj); | |
771fe6b9 | 715 | if (r) { |
4c788679 | 716 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
717 | return r; |
718 | } | |
e32eb50d | 719 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
720 | if (unlikely(r != 0)) |
721 | return r; | |
e32eb50d CK |
722 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
723 | &ring->gpu_addr); | |
771fe6b9 | 724 | if (r) { |
e32eb50d | 725 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 726 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
727 | return r; |
728 | } | |
e32eb50d CK |
729 | r = radeon_bo_kmap(ring->ring_obj, |
730 | (void **)&ring->ring); | |
731 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 732 | if (r) { |
4c788679 | 733 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
734 | return r; |
735 | } | |
736 | } | |
e32eb50d CK |
737 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
738 | ring->ring_free_dw = ring->ring_size / 4; | |
89d35807 AD |
739 | if (rdev->wb.enabled) { |
740 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); | |
741 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; | |
742 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; | |
743 | } | |
ec1a6cce CK |
744 | if (radeon_debugfs_ring_init(rdev, ring)) { |
745 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
746 | } | |
48c0ac99 | 747 | radeon_ring_lockup_update(ring); |
771fe6b9 JG |
748 | return 0; |
749 | } | |
750 | ||
75923280 AD |
751 | /** |
752 | * radeon_ring_fini - tear down the driver ring struct. | |
753 | * | |
754 | * @rdev: radeon_device pointer | |
755 | * @ring: radeon_ring structure holding ring information | |
756 | * | |
757 | * Tear down the driver information for the selected ring (all asics). | |
758 | */ | |
e32eb50d | 759 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 760 | { |
4c788679 | 761 | int r; |
ca2af923 | 762 | struct radeon_bo *ring_obj; |
4c788679 | 763 | |
d6999bc7 | 764 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 765 | ring_obj = ring->ring_obj; |
d6999bc7 | 766 | ring->ready = false; |
e32eb50d CK |
767 | ring->ring = NULL; |
768 | ring->ring_obj = NULL; | |
d6999bc7 | 769 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
770 | |
771 | if (ring_obj) { | |
772 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 773 | if (likely(r == 0)) { |
ca2af923 AD |
774 | radeon_bo_kunmap(ring_obj); |
775 | radeon_bo_unpin(ring_obj); | |
776 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 777 | } |
ca2af923 | 778 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 779 | } |
771fe6b9 JG |
780 | } |
781 | ||
771fe6b9 JG |
782 | /* |
783 | * Debugfs info | |
784 | */ | |
785 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
786 | |
787 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
788 | { | |
789 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
790 | struct drm_device *dev = node->minor->dev; | |
791 | struct radeon_device *rdev = dev->dev_private; | |
792 | int ridx = *(int*)node->info_ent->data; | |
793 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
794 | unsigned count, i, j; | |
4d009190 | 795 | u32 tmp; |
af9720f4 CK |
796 | |
797 | radeon_ring_free_size(rdev, ring); | |
798 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
4d009190 JG |
799 | tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; |
800 | seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); | |
801 | tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; | |
802 | seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); | |
45df6803 CK |
803 | if (ring->rptr_save_reg) { |
804 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, | |
805 | RREG32(ring->rptr_save_reg)); | |
806 | } | |
4d009190 JG |
807 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); |
808 | seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); | |
5f0839c1 JG |
809 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); |
810 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); | |
af9720f4 CK |
811 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
812 | seq_printf(m, "%u dwords in ring\n", count); | |
4d009190 JG |
813 | /* print 8 dw before current rptr as often it's the last executed |
814 | * packet that is the root issue | |
815 | */ | |
816 | i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; | |
817 | for (j = 0; j <= (count + 32); j++) { | |
818 | seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); | |
af9720f4 CK |
819 | i = (i + 1) & ring->ptr_mask; |
820 | } | |
821 | return 0; | |
822 | } | |
823 | ||
f2ba57b5 CK |
824 | static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
825 | static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
826 | static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
827 | static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX; | |
828 | static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; | |
829 | static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX; | |
af9720f4 CK |
830 | |
831 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
f2ba57b5 CK |
832 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index}, |
833 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index}, | |
834 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index}, | |
835 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index}, | |
836 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index}, | |
837 | {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index}, | |
af9720f4 CK |
838 | }; |
839 | ||
711a9729 CK |
840 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
841 | { | |
842 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
843 | struct drm_device *dev = node->minor->dev; | |
844 | struct radeon_device *rdev = dev->dev_private; | |
845 | ||
c507f7ef | 846 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
711a9729 CK |
847 | |
848 | return 0; | |
849 | ||
850 | } | |
851 | ||
852 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
853 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
854 | }; | |
855 | ||
771fe6b9 JG |
856 | #endif |
857 | ||
1109ca09 | 858 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
859 | { |
860 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
861 | unsigned i; |
862 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
863 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
864 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
865 | unsigned r; | |
866 | ||
867 | if (&rdev->ring[ridx] != ring) | |
868 | continue; | |
869 | ||
870 | r = radeon_debugfs_add_files(rdev, info, 1); | |
871 | if (r) | |
872 | return r; | |
873 | } | |
af9720f4 | 874 | #endif |
ec1a6cce | 875 | return 0; |
af9720f4 CK |
876 | } |
877 | ||
1109ca09 | 878 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
771fe6b9 JG |
879 | { |
880 | #if defined(CONFIG_DEBUG_FS) | |
c507f7ef | 881 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
771fe6b9 JG |
882 | #else |
883 | return 0; | |
884 | #endif | |
885 | } |