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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
c507f7ef | 27 | * Christian König |
771fe6b9 JG |
28 | */ |
29 | #include <linux/seq_file.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
771fe6b9 JG |
31 | #include "drmP.h" |
32 | #include "radeon_drm.h" | |
33 | #include "radeon_reg.h" | |
34 | #include "radeon.h" | |
35 | #include "atom.h" | |
36 | ||
c507f7ef | 37 | /* |
75923280 AD |
38 | * IB |
39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
40 | * commands are stored. You can put a pointer to the IB in the | |
41 | * command ring and the hw will fetch the commands from the IB | |
42 | * and execute them. Generally userspace acceleration drivers | |
43 | * produce command buffers which are send to the kernel and | |
44 | * put in IBs for execution by the requested ring. | |
c507f7ef JG |
45 | */ |
46 | int radeon_debugfs_sa_init(struct radeon_device *rdev); | |
771fe6b9 | 47 | |
75923280 AD |
48 | /** |
49 | * radeon_ib_get - request an IB (Indirect Buffer) | |
50 | * | |
51 | * @rdev: radeon_device pointer | |
52 | * @ring: ring index the IB is associated with | |
53 | * @ib: IB object returned | |
54 | * @size: requested IB size | |
55 | * | |
56 | * Request an IB (all asics). IBs are allocated using the | |
57 | * suballocator. | |
58 | * Returns 0 on success, error on failure. | |
59 | */ | |
69e130a6 | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
61 | struct radeon_ib *ib, struct radeon_vm *vm, |
62 | unsigned size) | |
771fe6b9 | 63 | { |
220907d9 | 64 | int i, r; |
b15ba512 | 65 | |
f2e39221 | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
c507f7ef JG |
67 | if (r) { |
68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); | |
c507f7ef | 69 | return r; |
b15ba512 | 70 | } |
c507f7ef | 71 | |
220907d9 CK |
72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
73 | if (r) { | |
74 | return r; | |
75 | } | |
76 | ||
876dc9f3 CK |
77 | ib->ring = ring; |
78 | ib->fence = NULL; | |
f2e39221 | 79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
4bf3dd92 CK |
80 | ib->vm = vm; |
81 | if (vm) { | |
82 | /* ib pool is bind at 0 in virtual address space, | |
83 | * so gpu_addr is the offset inside the pool bo | |
84 | */ | |
85 | ib->gpu_addr = ib->sa_bo->soffset; | |
86 | } else { | |
87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); | |
88 | } | |
f2e39221 | 89 | ib->is_const_ib = false; |
220907d9 CK |
90 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
91 | ib->sync_to[i] = NULL; | |
c507f7ef JG |
92 | |
93 | return 0; | |
771fe6b9 JG |
94 | } |
95 | ||
75923280 AD |
96 | /** |
97 | * radeon_ib_free - free an IB (Indirect Buffer) | |
98 | * | |
99 | * @rdev: radeon_device pointer | |
100 | * @ib: IB object to free | |
101 | * | |
102 | * Free an IB (all asics). | |
103 | */ | |
f2e39221 | 104 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
771fe6b9 | 105 | { |
220907d9 | 106 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
f2e39221 JG |
107 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
108 | radeon_fence_unref(&ib->fence); | |
771fe6b9 JG |
109 | } |
110 | ||
75923280 AD |
111 | /** |
112 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
113 | * | |
114 | * @rdev: radeon_device pointer | |
115 | * @ib: IB object to schedule | |
116 | * @const_ib: Const IB to schedule (SI only) | |
117 | * | |
118 | * Schedule an IB on the associated ring (all asics). | |
119 | * Returns 0 on success, error on failure. | |
120 | * | |
121 | * On SI, there are two parallel engines fed from the primary ring, | |
122 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
123 | * resource descriptors have moved to memory, the CE allows you to | |
124 | * prime the caches while the DE is updating register state so that | |
125 | * the resource descriptors will be already in cache when the draw is | |
126 | * processed. To accomplish this, the userspace driver submits two | |
127 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
128 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
129 | * to SI there was just a DE IB. | |
130 | */ | |
4ef72566 CK |
131 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
132 | struct radeon_ib *const_ib) | |
771fe6b9 | 133 | { |
876dc9f3 | 134 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
220907d9 CK |
135 | bool need_sync = false; |
136 | int i, r = 0; | |
771fe6b9 | 137 | |
e32eb50d | 138 | if (!ib->length_dw || !ring->ready) { |
771fe6b9 | 139 | /* TODO: Nothings in the ib we should report. */ |
c507f7ef | 140 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
771fe6b9 JG |
141 | return -EINVAL; |
142 | } | |
ecb114a1 | 143 | |
6cdf6585 | 144 | /* 64 dwords should be enough for fence too */ |
220907d9 | 145 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
771fe6b9 | 146 | if (r) { |
c507f7ef | 147 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
771fe6b9 JG |
148 | return r; |
149 | } | |
220907d9 CK |
150 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
151 | struct radeon_fence *fence = ib->sync_to[i]; | |
152 | if (radeon_fence_need_sync(fence, ib->ring)) { | |
153 | need_sync = true; | |
154 | radeon_semaphore_sync_rings(rdev, ib->semaphore, | |
155 | fence->ring, ib->ring); | |
156 | radeon_fence_note_sync(fence, ib->ring); | |
157 | } | |
158 | } | |
159 | /* immediately free semaphore when we don't need to sync */ | |
160 | if (!need_sync) { | |
161 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); | |
162 | } | |
9b40e5d8 CK |
163 | /* if we can't remember our last VM flush then flush now! */ |
164 | if (ib->vm && !ib->vm->last_flush) { | |
165 | radeon_ring_vm_flush(rdev, ib->ring, ib); | |
166 | } | |
4ef72566 CK |
167 | if (const_ib) { |
168 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); | |
169 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); | |
170 | } | |
876dc9f3 CK |
171 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
172 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); | |
173 | if (r) { | |
174 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); | |
175 | radeon_ring_unlock_undo(rdev, ring); | |
176 | return r; | |
177 | } | |
4ef72566 CK |
178 | if (const_ib) { |
179 | const_ib->fence = radeon_fence_ref(ib->fence); | |
180 | } | |
9b40e5d8 CK |
181 | /* we just flushed the VM, remember that */ |
182 | if (ib->vm && !ib->vm->last_flush) { | |
183 | ib->vm->last_flush = radeon_fence_ref(ib->fence); | |
184 | } | |
e32eb50d | 185 | radeon_ring_unlock_commit(rdev, ring); |
771fe6b9 JG |
186 | return 0; |
187 | } | |
188 | ||
75923280 AD |
189 | /** |
190 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool | |
191 | * | |
192 | * @rdev: radeon_device pointer | |
193 | * | |
194 | * Initialize the suballocator to manage a pool of memory | |
195 | * for use as IBs (all asics). | |
196 | * Returns 0 on success, error on failure. | |
197 | */ | |
771fe6b9 JG |
198 | int radeon_ib_pool_init(struct radeon_device *rdev) |
199 | { | |
c507f7ef | 200 | int r; |
771fe6b9 | 201 | |
c507f7ef | 202 | if (rdev->ib_pool_ready) { |
d54fbd49 JG |
203 | return 0; |
204 | } | |
c507f7ef | 205 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
c3b7fe8b CK |
206 | RADEON_IB_POOL_SIZE*64*1024, |
207 | RADEON_GEM_DOMAIN_GTT); | |
208 | if (r) { | |
c3b7fe8b CK |
209 | return r; |
210 | } | |
2898c348 CK |
211 | |
212 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); | |
213 | if (r) { | |
214 | return r; | |
215 | } | |
216 | ||
c507f7ef JG |
217 | rdev->ib_pool_ready = true; |
218 | if (radeon_debugfs_sa_init(rdev)) { | |
219 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); | |
771fe6b9 | 220 | } |
b15ba512 | 221 | return 0; |
771fe6b9 JG |
222 | } |
223 | ||
75923280 AD |
224 | /** |
225 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
226 | * | |
227 | * @rdev: radeon_device pointer | |
228 | * | |
229 | * Tear down the suballocator managing the pool of memory | |
230 | * for use as IBs (all asics). | |
231 | */ | |
771fe6b9 JG |
232 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
233 | { | |
c507f7ef | 234 | if (rdev->ib_pool_ready) { |
2898c348 | 235 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
c507f7ef JG |
236 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
237 | rdev->ib_pool_ready = false; | |
771fe6b9 | 238 | } |
771fe6b9 JG |
239 | } |
240 | ||
75923280 AD |
241 | /** |
242 | * radeon_ib_ring_tests - test IBs on the rings | |
243 | * | |
244 | * @rdev: radeon_device pointer | |
245 | * | |
246 | * Test an IB (Indirect Buffer) on each ring. | |
247 | * If the test fails, disable the ring. | |
248 | * Returns 0 on success, error if the primary GFX ring | |
249 | * IB test fails. | |
250 | */ | |
7bd560e8 CK |
251 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
252 | { | |
253 | unsigned i; | |
254 | int r; | |
255 | ||
256 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
257 | struct radeon_ring *ring = &rdev->ring[i]; | |
258 | ||
259 | if (!ring->ready) | |
260 | continue; | |
261 | ||
262 | r = radeon_ib_test(rdev, i, ring); | |
263 | if (r) { | |
264 | ring->ready = false; | |
265 | ||
266 | if (i == RADEON_RING_TYPE_GFX_INDEX) { | |
267 | /* oh, oh, that's really bad */ | |
268 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); | |
269 | rdev->accel_working = false; | |
270 | return r; | |
271 | ||
272 | } else { | |
273 | /* still not good, but we can live with it */ | |
274 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); | |
275 | } | |
276 | } | |
277 | } | |
278 | return 0; | |
279 | } | |
280 | ||
771fe6b9 | 281 | /* |
75923280 AD |
282 | * Rings |
283 | * Most engines on the GPU are fed via ring buffers. Ring | |
284 | * buffers are areas of GPU accessible memory that the host | |
285 | * writes commands into and the GPU reads commands out of. | |
286 | * There is a rptr (read pointer) that determines where the | |
287 | * GPU is currently reading, and a wptr (write pointer) | |
288 | * which determines where the host has written. When the | |
289 | * pointers are equal, the ring is idle. When the host | |
290 | * writes commands to the ring buffer, it increments the | |
291 | * wptr. The GPU then starts fetching commands and executes | |
292 | * them until the pointers are equal again. | |
771fe6b9 | 293 | */ |
c507f7ef JG |
294 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
295 | ||
75923280 AD |
296 | /** |
297 | * radeon_ring_write - write a value to the ring | |
298 | * | |
299 | * @ring: radeon_ring structure holding ring information | |
300 | * @v: dword (dw) value to write | |
301 | * | |
302 | * Write a value to the requested ring buffer (all asics). | |
303 | */ | |
c507f7ef JG |
304 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
305 | { | |
306 | #if DRM_DEBUG_CODE | |
307 | if (ring->count_dw <= 0) { | |
308 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
309 | } | |
310 | #endif | |
311 | ring->ring[ring->wptr++] = v; | |
312 | ring->wptr &= ring->ptr_mask; | |
313 | ring->count_dw--; | |
314 | ring->ring_free_dw--; | |
315 | } | |
316 | ||
75923280 AD |
317 | /** |
318 | * radeon_ring_supports_scratch_reg - check if the ring supports | |
319 | * writing to scratch registers | |
320 | * | |
321 | * @rdev: radeon_device pointer | |
322 | * @ring: radeon_ring structure holding ring information | |
323 | * | |
324 | * Check if a specific ring supports writing to scratch registers (all asics). | |
325 | * Returns true if the ring supports writing to scratch regs, false if not. | |
326 | */ | |
89d35807 AD |
327 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
328 | struct radeon_ring *ring) | |
329 | { | |
330 | switch (ring->idx) { | |
331 | case RADEON_RING_TYPE_GFX_INDEX: | |
332 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
333 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
334 | return true; | |
335 | default: | |
336 | return false; | |
337 | } | |
338 | } | |
339 | ||
75923280 AD |
340 | /** |
341 | * radeon_ring_free_size - update the free size | |
342 | * | |
343 | * @rdev: radeon_device pointer | |
344 | * @ring: radeon_ring structure holding ring information | |
345 | * | |
346 | * Update the free dw slots in the ring buffer (all asics). | |
347 | */ | |
e32eb50d | 348 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 349 | { |
78c5560a AD |
350 | u32 rptr; |
351 | ||
724c80e1 | 352 | if (rdev->wb.enabled) |
78c5560a | 353 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
5596a9db | 354 | else |
78c5560a AD |
355 | rptr = RREG32(ring->rptr_reg); |
356 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
771fe6b9 | 357 | /* This works because ring_size is a power of 2 */ |
e32eb50d CK |
358 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
359 | ring->ring_free_dw -= ring->wptr; | |
360 | ring->ring_free_dw &= ring->ptr_mask; | |
361 | if (!ring->ring_free_dw) { | |
362 | ring->ring_free_dw = ring->ring_size / 4; | |
771fe6b9 JG |
363 | } |
364 | } | |
365 | ||
75923280 AD |
366 | /** |
367 | * radeon_ring_alloc - allocate space on the ring buffer | |
368 | * | |
369 | * @rdev: radeon_device pointer | |
370 | * @ring: radeon_ring structure holding ring information | |
371 | * @ndw: number of dwords to allocate in the ring buffer | |
372 | * | |
373 | * Allocate @ndw dwords in the ring buffer (all asics). | |
374 | * Returns 0 on success, error on failure. | |
375 | */ | |
e32eb50d | 376 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
771fe6b9 JG |
377 | { |
378 | int r; | |
379 | ||
380 | /* Align requested size with padding so unlock_commit can | |
381 | * pad safely */ | |
e32eb50d CK |
382 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
383 | while (ndw > (ring->ring_free_dw - 1)) { | |
384 | radeon_ring_free_size(rdev, ring); | |
385 | if (ndw < ring->ring_free_dw) { | |
771fe6b9 JG |
386 | break; |
387 | } | |
8b25ed34 | 388 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
91700f3c | 389 | if (r) |
771fe6b9 | 390 | return r; |
771fe6b9 | 391 | } |
e32eb50d CK |
392 | ring->count_dw = ndw; |
393 | ring->wptr_old = ring->wptr; | |
771fe6b9 JG |
394 | return 0; |
395 | } | |
396 | ||
75923280 AD |
397 | /** |
398 | * radeon_ring_lock - lock the ring and allocate space on it | |
399 | * | |
400 | * @rdev: radeon_device pointer | |
401 | * @ring: radeon_ring structure holding ring information | |
402 | * @ndw: number of dwords to allocate in the ring buffer | |
403 | * | |
404 | * Lock the ring and allocate @ndw dwords in the ring buffer | |
405 | * (all asics). | |
406 | * Returns 0 on success, error on failure. | |
407 | */ | |
e32eb50d | 408 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
91700f3c MG |
409 | { |
410 | int r; | |
411 | ||
d6999bc7 | 412 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 413 | r = radeon_ring_alloc(rdev, ring, ndw); |
91700f3c | 414 | if (r) { |
d6999bc7 | 415 | mutex_unlock(&rdev->ring_lock); |
91700f3c MG |
416 | return r; |
417 | } | |
418 | return 0; | |
419 | } | |
420 | ||
75923280 AD |
421 | /** |
422 | * radeon_ring_commit - tell the GPU to execute the new | |
423 | * commands on the ring buffer | |
424 | * | |
425 | * @rdev: radeon_device pointer | |
426 | * @ring: radeon_ring structure holding ring information | |
427 | * | |
428 | * Update the wptr (write pointer) to tell the GPU to | |
429 | * execute new commands on the ring buffer (all asics). | |
430 | */ | |
e32eb50d | 431 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 432 | { |
771fe6b9 | 433 | /* We pad to match fetch size */ |
07a71330 | 434 | while (ring->wptr & ring->align_mask) { |
78c5560a | 435 | radeon_ring_write(ring, ring->nop); |
771fe6b9 JG |
436 | } |
437 | DRM_MEMORYBARRIER(); | |
78c5560a | 438 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
e32eb50d | 439 | (void)RREG32(ring->wptr_reg); |
91700f3c MG |
440 | } |
441 | ||
75923280 AD |
442 | /** |
443 | * radeon_ring_unlock_commit - tell the GPU to execute the new | |
444 | * commands on the ring buffer and unlock it | |
445 | * | |
446 | * @rdev: radeon_device pointer | |
447 | * @ring: radeon_ring structure holding ring information | |
448 | * | |
449 | * Call radeon_ring_commit() then unlock the ring (all asics). | |
450 | */ | |
e32eb50d | 451 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
91700f3c | 452 | { |
e32eb50d | 453 | radeon_ring_commit(rdev, ring); |
d6999bc7 | 454 | mutex_unlock(&rdev->ring_lock); |
771fe6b9 JG |
455 | } |
456 | ||
75923280 AD |
457 | /** |
458 | * radeon_ring_undo - reset the wptr | |
459 | * | |
460 | * @ring: radeon_ring structure holding ring information | |
461 | * | |
462 | * Reset the driver's copy of the wtpr (all asics). | |
463 | */ | |
d6999bc7 | 464 | void radeon_ring_undo(struct radeon_ring *ring) |
771fe6b9 | 465 | { |
e32eb50d | 466 | ring->wptr = ring->wptr_old; |
d6999bc7 CK |
467 | } |
468 | ||
75923280 AD |
469 | /** |
470 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring | |
471 | * | |
472 | * @ring: radeon_ring structure holding ring information | |
473 | * | |
474 | * Call radeon_ring_undo() then unlock the ring (all asics). | |
475 | */ | |
d6999bc7 CK |
476 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
477 | { | |
478 | radeon_ring_undo(ring); | |
479 | mutex_unlock(&rdev->ring_lock); | |
771fe6b9 JG |
480 | } |
481 | ||
75923280 AD |
482 | /** |
483 | * radeon_ring_force_activity - add some nop packets to the ring | |
484 | * | |
485 | * @rdev: radeon_device pointer | |
486 | * @ring: radeon_ring structure holding ring information | |
487 | * | |
488 | * Add some nop packets to the ring to force activity (all asics). | |
489 | * Used for lockup detection to see if the rptr is advancing. | |
490 | */ | |
7b9ef16b CK |
491 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
492 | { | |
493 | int r; | |
494 | ||
7b9ef16b CK |
495 | radeon_ring_free_size(rdev, ring); |
496 | if (ring->rptr == ring->wptr) { | |
497 | r = radeon_ring_alloc(rdev, ring, 1); | |
498 | if (!r) { | |
499 | radeon_ring_write(ring, ring->nop); | |
500 | radeon_ring_commit(rdev, ring); | |
501 | } | |
502 | } | |
7b9ef16b CK |
503 | } |
504 | ||
75923280 AD |
505 | /** |
506 | * radeon_ring_force_activity - update lockup variables | |
507 | * | |
508 | * @ring: radeon_ring structure holding ring information | |
509 | * | |
510 | * Update the last rptr value and timestamp (all asics). | |
511 | */ | |
069211e5 CK |
512 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
513 | { | |
514 | ring->last_rptr = ring->rptr; | |
515 | ring->last_activity = jiffies; | |
516 | } | |
517 | ||
518 | /** | |
519 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information | |
520 | * @rdev: radeon device structure | |
521 | * @ring: radeon_ring structure holding ring information | |
522 | * | |
523 | * We don't need to initialize the lockup tracking information as we will either | |
524 | * have CP rptr to a different value of jiffies wrap around which will force | |
525 | * initialization of the lockup tracking informations. | |
526 | * | |
527 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
528 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
529 | * if the elapsed time since last call is bigger than 2 second than we return | |
530 | * false and update the tracking information. Due to this the caller must call | |
531 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported | |
532 | * the fencing code should be cautious about that. | |
533 | * | |
534 | * Caller should write to the ring to force CP to do something so we don't get | |
535 | * false positive when CP is just gived nothing to do. | |
536 | * | |
537 | **/ | |
538 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
539 | { | |
540 | unsigned long cjiffies, elapsed; | |
541 | uint32_t rptr; | |
542 | ||
543 | cjiffies = jiffies; | |
544 | if (!time_after(cjiffies, ring->last_activity)) { | |
545 | /* likely a wrap around */ | |
546 | radeon_ring_lockup_update(ring); | |
547 | return false; | |
548 | } | |
549 | rptr = RREG32(ring->rptr_reg); | |
550 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; | |
551 | if (ring->rptr != ring->last_rptr) { | |
552 | /* CP is still working no lockup */ | |
553 | radeon_ring_lockup_update(ring); | |
554 | return false; | |
555 | } | |
556 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); | |
3368ff0c | 557 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
069211e5 CK |
558 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
559 | return true; | |
560 | } | |
561 | /* give a chance to the GPU ... */ | |
562 | return false; | |
563 | } | |
564 | ||
55d7c221 CK |
565 | /** |
566 | * radeon_ring_backup - Back up the content of a ring | |
567 | * | |
568 | * @rdev: radeon_device pointer | |
569 | * @ring: the ring we want to back up | |
570 | * | |
571 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
572 | */ | |
573 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, | |
574 | uint32_t **data) | |
575 | { | |
576 | unsigned size, ptr, i; | |
55d7c221 CK |
577 | |
578 | /* just in case lock the ring */ | |
579 | mutex_lock(&rdev->ring_lock); | |
580 | *data = NULL; | |
581 | ||
89d35807 | 582 | if (ring->ring_obj == NULL) { |
55d7c221 CK |
583 | mutex_unlock(&rdev->ring_lock); |
584 | return 0; | |
585 | } | |
586 | ||
587 | /* it doesn't make sense to save anything if all fences are signaled */ | |
8b25ed34 | 588 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
55d7c221 CK |
589 | mutex_unlock(&rdev->ring_lock); |
590 | return 0; | |
591 | } | |
592 | ||
593 | /* calculate the number of dw on the ring */ | |
89d35807 AD |
594 | if (ring->rptr_save_reg) |
595 | ptr = RREG32(ring->rptr_save_reg); | |
596 | else if (rdev->wb.enabled) | |
597 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
598 | else { | |
599 | /* no way to read back the next rptr */ | |
600 | mutex_unlock(&rdev->ring_lock); | |
601 | return 0; | |
602 | } | |
603 | ||
55d7c221 CK |
604 | size = ring->wptr + (ring->ring_size / 4); |
605 | size -= ptr; | |
606 | size &= ring->ptr_mask; | |
607 | if (size == 0) { | |
608 | mutex_unlock(&rdev->ring_lock); | |
609 | return 0; | |
610 | } | |
611 | ||
612 | /* and then save the content of the ring */ | |
1e179d4e DC |
613 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
614 | if (!*data) { | |
615 | mutex_unlock(&rdev->ring_lock); | |
616 | return 0; | |
617 | } | |
55d7c221 CK |
618 | for (i = 0; i < size; ++i) { |
619 | (*data)[i] = ring->ring[ptr++]; | |
620 | ptr &= ring->ptr_mask; | |
621 | } | |
622 | ||
623 | mutex_unlock(&rdev->ring_lock); | |
624 | return size; | |
625 | } | |
626 | ||
627 | /** | |
628 | * radeon_ring_restore - append saved commands to the ring again | |
629 | * | |
630 | * @rdev: radeon_device pointer | |
631 | * @ring: ring to append commands to | |
632 | * @size: number of dwords we want to write | |
633 | * @data: saved commands | |
634 | * | |
635 | * Allocates space on the ring and restore the previously saved commands. | |
636 | */ | |
637 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
638 | unsigned size, uint32_t *data) | |
639 | { | |
640 | int i, r; | |
641 | ||
642 | if (!size || !data) | |
643 | return 0; | |
644 | ||
645 | /* restore the saved ring content */ | |
646 | r = radeon_ring_lock(rdev, ring, size); | |
647 | if (r) | |
648 | return r; | |
649 | ||
650 | for (i = 0; i < size; ++i) { | |
651 | radeon_ring_write(ring, data[i]); | |
652 | } | |
653 | ||
654 | radeon_ring_unlock_commit(rdev, ring); | |
655 | kfree(data); | |
656 | return 0; | |
657 | } | |
658 | ||
75923280 AD |
659 | /** |
660 | * radeon_ring_init - init driver ring struct. | |
661 | * | |
662 | * @rdev: radeon_device pointer | |
663 | * @ring: radeon_ring structure holding ring information | |
664 | * @ring_size: size of the ring | |
665 | * @rptr_offs: offset of the rptr writeback location in the WB buffer | |
666 | * @rptr_reg: MMIO offset of the rptr register | |
667 | * @wptr_reg: MMIO offset of the wptr register | |
668 | * @ptr_reg_shift: bit offset of the rptr/wptr values | |
669 | * @ptr_reg_mask: bit mask of the rptr/wptr values | |
670 | * @nop: nop packet for this ring | |
671 | * | |
672 | * Initialize the driver information for the selected ring (all asics). | |
673 | * Returns 0 on success, error on failure. | |
674 | */ | |
e32eb50d | 675 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
78c5560a AD |
676 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
677 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) | |
771fe6b9 JG |
678 | { |
679 | int r; | |
680 | ||
e32eb50d CK |
681 | ring->ring_size = ring_size; |
682 | ring->rptr_offs = rptr_offs; | |
683 | ring->rptr_reg = rptr_reg; | |
684 | ring->wptr_reg = wptr_reg; | |
78c5560a AD |
685 | ring->ptr_reg_shift = ptr_reg_shift; |
686 | ring->ptr_reg_mask = ptr_reg_mask; | |
687 | ring->nop = nop; | |
771fe6b9 | 688 | /* Allocate ring buffer */ |
e32eb50d CK |
689 | if (ring->ring_obj == NULL) { |
690 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, | |
40f5cf99 AD |
691 | RADEON_GEM_DOMAIN_GTT, |
692 | NULL, &ring->ring_obj); | |
771fe6b9 | 693 | if (r) { |
4c788679 | 694 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
771fe6b9 JG |
695 | return r; |
696 | } | |
e32eb50d | 697 | r = radeon_bo_reserve(ring->ring_obj, false); |
4c788679 JG |
698 | if (unlikely(r != 0)) |
699 | return r; | |
e32eb50d CK |
700 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
701 | &ring->gpu_addr); | |
771fe6b9 | 702 | if (r) { |
e32eb50d | 703 | radeon_bo_unreserve(ring->ring_obj); |
4c788679 | 704 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
771fe6b9 JG |
705 | return r; |
706 | } | |
e32eb50d CK |
707 | r = radeon_bo_kmap(ring->ring_obj, |
708 | (void **)&ring->ring); | |
709 | radeon_bo_unreserve(ring->ring_obj); | |
771fe6b9 | 710 | if (r) { |
4c788679 | 711 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
771fe6b9 JG |
712 | return r; |
713 | } | |
714 | } | |
e32eb50d CK |
715 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
716 | ring->ring_free_dw = ring->ring_size / 4; | |
89d35807 AD |
717 | if (rdev->wb.enabled) { |
718 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); | |
719 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; | |
720 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; | |
721 | } | |
ec1a6cce CK |
722 | if (radeon_debugfs_ring_init(rdev, ring)) { |
723 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
724 | } | |
48c0ac99 | 725 | radeon_ring_lockup_update(ring); |
771fe6b9 JG |
726 | return 0; |
727 | } | |
728 | ||
75923280 AD |
729 | /** |
730 | * radeon_ring_fini - tear down the driver ring struct. | |
731 | * | |
732 | * @rdev: radeon_device pointer | |
733 | * @ring: radeon_ring structure holding ring information | |
734 | * | |
735 | * Tear down the driver information for the selected ring (all asics). | |
736 | */ | |
e32eb50d | 737 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 | 738 | { |
4c788679 | 739 | int r; |
ca2af923 | 740 | struct radeon_bo *ring_obj; |
4c788679 | 741 | |
d6999bc7 | 742 | mutex_lock(&rdev->ring_lock); |
e32eb50d | 743 | ring_obj = ring->ring_obj; |
d6999bc7 | 744 | ring->ready = false; |
e32eb50d CK |
745 | ring->ring = NULL; |
746 | ring->ring_obj = NULL; | |
d6999bc7 | 747 | mutex_unlock(&rdev->ring_lock); |
ca2af923 AD |
748 | |
749 | if (ring_obj) { | |
750 | r = radeon_bo_reserve(ring_obj, false); | |
4c788679 | 751 | if (likely(r == 0)) { |
ca2af923 AD |
752 | radeon_bo_kunmap(ring_obj); |
753 | radeon_bo_unpin(ring_obj); | |
754 | radeon_bo_unreserve(ring_obj); | |
4c788679 | 755 | } |
ca2af923 | 756 | radeon_bo_unref(&ring_obj); |
771fe6b9 | 757 | } |
771fe6b9 JG |
758 | } |
759 | ||
771fe6b9 JG |
760 | /* |
761 | * Debugfs info | |
762 | */ | |
763 | #if defined(CONFIG_DEBUG_FS) | |
af9720f4 CK |
764 | |
765 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) | |
766 | { | |
767 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
768 | struct drm_device *dev = node->minor->dev; | |
769 | struct radeon_device *rdev = dev->dev_private; | |
770 | int ridx = *(int*)node->info_ent->data; | |
771 | struct radeon_ring *ring = &rdev->ring[ridx]; | |
772 | unsigned count, i, j; | |
773 | ||
774 | radeon_ring_free_size(rdev, ring); | |
775 | count = (ring->ring_size / 4) - ring->ring_free_dw; | |
776 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); | |
777 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); | |
45df6803 CK |
778 | if (ring->rptr_save_reg) { |
779 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, | |
780 | RREG32(ring->rptr_save_reg)); | |
781 | } | |
af9720f4 CK |
782 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); |
783 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); | |
784 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); | |
785 | seq_printf(m, "%u dwords in ring\n", count); | |
786 | i = ring->rptr; | |
787 | for (j = 0; j <= count; j++) { | |
788 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); | |
789 | i = (i + 1) & ring->ptr_mask; | |
790 | } | |
791 | return 0; | |
792 | } | |
793 | ||
794 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; | |
795 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; | |
796 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; | |
797 | ||
798 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { | |
799 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, | |
800 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, | |
801 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, | |
802 | }; | |
803 | ||
711a9729 CK |
804 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
805 | { | |
806 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
807 | struct drm_device *dev = node->minor->dev; | |
808 | struct radeon_device *rdev = dev->dev_private; | |
809 | ||
c507f7ef | 810 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
711a9729 CK |
811 | |
812 | return 0; | |
813 | ||
814 | } | |
815 | ||
816 | static struct drm_info_list radeon_debugfs_sa_list[] = { | |
817 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, | |
818 | }; | |
819 | ||
771fe6b9 JG |
820 | #endif |
821 | ||
ec1a6cce | 822 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
af9720f4 CK |
823 | { |
824 | #if defined(CONFIG_DEBUG_FS) | |
ec1a6cce CK |
825 | unsigned i; |
826 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { | |
827 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; | |
828 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; | |
829 | unsigned r; | |
830 | ||
831 | if (&rdev->ring[ridx] != ring) | |
832 | continue; | |
833 | ||
834 | r = radeon_debugfs_add_files(rdev, info, 1); | |
835 | if (r) | |
836 | return r; | |
837 | } | |
af9720f4 | 838 | #endif |
ec1a6cce | 839 | return 0; |
af9720f4 CK |
840 | } |
841 | ||
c507f7ef | 842 | int radeon_debugfs_sa_init(struct radeon_device *rdev) |
771fe6b9 JG |
843 | { |
844 | #if defined(CONFIG_DEBUG_FS) | |
c507f7ef | 845 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
771fe6b9 JG |
846 | #else |
847 | return 0; | |
848 | #endif | |
849 | } |