Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <ttm/ttm_bo_api.h> | |
33 | #include <ttm/ttm_bo_driver.h> | |
34 | #include <ttm/ttm_placement.h> | |
35 | #include <ttm/ttm_module.h> | |
8d7cddcd | 36 | #include <ttm/ttm_page_alloc.h> |
771fe6b9 JG |
37 | #include <drm/drmP.h> |
38 | #include <drm/radeon_drm.h> | |
fa8a1238 | 39 | #include <linux/seq_file.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
4cfe7629 | 41 | #include <linux/swiotlb.h> |
2014b569 | 42 | #include <linux/debugfs.h> |
771fe6b9 JG |
43 | #include "radeon_reg.h" |
44 | #include "radeon.h" | |
45 | ||
46 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
47 | ||
fa8a1238 | 48 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
2014b569 | 49 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
fa8a1238 | 50 | |
771fe6b9 JG |
51 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
52 | { | |
53 | struct radeon_mman *mman; | |
54 | struct radeon_device *rdev; | |
55 | ||
56 | mman = container_of(bdev, struct radeon_mman, bdev); | |
57 | rdev = container_of(mman, struct radeon_device, mman); | |
58 | return rdev; | |
59 | } | |
60 | ||
61 | ||
62 | /* | |
63 | * Global memory. | |
64 | */ | |
ba4420c2 | 65 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
771fe6b9 JG |
66 | { |
67 | return ttm_mem_global_init(ref->object); | |
68 | } | |
69 | ||
ba4420c2 | 70 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
771fe6b9 JG |
71 | { |
72 | ttm_mem_global_release(ref->object); | |
73 | } | |
74 | ||
75 | static int radeon_ttm_global_init(struct radeon_device *rdev) | |
76 | { | |
ba4420c2 | 77 | struct drm_global_reference *global_ref; |
771fe6b9 JG |
78 | int r; |
79 | ||
80 | rdev->mman.mem_global_referenced = false; | |
81 | global_ref = &rdev->mman.mem_global_ref; | |
ba4420c2 | 82 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
771fe6b9 JG |
83 | global_ref->size = sizeof(struct ttm_mem_global); |
84 | global_ref->init = &radeon_ttm_mem_global_init; | |
85 | global_ref->release = &radeon_ttm_mem_global_release; | |
ba4420c2 | 86 | r = drm_global_item_ref(global_ref); |
771fe6b9 | 87 | if (r != 0) { |
a987fcaa TH |
88 | DRM_ERROR("Failed setting up TTM memory accounting " |
89 | "subsystem.\n"); | |
771fe6b9 JG |
90 | return r; |
91 | } | |
a987fcaa TH |
92 | |
93 | rdev->mman.bo_global_ref.mem_glob = | |
94 | rdev->mman.mem_global_ref.object; | |
95 | global_ref = &rdev->mman.bo_global_ref.ref; | |
ba4420c2 | 96 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
7f5f4db2 | 97 | global_ref->size = sizeof(struct ttm_bo_global); |
a987fcaa TH |
98 | global_ref->init = &ttm_bo_global_init; |
99 | global_ref->release = &ttm_bo_global_release; | |
ba4420c2 | 100 | r = drm_global_item_ref(global_ref); |
a987fcaa TH |
101 | if (r != 0) { |
102 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | |
ba4420c2 | 103 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
a987fcaa TH |
104 | return r; |
105 | } | |
106 | ||
771fe6b9 JG |
107 | rdev->mman.mem_global_referenced = true; |
108 | return 0; | |
109 | } | |
110 | ||
111 | static void radeon_ttm_global_fini(struct radeon_device *rdev) | |
112 | { | |
113 | if (rdev->mman.mem_global_referenced) { | |
ba4420c2 DA |
114 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
115 | drm_global_item_unref(&rdev->mman.mem_global_ref); | |
771fe6b9 JG |
116 | rdev->mman.mem_global_referenced = false; |
117 | } | |
118 | } | |
119 | ||
771fe6b9 JG |
120 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
121 | { | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
126 | struct ttm_mem_type_manager *man) | |
127 | { | |
128 | struct radeon_device *rdev; | |
129 | ||
130 | rdev = radeon_get_rdev(bdev); | |
131 | ||
132 | switch (type) { | |
133 | case TTM_PL_SYSTEM: | |
134 | /* System memory */ | |
135 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
136 | man->available_caching = TTM_PL_MASK_CACHING; | |
137 | man->default_caching = TTM_PL_FLAG_CACHED; | |
138 | break; | |
139 | case TTM_PL_TT: | |
d961db75 | 140 | man->func = &ttm_bo_manager_func; |
d594e46a | 141 | man->gpu_offset = rdev->mc.gtt_start; |
771fe6b9 JG |
142 | man->available_caching = TTM_PL_MASK_CACHING; |
143 | man->default_caching = TTM_PL_FLAG_CACHED; | |
55c93278 | 144 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
771fe6b9 JG |
145 | #if __OS_HAS_AGP |
146 | if (rdev->flags & RADEON_IS_AGP) { | |
d9906753 | 147 | if (!rdev->ddev->agp) { |
771fe6b9 JG |
148 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
149 | (unsigned)type); | |
150 | return -EINVAL; | |
151 | } | |
55c93278 | 152 | if (!rdev->ddev->agp->cant_use_aperture) |
0a2d50e3 | 153 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
771fe6b9 JG |
154 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
155 | TTM_PL_FLAG_WC; | |
156 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 | 157 | } |
0c321c79 | 158 | #endif |
771fe6b9 JG |
159 | break; |
160 | case TTM_PL_VRAM: | |
161 | /* "On-card" video ram */ | |
d961db75 | 162 | man->func = &ttm_bo_manager_func; |
d594e46a | 163 | man->gpu_offset = rdev->mc.vram_start; |
771fe6b9 | 164 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
771fe6b9 JG |
165 | TTM_MEMTYPE_FLAG_MAPPABLE; |
166 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
167 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 JG |
168 | break; |
169 | default: | |
170 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
171 | return -EINVAL; | |
172 | } | |
173 | return 0; | |
174 | } | |
175 | ||
312ea8da JG |
176 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
177 | struct ttm_placement *placement) | |
771fe6b9 | 178 | { |
d03d8589 JG |
179 | struct radeon_bo *rbo; |
180 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
181 | ||
182 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
183 | placement->fpfn = 0; | |
184 | placement->lpfn = 0; | |
185 | placement->placement = &placements; | |
186 | placement->busy_placement = &placements; | |
187 | placement->num_placement = 1; | |
188 | placement->num_busy_placement = 1; | |
189 | return; | |
190 | } | |
191 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 192 | switch (bo->mem.mem_type) { |
312ea8da | 193 | case TTM_PL_VRAM: |
e32eb50d | 194 | if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) |
9270eb1b DA |
195 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
196 | else | |
197 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
312ea8da JG |
198 | break; |
199 | case TTM_PL_TT: | |
771fe6b9 | 200 | default: |
312ea8da | 201 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 202 | } |
eaa5fd1a | 203 | *placement = rbo->placement; |
771fe6b9 JG |
204 | } |
205 | ||
206 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
207 | { | |
acb46527 DH |
208 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
209 | ||
210 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); | |
771fe6b9 JG |
211 | } |
212 | ||
213 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
214 | struct ttm_mem_reg *new_mem) | |
215 | { | |
216 | struct ttm_mem_reg *old_mem = &bo->mem; | |
217 | ||
218 | BUG_ON(old_mem->mm_node != NULL); | |
219 | *old_mem = *new_mem; | |
220 | new_mem->mm_node = NULL; | |
221 | } | |
222 | ||
223 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
97a875cb | 224 | bool evict, bool no_wait_gpu, |
9d87fa21 JG |
225 | struct ttm_mem_reg *new_mem, |
226 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
227 | { |
228 | struct radeon_device *rdev; | |
229 | uint64_t old_start, new_start; | |
876dc9f3 | 230 | struct radeon_fence *fence; |
876dc9f3 | 231 | int r, ridx; |
771fe6b9 JG |
232 | |
233 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 234 | ridx = radeon_copy_ring_index(rdev); |
d961db75 BS |
235 | old_start = old_mem->start << PAGE_SHIFT; |
236 | new_start = new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
237 | |
238 | switch (old_mem->mem_type) { | |
239 | case TTM_PL_VRAM: | |
d594e46a | 240 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
241 | break; |
242 | case TTM_PL_TT: | |
d594e46a | 243 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
244 | break; |
245 | default: | |
246 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
247 | return -EINVAL; | |
248 | } | |
249 | switch (new_mem->mem_type) { | |
250 | case TTM_PL_VRAM: | |
d594e46a | 251 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
252 | break; |
253 | case TTM_PL_TT: | |
d594e46a | 254 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
255 | break; |
256 | default: | |
257 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
258 | return -EINVAL; | |
259 | } | |
876dc9f3 | 260 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 261 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
262 | return -EINVAL; |
263 | } | |
003cefe0 AD |
264 | |
265 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
266 | ||
3000bf39 | 267 | /* sync other rings */ |
876dc9f3 | 268 | fence = bo->sync_obj; |
003cefe0 AD |
269 | r = radeon_copy(rdev, old_start, new_start, |
270 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ | |
876dc9f3 | 271 | &fence); |
771fe6b9 | 272 | /* FIXME: handle copy error */ |
b03640b1 | 273 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, |
97a875cb | 274 | evict, no_wait_gpu, new_mem); |
771fe6b9 JG |
275 | radeon_fence_unref(&fence); |
276 | return r; | |
277 | } | |
278 | ||
279 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 | 280 | bool evict, bool interruptible, |
97a875cb | 281 | bool no_wait_gpu, |
771fe6b9 JG |
282 | struct ttm_mem_reg *new_mem) |
283 | { | |
284 | struct radeon_device *rdev; | |
285 | struct ttm_mem_reg *old_mem = &bo->mem; | |
286 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
287 | u32 placements; |
288 | struct ttm_placement placement; | |
771fe6b9 JG |
289 | int r; |
290 | ||
291 | rdev = radeon_get_rdev(bo->bdev); | |
292 | tmp_mem = *new_mem; | |
293 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
294 | placement.fpfn = 0; |
295 | placement.lpfn = 0; | |
296 | placement.num_placement = 1; | |
297 | placement.placement = &placements; | |
298 | placement.num_busy_placement = 1; | |
299 | placement.busy_placement = &placements; | |
300 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
301 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
97a875cb | 302 | interruptible, no_wait_gpu); |
771fe6b9 JG |
303 | if (unlikely(r)) { |
304 | return r; | |
305 | } | |
df67bed9 DA |
306 | |
307 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
308 | if (unlikely(r)) { | |
309 | goto out_cleanup; | |
310 | } | |
311 | ||
771fe6b9 JG |
312 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
313 | if (unlikely(r)) { | |
314 | goto out_cleanup; | |
315 | } | |
97a875cb | 316 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
317 | if (unlikely(r)) { |
318 | goto out_cleanup; | |
319 | } | |
97a875cb | 320 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
771fe6b9 | 321 | out_cleanup: |
42311ff9 | 322 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
323 | return r; |
324 | } | |
325 | ||
326 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 | 327 | bool evict, bool interruptible, |
97a875cb | 328 | bool no_wait_gpu, |
771fe6b9 JG |
329 | struct ttm_mem_reg *new_mem) |
330 | { | |
331 | struct radeon_device *rdev; | |
332 | struct ttm_mem_reg *old_mem = &bo->mem; | |
333 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
334 | struct ttm_placement placement; |
335 | u32 placements; | |
771fe6b9 JG |
336 | int r; |
337 | ||
338 | rdev = radeon_get_rdev(bo->bdev); | |
339 | tmp_mem = *new_mem; | |
340 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
341 | placement.fpfn = 0; |
342 | placement.lpfn = 0; | |
343 | placement.num_placement = 1; | |
344 | placement.placement = &placements; | |
345 | placement.num_busy_placement = 1; | |
346 | placement.busy_placement = &placements; | |
347 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
97a875cb ML |
348 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
349 | interruptible, no_wait_gpu); | |
771fe6b9 JG |
350 | if (unlikely(r)) { |
351 | return r; | |
352 | } | |
97a875cb | 353 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
771fe6b9 JG |
354 | if (unlikely(r)) { |
355 | goto out_cleanup; | |
356 | } | |
97a875cb | 357 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
358 | if (unlikely(r)) { |
359 | goto out_cleanup; | |
360 | } | |
361 | out_cleanup: | |
42311ff9 | 362 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
363 | return r; |
364 | } | |
365 | ||
366 | static int radeon_bo_move(struct ttm_buffer_object *bo, | |
9d87fa21 | 367 | bool evict, bool interruptible, |
97a875cb | 368 | bool no_wait_gpu, |
9d87fa21 | 369 | struct ttm_mem_reg *new_mem) |
771fe6b9 JG |
370 | { |
371 | struct radeon_device *rdev; | |
372 | struct ttm_mem_reg *old_mem = &bo->mem; | |
373 | int r; | |
374 | ||
375 | rdev = radeon_get_rdev(bo->bdev); | |
376 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
377 | radeon_move_null(bo, new_mem); | |
378 | return 0; | |
379 | } | |
380 | if ((old_mem->mem_type == TTM_PL_TT && | |
381 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
382 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
383 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 384 | /* bind is enough */ |
771fe6b9 JG |
385 | radeon_move_null(bo, new_mem); |
386 | return 0; | |
387 | } | |
27cd7769 AD |
388 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
389 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 390 | /* use memcpy */ |
1ab2e105 | 391 | goto memcpy; |
771fe6b9 JG |
392 | } |
393 | ||
394 | if (old_mem->mem_type == TTM_PL_VRAM && | |
395 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
1ab2e105 | 396 | r = radeon_move_vram_ram(bo, evict, interruptible, |
97a875cb | 397 | no_wait_gpu, new_mem); |
771fe6b9 JG |
398 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
399 | new_mem->mem_type == TTM_PL_VRAM) { | |
1ab2e105 | 400 | r = radeon_move_ram_vram(bo, evict, interruptible, |
97a875cb | 401 | no_wait_gpu, new_mem); |
771fe6b9 | 402 | } else { |
97a875cb | 403 | r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); |
771fe6b9 | 404 | } |
1ab2e105 MD |
405 | |
406 | if (r) { | |
407 | memcpy: | |
97a875cb | 408 | r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
67e8e3f9 MO |
409 | if (r) { |
410 | return r; | |
411 | } | |
1ab2e105 | 412 | } |
67e8e3f9 MO |
413 | |
414 | /* update statistics */ | |
415 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); | |
416 | return 0; | |
771fe6b9 JG |
417 | } |
418 | ||
0a2d50e3 JG |
419 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
420 | { | |
421 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
422 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
423 | ||
424 | mem->bus.addr = NULL; | |
425 | mem->bus.offset = 0; | |
426 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
427 | mem->bus.base = 0; | |
428 | mem->bus.is_iomem = false; | |
429 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
430 | return -EINVAL; | |
431 | switch (mem->mem_type) { | |
432 | case TTM_PL_SYSTEM: | |
433 | /* system memory */ | |
434 | return 0; | |
435 | case TTM_PL_TT: | |
436 | #if __OS_HAS_AGP | |
437 | if (rdev->flags & RADEON_IS_AGP) { | |
438 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 439 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 440 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 441 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
442 | } |
443 | #endif | |
444 | break; | |
445 | case TTM_PL_VRAM: | |
d961db75 | 446 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
447 | /* check if it's visible */ |
448 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
449 | return -EINVAL; | |
450 | mem->bus.base = rdev->mc.aper_base; | |
451 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
452 | #ifdef __alpha__ |
453 | /* | |
454 | * Alpha: use bus.addr to hold the ioremap() return, | |
455 | * so we can modify bus.base below. | |
456 | */ | |
457 | if (mem->placement & TTM_PL_FLAG_WC) | |
458 | mem->bus.addr = | |
459 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
460 | mem->bus.size); | |
461 | else | |
462 | mem->bus.addr = | |
463 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
464 | mem->bus.size); | |
465 | ||
466 | /* | |
467 | * Alpha: Use just the bus offset plus | |
468 | * the hose/domain memory base for bus.base. | |
469 | * It then can be used to build PTEs for VRAM | |
470 | * access, as done in ttm_bo_vm_fault(). | |
471 | */ | |
472 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
473 | rdev->ddev->hose->dense_mem_base; | |
474 | #endif | |
0a2d50e3 JG |
475 | break; |
476 | default: | |
477 | return -EINVAL; | |
478 | } | |
479 | return 0; | |
480 | } | |
481 | ||
482 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
483 | { | |
484 | } | |
485 | ||
dedfdffd | 486 | static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) |
771fe6b9 JG |
487 | { |
488 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); | |
489 | } | |
490 | ||
dedfdffd | 491 | static int radeon_sync_obj_flush(void *sync_obj) |
771fe6b9 JG |
492 | { |
493 | return 0; | |
494 | } | |
495 | ||
496 | static void radeon_sync_obj_unref(void **sync_obj) | |
497 | { | |
498 | radeon_fence_unref((struct radeon_fence **)sync_obj); | |
499 | } | |
500 | ||
501 | static void *radeon_sync_obj_ref(void *sync_obj) | |
502 | { | |
503 | return radeon_fence_ref((struct radeon_fence *)sync_obj); | |
504 | } | |
505 | ||
dedfdffd | 506 | static bool radeon_sync_obj_signaled(void *sync_obj) |
771fe6b9 JG |
507 | { |
508 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); | |
509 | } | |
510 | ||
649bf3ca JG |
511 | /* |
512 | * TTM backend functions. | |
513 | */ | |
514 | struct radeon_ttm_tt { | |
8e7e7052 | 515 | struct ttm_dma_tt ttm; |
649bf3ca JG |
516 | struct radeon_device *rdev; |
517 | u64 offset; | |
518 | }; | |
519 | ||
520 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, | |
521 | struct ttm_mem_reg *bo_mem) | |
522 | { | |
8e7e7052 | 523 | struct radeon_ttm_tt *gtt = (void*)ttm; |
77497f27 MD |
524 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
525 | RADEON_GART_PAGE_WRITE; | |
649bf3ca JG |
526 | int r; |
527 | ||
649bf3ca JG |
528 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
529 | if (!ttm->num_pages) { | |
530 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
531 | ttm->num_pages, bo_mem, ttm); | |
532 | } | |
77497f27 MD |
533 | if (ttm->caching_state == tt_cached) |
534 | flags |= RADEON_GART_PAGE_SNOOP; | |
535 | r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, | |
536 | ttm->pages, gtt->ttm.dma_address, flags); | |
649bf3ca JG |
537 | if (r) { |
538 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
539 | ttm->num_pages, (unsigned)gtt->offset); | |
540 | return r; | |
541 | } | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
546 | { | |
8e7e7052 | 547 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 548 | |
649bf3ca JG |
549 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
550 | return 0; | |
551 | } | |
552 | ||
553 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
554 | { | |
8e7e7052 | 555 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 556 | |
8e7e7052 | 557 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
558 | kfree(gtt); |
559 | } | |
560 | ||
561 | static struct ttm_backend_func radeon_backend_func = { | |
562 | .bind = &radeon_ttm_backend_bind, | |
563 | .unbind = &radeon_ttm_backend_unbind, | |
564 | .destroy = &radeon_ttm_backend_destroy, | |
565 | }; | |
566 | ||
1109ca09 | 567 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, |
649bf3ca JG |
568 | unsigned long size, uint32_t page_flags, |
569 | struct page *dummy_read_page) | |
570 | { | |
571 | struct radeon_device *rdev; | |
572 | struct radeon_ttm_tt *gtt; | |
573 | ||
574 | rdev = radeon_get_rdev(bdev); | |
575 | #if __OS_HAS_AGP | |
576 | if (rdev->flags & RADEON_IS_AGP) { | |
577 | return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, | |
578 | size, page_flags, dummy_read_page); | |
579 | } | |
580 | #endif | |
581 | ||
582 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
583 | if (gtt == NULL) { | |
584 | return NULL; | |
585 | } | |
8e7e7052 | 586 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 587 | gtt->rdev = rdev; |
8e7e7052 JG |
588 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { |
589 | kfree(gtt); | |
649bf3ca JG |
590 | return NULL; |
591 | } | |
8e7e7052 | 592 | return >t->ttm.ttm; |
649bf3ca JG |
593 | } |
594 | ||
c52494f6 KRW |
595 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm) |
596 | { | |
597 | struct radeon_device *rdev; | |
8e7e7052 | 598 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 KRW |
599 | unsigned i; |
600 | int r; | |
40f5cf99 | 601 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 KRW |
602 | |
603 | if (ttm->state != tt_unpopulated) | |
604 | return 0; | |
605 | ||
40f5cf99 AD |
606 | if (slave && ttm->sg) { |
607 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
608 | gtt->ttm.dma_address, ttm->num_pages); | |
609 | ttm->state = tt_unbound; | |
610 | return 0; | |
611 | } | |
612 | ||
c52494f6 | 613 | rdev = radeon_get_rdev(ttm->bdev); |
dea7e0ac JG |
614 | #if __OS_HAS_AGP |
615 | if (rdev->flags & RADEON_IS_AGP) { | |
616 | return ttm_agp_tt_populate(ttm); | |
617 | } | |
618 | #endif | |
c52494f6 KRW |
619 | |
620 | #ifdef CONFIG_SWIOTLB | |
621 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 622 | return ttm_dma_populate(>t->ttm, rdev->dev); |
c52494f6 KRW |
623 | } |
624 | #endif | |
625 | ||
626 | r = ttm_pool_populate(ttm); | |
627 | if (r) { | |
628 | return r; | |
629 | } | |
630 | ||
631 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
632 | gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], |
633 | 0, PAGE_SIZE, | |
634 | PCI_DMA_BIDIRECTIONAL); | |
635 | if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { | |
c52494f6 | 636 | while (--i) { |
8e7e7052 | 637 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
c52494f6 | 638 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
8e7e7052 | 639 | gtt->ttm.dma_address[i] = 0; |
c52494f6 KRW |
640 | } |
641 | ttm_pool_unpopulate(ttm); | |
642 | return -EFAULT; | |
643 | } | |
644 | } | |
645 | return 0; | |
646 | } | |
647 | ||
648 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
649 | { | |
650 | struct radeon_device *rdev; | |
8e7e7052 | 651 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 | 652 | unsigned i; |
40f5cf99 AD |
653 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
654 | ||
655 | if (slave) | |
656 | return; | |
c52494f6 KRW |
657 | |
658 | rdev = radeon_get_rdev(ttm->bdev); | |
dea7e0ac JG |
659 | #if __OS_HAS_AGP |
660 | if (rdev->flags & RADEON_IS_AGP) { | |
661 | ttm_agp_tt_unpopulate(ttm); | |
662 | return; | |
663 | } | |
664 | #endif | |
c52494f6 KRW |
665 | |
666 | #ifdef CONFIG_SWIOTLB | |
667 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 668 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
669 | return; |
670 | } | |
671 | #endif | |
672 | ||
673 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
674 | if (gtt->ttm.dma_address[i]) { |
675 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], | |
c52494f6 KRW |
676 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
677 | } | |
678 | } | |
679 | ||
680 | ttm_pool_unpopulate(ttm); | |
681 | } | |
649bf3ca | 682 | |
771fe6b9 | 683 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 684 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
685 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
686 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
771fe6b9 JG |
687 | .invalidate_caches = &radeon_invalidate_caches, |
688 | .init_mem_type = &radeon_init_mem_type, | |
689 | .evict_flags = &radeon_evict_flags, | |
690 | .move = &radeon_bo_move, | |
691 | .verify_access = &radeon_verify_access, | |
692 | .sync_obj_signaled = &radeon_sync_obj_signaled, | |
693 | .sync_obj_wait = &radeon_sync_obj_wait, | |
694 | .sync_obj_flush = &radeon_sync_obj_flush, | |
695 | .sync_obj_unref = &radeon_sync_obj_unref, | |
696 | .sync_obj_ref = &radeon_sync_obj_ref, | |
e024e110 DA |
697 | .move_notify = &radeon_bo_move_notify, |
698 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 JG |
699 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
700 | .io_mem_free = &radeon_ttm_io_mem_free, | |
771fe6b9 JG |
701 | }; |
702 | ||
703 | int radeon_ttm_init(struct radeon_device *rdev) | |
704 | { | |
705 | int r; | |
706 | ||
707 | r = radeon_ttm_global_init(rdev); | |
708 | if (r) { | |
709 | return r; | |
710 | } | |
711 | /* No others user of address space so set it to 0 */ | |
712 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
a987fcaa | 713 | rdev->mman.bo_global_ref.ref.object, |
44d847b7 DH |
714 | &radeon_bo_driver, |
715 | rdev->ddev->anon_inode->i_mapping, | |
716 | DRM_FILE_PAGE_OFFSET, | |
ad49f501 | 717 | rdev->need_dma32); |
771fe6b9 JG |
718 | if (r) { |
719 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
720 | return r; | |
721 | } | |
0a0c7596 | 722 | rdev->mman.initialized = true; |
4c788679 | 723 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
312ea8da | 724 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
771fe6b9 JG |
725 | if (r) { |
726 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
727 | return r; | |
728 | } | |
14eedc32 LK |
729 | /* Change the size here instead of the init above so only lpfn is affected */ |
730 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
731 | ||
441921d5 | 732 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
02376d82 | 733 | RADEON_GEM_DOMAIN_VRAM, 0, |
40f5cf99 | 734 | NULL, &rdev->stollen_vga_memory); |
771fe6b9 JG |
735 | if (r) { |
736 | return r; | |
737 | } | |
4c788679 JG |
738 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
739 | if (r) | |
740 | return r; | |
741 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); | |
742 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
771fe6b9 | 743 | if (r) { |
4c788679 | 744 | radeon_bo_unref(&rdev->stollen_vga_memory); |
771fe6b9 JG |
745 | return r; |
746 | } | |
747 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
fc986034 | 748 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
4c788679 | 749 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
312ea8da | 750 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
751 | if (r) { |
752 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
753 | return r; | |
754 | } | |
755 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 756 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
fa8a1238 DA |
757 | |
758 | r = radeon_ttm_debugfs_init(rdev); | |
759 | if (r) { | |
760 | DRM_ERROR("Failed to init debugfs\n"); | |
761 | return r; | |
762 | } | |
771fe6b9 JG |
763 | return 0; |
764 | } | |
765 | ||
766 | void radeon_ttm_fini(struct radeon_device *rdev) | |
767 | { | |
4c788679 JG |
768 | int r; |
769 | ||
0a0c7596 JG |
770 | if (!rdev->mman.initialized) |
771 | return; | |
2014b569 | 772 | radeon_ttm_debugfs_fini(rdev); |
771fe6b9 | 773 | if (rdev->stollen_vga_memory) { |
4c788679 JG |
774 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
775 | if (r == 0) { | |
776 | radeon_bo_unpin(rdev->stollen_vga_memory); | |
777 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
778 | } | |
779 | radeon_bo_unref(&rdev->stollen_vga_memory); | |
771fe6b9 JG |
780 | } |
781 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
782 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
783 | ttm_bo_device_release(&rdev->mman.bdev); | |
784 | radeon_gart_fini(rdev); | |
785 | radeon_ttm_global_fini(rdev); | |
0a0c7596 | 786 | rdev->mman.initialized = false; |
771fe6b9 JG |
787 | DRM_INFO("radeon: ttm finalized\n"); |
788 | } | |
789 | ||
53595338 DA |
790 | /* this should only be called at bootup or when userspace |
791 | * isn't running */ | |
792 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
793 | { | |
794 | struct ttm_mem_type_manager *man; | |
795 | ||
796 | if (!rdev->mman.initialized) | |
797 | return; | |
798 | ||
799 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
800 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
801 | man->size = size >> PAGE_SHIFT; | |
802 | } | |
803 | ||
771fe6b9 | 804 | static struct vm_operations_struct radeon_ttm_vm_ops; |
f0f37e2f | 805 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
771fe6b9 JG |
806 | |
807 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
808 | { | |
809 | struct ttm_buffer_object *bo; | |
5876dd24 | 810 | struct radeon_device *rdev; |
771fe6b9 JG |
811 | int r; |
812 | ||
5876dd24 | 813 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
771fe6b9 JG |
814 | if (bo == NULL) { |
815 | return VM_FAULT_NOPAGE; | |
816 | } | |
5876dd24 | 817 | rdev = radeon_get_rdev(bo->bdev); |
db7fce39 | 818 | down_read(&rdev->pm.mclk_lock); |
771fe6b9 | 819 | r = ttm_vm_ops->fault(vma, vmf); |
db7fce39 | 820 | up_read(&rdev->pm.mclk_lock); |
771fe6b9 JG |
821 | return r; |
822 | } | |
823 | ||
824 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) | |
825 | { | |
826 | struct drm_file *file_priv; | |
827 | struct radeon_device *rdev; | |
828 | int r; | |
829 | ||
830 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { | |
831 | return drm_mmap(filp, vma); | |
832 | } | |
833 | ||
40b3be3f | 834 | file_priv = filp->private_data; |
771fe6b9 JG |
835 | rdev = file_priv->minor->dev->dev_private; |
836 | if (rdev == NULL) { | |
837 | return -EINVAL; | |
838 | } | |
839 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); | |
840 | if (unlikely(r != 0)) { | |
841 | return r; | |
842 | } | |
843 | if (unlikely(ttm_vm_ops == NULL)) { | |
844 | ttm_vm_ops = vma->vm_ops; | |
845 | radeon_ttm_vm_ops = *ttm_vm_ops; | |
846 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; | |
847 | } | |
848 | vma->vm_ops = &radeon_ttm_vm_ops; | |
849 | return 0; | |
850 | } | |
851 | ||
fa8a1238 | 852 | #if defined(CONFIG_DEBUG_FS) |
893d6e6e | 853 | |
fa8a1238 DA |
854 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
855 | { | |
856 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
893d6e6e | 857 | unsigned ttm_pl = *(int *)node->info_ent->data; |
fa8a1238 DA |
858 | struct drm_device *dev = node->minor->dev; |
859 | struct radeon_device *rdev = dev->dev_private; | |
893d6e6e | 860 | struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; |
fa8a1238 DA |
861 | int ret; |
862 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; | |
863 | ||
864 | spin_lock(&glob->lru_lock); | |
865 | ret = drm_mm_dump_table(m, mm); | |
866 | spin_unlock(&glob->lru_lock); | |
867 | return ret; | |
868 | } | |
893d6e6e CK |
869 | |
870 | static int ttm_pl_vram = TTM_PL_VRAM; | |
871 | static int ttm_pl_tt = TTM_PL_TT; | |
872 | ||
873 | static struct drm_info_list radeon_ttm_debugfs_list[] = { | |
874 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, | |
875 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, | |
876 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
877 | #ifdef CONFIG_SWIOTLB | |
878 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
879 | #endif | |
880 | }; | |
881 | ||
2014b569 CK |
882 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
883 | { | |
884 | struct radeon_device *rdev = inode->i_private; | |
885 | i_size_write(inode, rdev->mc.mc_vram_size); | |
886 | filep->private_data = inode->i_private; | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, | |
891 | size_t size, loff_t *pos) | |
892 | { | |
893 | struct radeon_device *rdev = f->private_data; | |
894 | ssize_t result = 0; | |
895 | int r; | |
896 | ||
897 | if (size & 0x3 || *pos & 0x3) | |
898 | return -EINVAL; | |
899 | ||
900 | while (size) { | |
901 | unsigned long flags; | |
902 | uint32_t value; | |
903 | ||
904 | if (*pos >= rdev->mc.mc_vram_size) | |
905 | return result; | |
906 | ||
907 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
908 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
909 | if (rdev->family >= CHIP_CEDAR) | |
910 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); | |
911 | value = RREG32(RADEON_MM_DATA); | |
912 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
913 | ||
914 | r = put_user(value, (uint32_t *)buf); | |
915 | if (r) | |
916 | return r; | |
917 | ||
918 | result += 4; | |
919 | buf += 4; | |
920 | *pos += 4; | |
921 | size -= 4; | |
922 | } | |
923 | ||
924 | return result; | |
925 | } | |
926 | ||
927 | static const struct file_operations radeon_ttm_vram_fops = { | |
928 | .owner = THIS_MODULE, | |
929 | .open = radeon_ttm_vram_open, | |
930 | .read = radeon_ttm_vram_read, | |
931 | .llseek = default_llseek | |
932 | }; | |
933 | ||
dd66d20e CK |
934 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
935 | { | |
936 | struct radeon_device *rdev = inode->i_private; | |
937 | i_size_write(inode, rdev->mc.gtt_size); | |
938 | filep->private_data = inode->i_private; | |
939 | return 0; | |
940 | } | |
941 | ||
942 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |
943 | size_t size, loff_t *pos) | |
944 | { | |
945 | struct radeon_device *rdev = f->private_data; | |
946 | ssize_t result = 0; | |
947 | int r; | |
948 | ||
949 | while (size) { | |
950 | loff_t p = *pos / PAGE_SIZE; | |
951 | unsigned off = *pos & ~PAGE_MASK; | |
0d997b68 | 952 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
dd66d20e CK |
953 | struct page *page; |
954 | void *ptr; | |
955 | ||
956 | if (p >= rdev->gart.num_cpu_pages) | |
957 | return result; | |
958 | ||
959 | page = rdev->gart.pages[p]; | |
960 | if (page) { | |
961 | ptr = kmap(page); | |
962 | ptr += off; | |
963 | ||
964 | r = copy_to_user(buf, ptr, cur_size); | |
965 | kunmap(rdev->gart.pages[p]); | |
966 | } else | |
967 | r = clear_user(buf, cur_size); | |
968 | ||
969 | if (r) | |
970 | return -EFAULT; | |
971 | ||
972 | result += cur_size; | |
973 | buf += cur_size; | |
974 | *pos += cur_size; | |
975 | size -= cur_size; | |
976 | } | |
977 | ||
978 | return result; | |
979 | } | |
980 | ||
981 | static const struct file_operations radeon_ttm_gtt_fops = { | |
982 | .owner = THIS_MODULE, | |
983 | .open = radeon_ttm_gtt_open, | |
984 | .read = radeon_ttm_gtt_read, | |
985 | .llseek = default_llseek | |
986 | }; | |
987 | ||
fa8a1238 DA |
988 | #endif |
989 | ||
990 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
991 | { | |
f4e45d02 | 992 | #if defined(CONFIG_DEBUG_FS) |
2014b569 CK |
993 | unsigned count; |
994 | ||
995 | struct drm_minor *minor = rdev->ddev->primary; | |
996 | struct dentry *ent, *root = minor->debugfs_root; | |
997 | ||
998 | ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, | |
999 | rdev, &radeon_ttm_vram_fops); | |
1000 | if (IS_ERR(ent)) | |
1001 | return PTR_ERR(ent); | |
1002 | rdev->mman.vram = ent; | |
1003 | ||
dd66d20e CK |
1004 | ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, |
1005 | rdev, &radeon_ttm_gtt_fops); | |
1006 | if (IS_ERR(ent)) | |
1007 | return PTR_ERR(ent); | |
1008 | rdev->mman.gtt = ent; | |
1009 | ||
2014b569 | 1010 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
fa8a1238 | 1011 | |
c52494f6 | 1012 | #ifdef CONFIG_SWIOTLB |
893d6e6e CK |
1013 | if (!swiotlb_nr_tbl()) |
1014 | --count; | |
c52494f6 | 1015 | #endif |
fa8a1238 | 1016 | |
893d6e6e CK |
1017 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
1018 | #else | |
1019 | ||
fa8a1238 | 1020 | return 0; |
893d6e6e | 1021 | #endif |
fa8a1238 | 1022 | } |
2014b569 CK |
1023 | |
1024 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) | |
1025 | { | |
1026 | #if defined(CONFIG_DEBUG_FS) | |
1027 | ||
1028 | debugfs_remove(rdev->mman.vram); | |
1029 | rdev->mman.vram = NULL; | |
dd66d20e CK |
1030 | |
1031 | debugfs_remove(rdev->mman.gtt); | |
1032 | rdev->mman.gtt = NULL; | |
2014b569 CK |
1033 | #endif |
1034 | } |