Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <ttm/ttm_bo_api.h> | |
33 | #include <ttm/ttm_bo_driver.h> | |
34 | #include <ttm/ttm_placement.h> | |
35 | #include <ttm/ttm_module.h> | |
8d7cddcd | 36 | #include <ttm/ttm_page_alloc.h> |
771fe6b9 JG |
37 | #include <drm/drmP.h> |
38 | #include <drm/radeon_drm.h> | |
fa8a1238 | 39 | #include <linux/seq_file.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
771fe6b9 JG |
41 | #include "radeon_reg.h" |
42 | #include "radeon.h" | |
43 | ||
44 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
45 | ||
fa8a1238 DA |
46 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
47 | ||
771fe6b9 JG |
48 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
49 | { | |
50 | struct radeon_mman *mman; | |
51 | struct radeon_device *rdev; | |
52 | ||
53 | mman = container_of(bdev, struct radeon_mman, bdev); | |
54 | rdev = container_of(mman, struct radeon_device, mman); | |
55 | return rdev; | |
56 | } | |
57 | ||
58 | ||
59 | /* | |
60 | * Global memory. | |
61 | */ | |
ba4420c2 | 62 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
771fe6b9 JG |
63 | { |
64 | return ttm_mem_global_init(ref->object); | |
65 | } | |
66 | ||
ba4420c2 | 67 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
771fe6b9 JG |
68 | { |
69 | ttm_mem_global_release(ref->object); | |
70 | } | |
71 | ||
72 | static int radeon_ttm_global_init(struct radeon_device *rdev) | |
73 | { | |
ba4420c2 | 74 | struct drm_global_reference *global_ref; |
771fe6b9 JG |
75 | int r; |
76 | ||
77 | rdev->mman.mem_global_referenced = false; | |
78 | global_ref = &rdev->mman.mem_global_ref; | |
ba4420c2 | 79 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
771fe6b9 JG |
80 | global_ref->size = sizeof(struct ttm_mem_global); |
81 | global_ref->init = &radeon_ttm_mem_global_init; | |
82 | global_ref->release = &radeon_ttm_mem_global_release; | |
ba4420c2 | 83 | r = drm_global_item_ref(global_ref); |
771fe6b9 | 84 | if (r != 0) { |
a987fcaa TH |
85 | DRM_ERROR("Failed setting up TTM memory accounting " |
86 | "subsystem.\n"); | |
771fe6b9 JG |
87 | return r; |
88 | } | |
a987fcaa TH |
89 | |
90 | rdev->mman.bo_global_ref.mem_glob = | |
91 | rdev->mman.mem_global_ref.object; | |
92 | global_ref = &rdev->mman.bo_global_ref.ref; | |
ba4420c2 | 93 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
7f5f4db2 | 94 | global_ref->size = sizeof(struct ttm_bo_global); |
a987fcaa TH |
95 | global_ref->init = &ttm_bo_global_init; |
96 | global_ref->release = &ttm_bo_global_release; | |
ba4420c2 | 97 | r = drm_global_item_ref(global_ref); |
a987fcaa TH |
98 | if (r != 0) { |
99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | |
ba4420c2 | 100 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
a987fcaa TH |
101 | return r; |
102 | } | |
103 | ||
771fe6b9 JG |
104 | rdev->mman.mem_global_referenced = true; |
105 | return 0; | |
106 | } | |
107 | ||
108 | static void radeon_ttm_global_fini(struct radeon_device *rdev) | |
109 | { | |
110 | if (rdev->mman.mem_global_referenced) { | |
ba4420c2 DA |
111 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
112 | drm_global_item_unref(&rdev->mman.mem_global_ref); | |
771fe6b9 JG |
113 | rdev->mman.mem_global_referenced = false; |
114 | } | |
115 | } | |
116 | ||
117 | struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev); | |
118 | ||
119 | static struct ttm_backend* | |
120 | radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev) | |
121 | { | |
122 | struct radeon_device *rdev; | |
123 | ||
124 | rdev = radeon_get_rdev(bdev); | |
125 | #if __OS_HAS_AGP | |
126 | if (rdev->flags & RADEON_IS_AGP) { | |
127 | return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge); | |
128 | } else | |
129 | #endif | |
130 | { | |
131 | return radeon_ttm_backend_create(rdev); | |
132 | } | |
133 | } | |
134 | ||
135 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
136 | { | |
137 | return 0; | |
138 | } | |
139 | ||
140 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
141 | struct ttm_mem_type_manager *man) | |
142 | { | |
143 | struct radeon_device *rdev; | |
144 | ||
145 | rdev = radeon_get_rdev(bdev); | |
146 | ||
147 | switch (type) { | |
148 | case TTM_PL_SYSTEM: | |
149 | /* System memory */ | |
150 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
151 | man->available_caching = TTM_PL_MASK_CACHING; | |
152 | man->default_caching = TTM_PL_FLAG_CACHED; | |
153 | break; | |
154 | case TTM_PL_TT: | |
d961db75 | 155 | man->func = &ttm_bo_manager_func; |
d594e46a | 156 | man->gpu_offset = rdev->mc.gtt_start; |
771fe6b9 JG |
157 | man->available_caching = TTM_PL_MASK_CACHING; |
158 | man->default_caching = TTM_PL_FLAG_CACHED; | |
55c93278 | 159 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
771fe6b9 JG |
160 | #if __OS_HAS_AGP |
161 | if (rdev->flags & RADEON_IS_AGP) { | |
162 | if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { | |
163 | DRM_ERROR("AGP is not enabled for memory type %u\n", | |
164 | (unsigned)type); | |
165 | return -EINVAL; | |
166 | } | |
55c93278 | 167 | if (!rdev->ddev->agp->cant_use_aperture) |
0a2d50e3 | 168 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
771fe6b9 JG |
169 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
170 | TTM_PL_FLAG_WC; | |
171 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 | 172 | } |
0c321c79 | 173 | #endif |
771fe6b9 JG |
174 | break; |
175 | case TTM_PL_VRAM: | |
176 | /* "On-card" video ram */ | |
d961db75 | 177 | man->func = &ttm_bo_manager_func; |
d594e46a | 178 | man->gpu_offset = rdev->mc.vram_start; |
771fe6b9 | 179 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
771fe6b9 JG |
180 | TTM_MEMTYPE_FLAG_MAPPABLE; |
181 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
182 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 JG |
183 | break; |
184 | default: | |
185 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
186 | return -EINVAL; | |
187 | } | |
188 | return 0; | |
189 | } | |
190 | ||
312ea8da JG |
191 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
192 | struct ttm_placement *placement) | |
771fe6b9 | 193 | { |
d03d8589 JG |
194 | struct radeon_bo *rbo; |
195 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
196 | ||
197 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
198 | placement->fpfn = 0; | |
199 | placement->lpfn = 0; | |
200 | placement->placement = &placements; | |
201 | placement->busy_placement = &placements; | |
202 | placement->num_placement = 1; | |
203 | placement->num_busy_placement = 1; | |
204 | return; | |
205 | } | |
206 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 207 | switch (bo->mem.mem_type) { |
312ea8da | 208 | case TTM_PL_VRAM: |
9270eb1b DA |
209 | if (rbo->rdev->cp.ready == false) |
210 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); | |
211 | else | |
212 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
312ea8da JG |
213 | break; |
214 | case TTM_PL_TT: | |
771fe6b9 | 215 | default: |
312ea8da | 216 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 217 | } |
eaa5fd1a | 218 | *placement = rbo->placement; |
771fe6b9 JG |
219 | } |
220 | ||
221 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
222 | { | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
227 | struct ttm_mem_reg *new_mem) | |
228 | { | |
229 | struct ttm_mem_reg *old_mem = &bo->mem; | |
230 | ||
231 | BUG_ON(old_mem->mm_node != NULL); | |
232 | *old_mem = *new_mem; | |
233 | new_mem->mm_node = NULL; | |
234 | } | |
235 | ||
236 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
237 | bool evict, int no_wait_reserve, bool no_wait_gpu, |
238 | struct ttm_mem_reg *new_mem, | |
239 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
240 | { |
241 | struct radeon_device *rdev; | |
242 | uint64_t old_start, new_start; | |
243 | struct radeon_fence *fence; | |
244 | int r; | |
245 | ||
246 | rdev = radeon_get_rdev(bo->bdev); | |
247 | r = radeon_fence_create(rdev, &fence); | |
248 | if (unlikely(r)) { | |
249 | return r; | |
250 | } | |
d961db75 BS |
251 | old_start = old_mem->start << PAGE_SHIFT; |
252 | new_start = new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
253 | |
254 | switch (old_mem->mem_type) { | |
255 | case TTM_PL_VRAM: | |
d594e46a | 256 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
257 | break; |
258 | case TTM_PL_TT: | |
d594e46a | 259 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
260 | break; |
261 | default: | |
262 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
263 | return -EINVAL; | |
264 | } | |
265 | switch (new_mem->mem_type) { | |
266 | case TTM_PL_VRAM: | |
d594e46a | 267 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
268 | break; |
269 | case TTM_PL_TT: | |
d594e46a | 270 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
271 | break; |
272 | default: | |
273 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
274 | return -EINVAL; | |
275 | } | |
276 | if (!rdev->cp.ready) { | |
277 | DRM_ERROR("Trying to move memory with CP turned off.\n"); | |
278 | return -EINVAL; | |
279 | } | |
003cefe0 AD |
280 | |
281 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
282 | ||
283 | r = radeon_copy(rdev, old_start, new_start, | |
284 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ | |
285 | fence); | |
771fe6b9 JG |
286 | /* FIXME: handle copy error */ |
287 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL, | |
9d87fa21 | 288 | evict, no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 JG |
289 | radeon_fence_unref(&fence); |
290 | return r; | |
291 | } | |
292 | ||
293 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
294 | bool evict, bool interruptible, |
295 | bool no_wait_reserve, bool no_wait_gpu, | |
771fe6b9 JG |
296 | struct ttm_mem_reg *new_mem) |
297 | { | |
298 | struct radeon_device *rdev; | |
299 | struct ttm_mem_reg *old_mem = &bo->mem; | |
300 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
301 | u32 placements; |
302 | struct ttm_placement placement; | |
771fe6b9 JG |
303 | int r; |
304 | ||
305 | rdev = radeon_get_rdev(bo->bdev); | |
306 | tmp_mem = *new_mem; | |
307 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
308 | placement.fpfn = 0; |
309 | placement.lpfn = 0; | |
310 | placement.num_placement = 1; | |
311 | placement.placement = &placements; | |
312 | placement.num_busy_placement = 1; | |
313 | placement.busy_placement = &placements; | |
314 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
315 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
9d87fa21 | 316 | interruptible, no_wait_reserve, no_wait_gpu); |
771fe6b9 JG |
317 | if (unlikely(r)) { |
318 | return r; | |
319 | } | |
df67bed9 DA |
320 | |
321 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
322 | if (unlikely(r)) { | |
323 | goto out_cleanup; | |
324 | } | |
325 | ||
771fe6b9 JG |
326 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
327 | if (unlikely(r)) { | |
328 | goto out_cleanup; | |
329 | } | |
9d87fa21 | 330 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
331 | if (unlikely(r)) { |
332 | goto out_cleanup; | |
333 | } | |
9d87fa21 | 334 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 | 335 | out_cleanup: |
42311ff9 | 336 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
337 | return r; |
338 | } | |
339 | ||
340 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
341 | bool evict, bool interruptible, |
342 | bool no_wait_reserve, bool no_wait_gpu, | |
771fe6b9 JG |
343 | struct ttm_mem_reg *new_mem) |
344 | { | |
345 | struct radeon_device *rdev; | |
346 | struct ttm_mem_reg *old_mem = &bo->mem; | |
347 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
348 | struct ttm_placement placement; |
349 | u32 placements; | |
771fe6b9 JG |
350 | int r; |
351 | ||
352 | rdev = radeon_get_rdev(bo->bdev); | |
353 | tmp_mem = *new_mem; | |
354 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
355 | placement.fpfn = 0; |
356 | placement.lpfn = 0; | |
357 | placement.num_placement = 1; | |
358 | placement.placement = &placements; | |
359 | placement.num_busy_placement = 1; | |
360 | placement.busy_placement = &placements; | |
361 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
9d87fa21 | 362 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu); |
771fe6b9 JG |
363 | if (unlikely(r)) { |
364 | return r; | |
365 | } | |
9d87fa21 | 366 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem); |
771fe6b9 JG |
367 | if (unlikely(r)) { |
368 | goto out_cleanup; | |
369 | } | |
9d87fa21 | 370 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
371 | if (unlikely(r)) { |
372 | goto out_cleanup; | |
373 | } | |
374 | out_cleanup: | |
42311ff9 | 375 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
376 | return r; |
377 | } | |
378 | ||
379 | static int radeon_bo_move(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
380 | bool evict, bool interruptible, |
381 | bool no_wait_reserve, bool no_wait_gpu, | |
382 | struct ttm_mem_reg *new_mem) | |
771fe6b9 JG |
383 | { |
384 | struct radeon_device *rdev; | |
385 | struct ttm_mem_reg *old_mem = &bo->mem; | |
386 | int r; | |
387 | ||
388 | rdev = radeon_get_rdev(bo->bdev); | |
389 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
390 | radeon_move_null(bo, new_mem); | |
391 | return 0; | |
392 | } | |
393 | if ((old_mem->mem_type == TTM_PL_TT && | |
394 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
395 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
396 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 397 | /* bind is enough */ |
771fe6b9 JG |
398 | radeon_move_null(bo, new_mem); |
399 | return 0; | |
400 | } | |
3ce0a23d | 401 | if (!rdev->cp.ready || rdev->asic->copy == NULL) { |
771fe6b9 | 402 | /* use memcpy */ |
1ab2e105 | 403 | goto memcpy; |
771fe6b9 JG |
404 | } |
405 | ||
406 | if (old_mem->mem_type == TTM_PL_VRAM && | |
407 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
1ab2e105 | 408 | r = radeon_move_vram_ram(bo, evict, interruptible, |
9d87fa21 | 409 | no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 JG |
410 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
411 | new_mem->mem_type == TTM_PL_VRAM) { | |
1ab2e105 | 412 | r = radeon_move_ram_vram(bo, evict, interruptible, |
9d87fa21 | 413 | no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 | 414 | } else { |
9d87fa21 | 415 | r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
771fe6b9 | 416 | } |
1ab2e105 MD |
417 | |
418 | if (r) { | |
419 | memcpy: | |
9d87fa21 | 420 | r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
1ab2e105 | 421 | } |
771fe6b9 JG |
422 | return r; |
423 | } | |
424 | ||
0a2d50e3 JG |
425 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
426 | { | |
427 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
428 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
429 | ||
430 | mem->bus.addr = NULL; | |
431 | mem->bus.offset = 0; | |
432 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
433 | mem->bus.base = 0; | |
434 | mem->bus.is_iomem = false; | |
435 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
436 | return -EINVAL; | |
437 | switch (mem->mem_type) { | |
438 | case TTM_PL_SYSTEM: | |
439 | /* system memory */ | |
440 | return 0; | |
441 | case TTM_PL_TT: | |
442 | #if __OS_HAS_AGP | |
443 | if (rdev->flags & RADEON_IS_AGP) { | |
444 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 445 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 446 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 447 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
448 | } |
449 | #endif | |
450 | break; | |
451 | case TTM_PL_VRAM: | |
d961db75 | 452 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
453 | /* check if it's visible */ |
454 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
455 | return -EINVAL; | |
456 | mem->bus.base = rdev->mc.aper_base; | |
457 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
458 | #ifdef __alpha__ |
459 | /* | |
460 | * Alpha: use bus.addr to hold the ioremap() return, | |
461 | * so we can modify bus.base below. | |
462 | */ | |
463 | if (mem->placement & TTM_PL_FLAG_WC) | |
464 | mem->bus.addr = | |
465 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
466 | mem->bus.size); | |
467 | else | |
468 | mem->bus.addr = | |
469 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
470 | mem->bus.size); | |
471 | ||
472 | /* | |
473 | * Alpha: Use just the bus offset plus | |
474 | * the hose/domain memory base for bus.base. | |
475 | * It then can be used to build PTEs for VRAM | |
476 | * access, as done in ttm_bo_vm_fault(). | |
477 | */ | |
478 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
479 | rdev->ddev->hose->dense_mem_base; | |
480 | #endif | |
0a2d50e3 JG |
481 | break; |
482 | default: | |
483 | return -EINVAL; | |
484 | } | |
485 | return 0; | |
486 | } | |
487 | ||
488 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
489 | { | |
490 | } | |
491 | ||
771fe6b9 JG |
492 | static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg, |
493 | bool lazy, bool interruptible) | |
494 | { | |
495 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); | |
496 | } | |
497 | ||
498 | static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg) | |
499 | { | |
500 | return 0; | |
501 | } | |
502 | ||
503 | static void radeon_sync_obj_unref(void **sync_obj) | |
504 | { | |
505 | radeon_fence_unref((struct radeon_fence **)sync_obj); | |
506 | } | |
507 | ||
508 | static void *radeon_sync_obj_ref(void *sync_obj) | |
509 | { | |
510 | return radeon_fence_ref((struct radeon_fence *)sync_obj); | |
511 | } | |
512 | ||
513 | static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg) | |
514 | { | |
515 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); | |
516 | } | |
517 | ||
518 | static struct ttm_bo_driver radeon_bo_driver = { | |
771fe6b9 JG |
519 | .create_ttm_backend_entry = &radeon_create_ttm_backend_entry, |
520 | .invalidate_caches = &radeon_invalidate_caches, | |
521 | .init_mem_type = &radeon_init_mem_type, | |
522 | .evict_flags = &radeon_evict_flags, | |
523 | .move = &radeon_bo_move, | |
524 | .verify_access = &radeon_verify_access, | |
525 | .sync_obj_signaled = &radeon_sync_obj_signaled, | |
526 | .sync_obj_wait = &radeon_sync_obj_wait, | |
527 | .sync_obj_flush = &radeon_sync_obj_flush, | |
528 | .sync_obj_unref = &radeon_sync_obj_unref, | |
529 | .sync_obj_ref = &radeon_sync_obj_ref, | |
e024e110 DA |
530 | .move_notify = &radeon_bo_move_notify, |
531 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 JG |
532 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
533 | .io_mem_free = &radeon_ttm_io_mem_free, | |
771fe6b9 JG |
534 | }; |
535 | ||
536 | int radeon_ttm_init(struct radeon_device *rdev) | |
537 | { | |
538 | int r; | |
539 | ||
540 | r = radeon_ttm_global_init(rdev); | |
541 | if (r) { | |
542 | return r; | |
543 | } | |
544 | /* No others user of address space so set it to 0 */ | |
545 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
a987fcaa | 546 | rdev->mman.bo_global_ref.ref.object, |
ad49f501 DA |
547 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
548 | rdev->need_dma32); | |
771fe6b9 JG |
549 | if (r) { |
550 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
551 | return r; | |
552 | } | |
0a0c7596 | 553 | rdev->mman.initialized = true; |
4c788679 | 554 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
312ea8da | 555 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
771fe6b9 JG |
556 | if (r) { |
557 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
558 | return r; | |
559 | } | |
441921d5 | 560 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
4c788679 JG |
561 | RADEON_GEM_DOMAIN_VRAM, |
562 | &rdev->stollen_vga_memory); | |
771fe6b9 JG |
563 | if (r) { |
564 | return r; | |
565 | } | |
4c788679 JG |
566 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
567 | if (r) | |
568 | return r; | |
569 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); | |
570 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
771fe6b9 | 571 | if (r) { |
4c788679 | 572 | radeon_bo_unref(&rdev->stollen_vga_memory); |
771fe6b9 JG |
573 | return r; |
574 | } | |
575 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
3ce0a23d | 576 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); |
4c788679 | 577 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
312ea8da | 578 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
579 | if (r) { |
580 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
581 | return r; | |
582 | } | |
583 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 584 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
771fe6b9 JG |
585 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
586 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
587 | } | |
fa8a1238 DA |
588 | |
589 | r = radeon_ttm_debugfs_init(rdev); | |
590 | if (r) { | |
591 | DRM_ERROR("Failed to init debugfs\n"); | |
592 | return r; | |
593 | } | |
771fe6b9 JG |
594 | return 0; |
595 | } | |
596 | ||
597 | void radeon_ttm_fini(struct radeon_device *rdev) | |
598 | { | |
4c788679 JG |
599 | int r; |
600 | ||
0a0c7596 JG |
601 | if (!rdev->mman.initialized) |
602 | return; | |
771fe6b9 | 603 | if (rdev->stollen_vga_memory) { |
4c788679 JG |
604 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
605 | if (r == 0) { | |
606 | radeon_bo_unpin(rdev->stollen_vga_memory); | |
607 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
608 | } | |
609 | radeon_bo_unref(&rdev->stollen_vga_memory); | |
771fe6b9 JG |
610 | } |
611 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
612 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
613 | ttm_bo_device_release(&rdev->mman.bdev); | |
614 | radeon_gart_fini(rdev); | |
615 | radeon_ttm_global_fini(rdev); | |
0a0c7596 | 616 | rdev->mman.initialized = false; |
771fe6b9 JG |
617 | DRM_INFO("radeon: ttm finalized\n"); |
618 | } | |
619 | ||
53595338 DA |
620 | /* this should only be called at bootup or when userspace |
621 | * isn't running */ | |
622 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
623 | { | |
624 | struct ttm_mem_type_manager *man; | |
625 | ||
626 | if (!rdev->mman.initialized) | |
627 | return; | |
628 | ||
629 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
630 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
631 | man->size = size >> PAGE_SHIFT; | |
632 | } | |
633 | ||
771fe6b9 | 634 | static struct vm_operations_struct radeon_ttm_vm_ops; |
f0f37e2f | 635 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
771fe6b9 JG |
636 | |
637 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
638 | { | |
639 | struct ttm_buffer_object *bo; | |
5876dd24 | 640 | struct radeon_device *rdev; |
771fe6b9 JG |
641 | int r; |
642 | ||
5876dd24 | 643 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
771fe6b9 JG |
644 | if (bo == NULL) { |
645 | return VM_FAULT_NOPAGE; | |
646 | } | |
5876dd24 MG |
647 | rdev = radeon_get_rdev(bo->bdev); |
648 | mutex_lock(&rdev->vram_mutex); | |
771fe6b9 | 649 | r = ttm_vm_ops->fault(vma, vmf); |
5876dd24 | 650 | mutex_unlock(&rdev->vram_mutex); |
771fe6b9 JG |
651 | return r; |
652 | } | |
653 | ||
654 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) | |
655 | { | |
656 | struct drm_file *file_priv; | |
657 | struct radeon_device *rdev; | |
658 | int r; | |
659 | ||
660 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { | |
661 | return drm_mmap(filp, vma); | |
662 | } | |
663 | ||
40b3be3f | 664 | file_priv = filp->private_data; |
771fe6b9 JG |
665 | rdev = file_priv->minor->dev->dev_private; |
666 | if (rdev == NULL) { | |
667 | return -EINVAL; | |
668 | } | |
669 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); | |
670 | if (unlikely(r != 0)) { | |
671 | return r; | |
672 | } | |
673 | if (unlikely(ttm_vm_ops == NULL)) { | |
674 | ttm_vm_ops = vma->vm_ops; | |
675 | radeon_ttm_vm_ops = *ttm_vm_ops; | |
676 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; | |
677 | } | |
678 | vma->vm_ops = &radeon_ttm_vm_ops; | |
679 | return 0; | |
680 | } | |
681 | ||
682 | ||
683 | /* | |
684 | * TTM backend functions. | |
685 | */ | |
686 | struct radeon_ttm_backend { | |
687 | struct ttm_backend backend; | |
688 | struct radeon_device *rdev; | |
689 | unsigned long num_pages; | |
690 | struct page **pages; | |
691 | struct page *dummy_read_page; | |
c39d3516 | 692 | dma_addr_t *dma_addrs; |
771fe6b9 JG |
693 | bool populated; |
694 | bool bound; | |
695 | unsigned offset; | |
696 | }; | |
697 | ||
698 | static int radeon_ttm_backend_populate(struct ttm_backend *backend, | |
699 | unsigned long num_pages, | |
700 | struct page **pages, | |
27e8b237 KRW |
701 | struct page *dummy_read_page, |
702 | dma_addr_t *dma_addrs) | |
771fe6b9 JG |
703 | { |
704 | struct radeon_ttm_backend *gtt; | |
705 | ||
706 | gtt = container_of(backend, struct radeon_ttm_backend, backend); | |
707 | gtt->pages = pages; | |
c39d3516 | 708 | gtt->dma_addrs = dma_addrs; |
771fe6b9 JG |
709 | gtt->num_pages = num_pages; |
710 | gtt->dummy_read_page = dummy_read_page; | |
711 | gtt->populated = true; | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static void radeon_ttm_backend_clear(struct ttm_backend *backend) | |
716 | { | |
717 | struct radeon_ttm_backend *gtt; | |
718 | ||
719 | gtt = container_of(backend, struct radeon_ttm_backend, backend); | |
720 | gtt->pages = NULL; | |
c39d3516 | 721 | gtt->dma_addrs = NULL; |
771fe6b9 JG |
722 | gtt->num_pages = 0; |
723 | gtt->dummy_read_page = NULL; | |
724 | gtt->populated = false; | |
725 | gtt->bound = false; | |
726 | } | |
727 | ||
728 | ||
729 | static int radeon_ttm_backend_bind(struct ttm_backend *backend, | |
730 | struct ttm_mem_reg *bo_mem) | |
731 | { | |
732 | struct radeon_ttm_backend *gtt; | |
733 | int r; | |
734 | ||
735 | gtt = container_of(backend, struct radeon_ttm_backend, backend); | |
d961db75 | 736 | gtt->offset = bo_mem->start << PAGE_SHIFT; |
771fe6b9 | 737 | if (!gtt->num_pages) { |
fce7d61b JP |
738 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", |
739 | gtt->num_pages, bo_mem, backend); | |
771fe6b9 JG |
740 | } |
741 | r = radeon_gart_bind(gtt->rdev, gtt->offset, | |
c39d3516 | 742 | gtt->num_pages, gtt->pages, gtt->dma_addrs); |
771fe6b9 JG |
743 | if (r) { |
744 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
745 | gtt->num_pages, gtt->offset); | |
746 | return r; | |
747 | } | |
748 | gtt->bound = true; | |
749 | return 0; | |
750 | } | |
751 | ||
752 | static int radeon_ttm_backend_unbind(struct ttm_backend *backend) | |
753 | { | |
754 | struct radeon_ttm_backend *gtt; | |
755 | ||
756 | gtt = container_of(backend, struct radeon_ttm_backend, backend); | |
757 | radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages); | |
758 | gtt->bound = false; | |
759 | return 0; | |
760 | } | |
761 | ||
762 | static void radeon_ttm_backend_destroy(struct ttm_backend *backend) | |
763 | { | |
764 | struct radeon_ttm_backend *gtt; | |
765 | ||
766 | gtt = container_of(backend, struct radeon_ttm_backend, backend); | |
767 | if (gtt->bound) { | |
768 | radeon_ttm_backend_unbind(backend); | |
769 | } | |
770 | kfree(gtt); | |
771 | } | |
772 | ||
773 | static struct ttm_backend_func radeon_backend_func = { | |
774 | .populate = &radeon_ttm_backend_populate, | |
775 | .clear = &radeon_ttm_backend_clear, | |
776 | .bind = &radeon_ttm_backend_bind, | |
777 | .unbind = &radeon_ttm_backend_unbind, | |
778 | .destroy = &radeon_ttm_backend_destroy, | |
779 | }; | |
780 | ||
781 | struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev) | |
782 | { | |
783 | struct radeon_ttm_backend *gtt; | |
784 | ||
785 | gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL); | |
786 | if (gtt == NULL) { | |
787 | return NULL; | |
788 | } | |
789 | gtt->backend.bdev = &rdev->mman.bdev; | |
771fe6b9 JG |
790 | gtt->backend.func = &radeon_backend_func; |
791 | gtt->rdev = rdev; | |
792 | gtt->pages = NULL; | |
793 | gtt->num_pages = 0; | |
794 | gtt->dummy_read_page = NULL; | |
795 | gtt->populated = false; | |
796 | gtt->bound = false; | |
797 | return >t->backend; | |
798 | } | |
fa8a1238 DA |
799 | |
800 | #define RADEON_DEBUGFS_MEM_TYPES 2 | |
801 | ||
fa8a1238 DA |
802 | #if defined(CONFIG_DEBUG_FS) |
803 | static int radeon_mm_dump_table(struct seq_file *m, void *data) | |
804 | { | |
805 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
806 | struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; | |
807 | struct drm_device *dev = node->minor->dev; | |
808 | struct radeon_device *rdev = dev->dev_private; | |
809 | int ret; | |
810 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; | |
811 | ||
812 | spin_lock(&glob->lru_lock); | |
813 | ret = drm_mm_dump_table(m, mm); | |
814 | spin_unlock(&glob->lru_lock); | |
815 | return ret; | |
816 | } | |
817 | #endif | |
818 | ||
819 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
820 | { | |
f4e45d02 | 821 | #if defined(CONFIG_DEBUG_FS) |
8d7cddcd PN |
822 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+1]; |
823 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+1][32]; | |
fa8a1238 DA |
824 | unsigned i; |
825 | ||
fa8a1238 DA |
826 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { |
827 | if (i == 0) | |
828 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); | |
829 | else | |
830 | sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); | |
831 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
832 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; | |
833 | radeon_mem_types_list[i].driver_features = 0; | |
834 | if (i == 0) | |
16f9fdcb | 835 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; |
fa8a1238 | 836 | else |
16f9fdcb | 837 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; |
fa8a1238 DA |
838 | |
839 | } | |
8d7cddcd PN |
840 | /* Add ttm page pool to debugfs */ |
841 | sprintf(radeon_mem_types_names[i], "ttm_page_pool"); | |
842 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
843 | radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; | |
844 | radeon_mem_types_list[i].driver_features = 0; | |
845 | radeon_mem_types_list[i].data = NULL; | |
846 | return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES+1); | |
fa8a1238 DA |
847 | |
848 | #endif | |
849 | return 0; | |
850 | } |