Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <ttm/ttm_bo_api.h> | |
33 | #include <ttm/ttm_bo_driver.h> | |
34 | #include <ttm/ttm_placement.h> | |
35 | #include <ttm/ttm_module.h> | |
8d7cddcd | 36 | #include <ttm/ttm_page_alloc.h> |
771fe6b9 JG |
37 | #include <drm/drmP.h> |
38 | #include <drm/radeon_drm.h> | |
fa8a1238 | 39 | #include <linux/seq_file.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
771fe6b9 JG |
41 | #include "radeon_reg.h" |
42 | #include "radeon.h" | |
43 | ||
44 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
45 | ||
fa8a1238 DA |
46 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
47 | ||
771fe6b9 JG |
48 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
49 | { | |
50 | struct radeon_mman *mman; | |
51 | struct radeon_device *rdev; | |
52 | ||
53 | mman = container_of(bdev, struct radeon_mman, bdev); | |
54 | rdev = container_of(mman, struct radeon_device, mman); | |
55 | return rdev; | |
56 | } | |
57 | ||
58 | ||
59 | /* | |
60 | * Global memory. | |
61 | */ | |
ba4420c2 | 62 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
771fe6b9 JG |
63 | { |
64 | return ttm_mem_global_init(ref->object); | |
65 | } | |
66 | ||
ba4420c2 | 67 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
771fe6b9 JG |
68 | { |
69 | ttm_mem_global_release(ref->object); | |
70 | } | |
71 | ||
72 | static int radeon_ttm_global_init(struct radeon_device *rdev) | |
73 | { | |
ba4420c2 | 74 | struct drm_global_reference *global_ref; |
771fe6b9 JG |
75 | int r; |
76 | ||
77 | rdev->mman.mem_global_referenced = false; | |
78 | global_ref = &rdev->mman.mem_global_ref; | |
ba4420c2 | 79 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
771fe6b9 JG |
80 | global_ref->size = sizeof(struct ttm_mem_global); |
81 | global_ref->init = &radeon_ttm_mem_global_init; | |
82 | global_ref->release = &radeon_ttm_mem_global_release; | |
ba4420c2 | 83 | r = drm_global_item_ref(global_ref); |
771fe6b9 | 84 | if (r != 0) { |
a987fcaa TH |
85 | DRM_ERROR("Failed setting up TTM memory accounting " |
86 | "subsystem.\n"); | |
771fe6b9 JG |
87 | return r; |
88 | } | |
a987fcaa TH |
89 | |
90 | rdev->mman.bo_global_ref.mem_glob = | |
91 | rdev->mman.mem_global_ref.object; | |
92 | global_ref = &rdev->mman.bo_global_ref.ref; | |
ba4420c2 | 93 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
7f5f4db2 | 94 | global_ref->size = sizeof(struct ttm_bo_global); |
a987fcaa TH |
95 | global_ref->init = &ttm_bo_global_init; |
96 | global_ref->release = &ttm_bo_global_release; | |
ba4420c2 | 97 | r = drm_global_item_ref(global_ref); |
a987fcaa TH |
98 | if (r != 0) { |
99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | |
ba4420c2 | 100 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
a987fcaa TH |
101 | return r; |
102 | } | |
103 | ||
771fe6b9 JG |
104 | rdev->mman.mem_global_referenced = true; |
105 | return 0; | |
106 | } | |
107 | ||
108 | static void radeon_ttm_global_fini(struct radeon_device *rdev) | |
109 | { | |
110 | if (rdev->mman.mem_global_referenced) { | |
ba4420c2 DA |
111 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
112 | drm_global_item_unref(&rdev->mman.mem_global_ref); | |
771fe6b9 JG |
113 | rdev->mman.mem_global_referenced = false; |
114 | } | |
115 | } | |
116 | ||
771fe6b9 JG |
117 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
118 | { | |
119 | return 0; | |
120 | } | |
121 | ||
122 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
123 | struct ttm_mem_type_manager *man) | |
124 | { | |
125 | struct radeon_device *rdev; | |
126 | ||
127 | rdev = radeon_get_rdev(bdev); | |
128 | ||
129 | switch (type) { | |
130 | case TTM_PL_SYSTEM: | |
131 | /* System memory */ | |
132 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
133 | man->available_caching = TTM_PL_MASK_CACHING; | |
134 | man->default_caching = TTM_PL_FLAG_CACHED; | |
135 | break; | |
136 | case TTM_PL_TT: | |
d961db75 | 137 | man->func = &ttm_bo_manager_func; |
d594e46a | 138 | man->gpu_offset = rdev->mc.gtt_start; |
771fe6b9 JG |
139 | man->available_caching = TTM_PL_MASK_CACHING; |
140 | man->default_caching = TTM_PL_FLAG_CACHED; | |
55c93278 | 141 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
771fe6b9 JG |
142 | #if __OS_HAS_AGP |
143 | if (rdev->flags & RADEON_IS_AGP) { | |
144 | if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { | |
145 | DRM_ERROR("AGP is not enabled for memory type %u\n", | |
146 | (unsigned)type); | |
147 | return -EINVAL; | |
148 | } | |
55c93278 | 149 | if (!rdev->ddev->agp->cant_use_aperture) |
0a2d50e3 | 150 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
771fe6b9 JG |
151 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
152 | TTM_PL_FLAG_WC; | |
153 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 | 154 | } |
0c321c79 | 155 | #endif |
771fe6b9 JG |
156 | break; |
157 | case TTM_PL_VRAM: | |
158 | /* "On-card" video ram */ | |
d961db75 | 159 | man->func = &ttm_bo_manager_func; |
d594e46a | 160 | man->gpu_offset = rdev->mc.vram_start; |
771fe6b9 | 161 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
771fe6b9 JG |
162 | TTM_MEMTYPE_FLAG_MAPPABLE; |
163 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
164 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 JG |
165 | break; |
166 | default: | |
167 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
168 | return -EINVAL; | |
169 | } | |
170 | return 0; | |
171 | } | |
172 | ||
312ea8da JG |
173 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
174 | struct ttm_placement *placement) | |
771fe6b9 | 175 | { |
d03d8589 JG |
176 | struct radeon_bo *rbo; |
177 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
178 | ||
179 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
180 | placement->fpfn = 0; | |
181 | placement->lpfn = 0; | |
182 | placement->placement = &placements; | |
183 | placement->busy_placement = &placements; | |
184 | placement->num_placement = 1; | |
185 | placement->num_busy_placement = 1; | |
186 | return; | |
187 | } | |
188 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 189 | switch (bo->mem.mem_type) { |
312ea8da | 190 | case TTM_PL_VRAM: |
e32eb50d | 191 | if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) |
9270eb1b DA |
192 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
193 | else | |
194 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
312ea8da JG |
195 | break; |
196 | case TTM_PL_TT: | |
771fe6b9 | 197 | default: |
312ea8da | 198 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 199 | } |
eaa5fd1a | 200 | *placement = rbo->placement; |
771fe6b9 JG |
201 | } |
202 | ||
203 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
209 | struct ttm_mem_reg *new_mem) | |
210 | { | |
211 | struct ttm_mem_reg *old_mem = &bo->mem; | |
212 | ||
213 | BUG_ON(old_mem->mm_node != NULL); | |
214 | *old_mem = *new_mem; | |
215 | new_mem->mm_node = NULL; | |
216 | } | |
217 | ||
218 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
219 | bool evict, int no_wait_reserve, bool no_wait_gpu, |
220 | struct ttm_mem_reg *new_mem, | |
221 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
222 | { |
223 | struct radeon_device *rdev; | |
224 | uint64_t old_start, new_start; | |
225 | struct radeon_fence *fence; | |
3000bf39 | 226 | int r, i; |
771fe6b9 JG |
227 | |
228 | rdev = radeon_get_rdev(bo->bdev); | |
3000bf39 | 229 | r = radeon_fence_create(rdev, &fence, rdev->copy_ring); |
771fe6b9 JG |
230 | if (unlikely(r)) { |
231 | return r; | |
232 | } | |
d961db75 BS |
233 | old_start = old_mem->start << PAGE_SHIFT; |
234 | new_start = new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
235 | |
236 | switch (old_mem->mem_type) { | |
237 | case TTM_PL_VRAM: | |
d594e46a | 238 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
239 | break; |
240 | case TTM_PL_TT: | |
d594e46a | 241 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
242 | break; |
243 | default: | |
244 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
245 | return -EINVAL; | |
246 | } | |
247 | switch (new_mem->mem_type) { | |
248 | case TTM_PL_VRAM: | |
d594e46a | 249 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
250 | break; |
251 | case TTM_PL_TT: | |
d594e46a | 252 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
253 | break; |
254 | default: | |
255 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
256 | return -EINVAL; | |
257 | } | |
3000bf39 AD |
258 | if (!rdev->ring[rdev->copy_ring].ready) { |
259 | DRM_ERROR("Trying to move memory with ring turned off.\n"); | |
771fe6b9 JG |
260 | return -EINVAL; |
261 | } | |
003cefe0 AD |
262 | |
263 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
264 | ||
3000bf39 AD |
265 | /* sync other rings */ |
266 | if (rdev->family >= CHIP_R600) { | |
267 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | |
268 | /* no need to sync to our own or unused rings */ | |
269 | if (i == rdev->copy_ring || !rdev->ring[i].ready) | |
270 | continue; | |
271 | ||
272 | if (!fence->semaphore) { | |
273 | r = radeon_semaphore_create(rdev, &fence->semaphore); | |
274 | /* FIXME: handle semaphore error */ | |
275 | if (r) | |
276 | continue; | |
277 | } | |
278 | ||
279 | r = radeon_ring_lock(rdev, &rdev->ring[i], 3); | |
280 | /* FIXME: handle ring lock error */ | |
281 | if (r) | |
282 | continue; | |
283 | radeon_semaphore_emit_signal(rdev, i, fence->semaphore); | |
284 | radeon_ring_unlock_commit(rdev, &rdev->ring[i]); | |
285 | ||
286 | r = radeon_ring_lock(rdev, &rdev->ring[rdev->copy_ring], 3); | |
287 | /* FIXME: handle ring lock error */ | |
288 | if (r) | |
289 | continue; | |
290 | radeon_semaphore_emit_wait(rdev, rdev->copy_ring, fence->semaphore); | |
291 | radeon_ring_unlock_commit(rdev, &rdev->ring[rdev->copy_ring]); | |
292 | } | |
293 | } | |
294 | ||
003cefe0 AD |
295 | r = radeon_copy(rdev, old_start, new_start, |
296 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ | |
297 | fence); | |
771fe6b9 JG |
298 | /* FIXME: handle copy error */ |
299 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL, | |
9d87fa21 | 300 | evict, no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 JG |
301 | radeon_fence_unref(&fence); |
302 | return r; | |
303 | } | |
304 | ||
305 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
306 | bool evict, bool interruptible, |
307 | bool no_wait_reserve, bool no_wait_gpu, | |
771fe6b9 JG |
308 | struct ttm_mem_reg *new_mem) |
309 | { | |
310 | struct radeon_device *rdev; | |
311 | struct ttm_mem_reg *old_mem = &bo->mem; | |
312 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
313 | u32 placements; |
314 | struct ttm_placement placement; | |
771fe6b9 JG |
315 | int r; |
316 | ||
317 | rdev = radeon_get_rdev(bo->bdev); | |
318 | tmp_mem = *new_mem; | |
319 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
320 | placement.fpfn = 0; |
321 | placement.lpfn = 0; | |
322 | placement.num_placement = 1; | |
323 | placement.placement = &placements; | |
324 | placement.num_busy_placement = 1; | |
325 | placement.busy_placement = &placements; | |
326 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
327 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
9d87fa21 | 328 | interruptible, no_wait_reserve, no_wait_gpu); |
771fe6b9 JG |
329 | if (unlikely(r)) { |
330 | return r; | |
331 | } | |
df67bed9 DA |
332 | |
333 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
334 | if (unlikely(r)) { | |
335 | goto out_cleanup; | |
336 | } | |
337 | ||
771fe6b9 JG |
338 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
339 | if (unlikely(r)) { | |
340 | goto out_cleanup; | |
341 | } | |
9d87fa21 | 342 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
343 | if (unlikely(r)) { |
344 | goto out_cleanup; | |
345 | } | |
9d87fa21 | 346 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 | 347 | out_cleanup: |
42311ff9 | 348 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
349 | return r; |
350 | } | |
351 | ||
352 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
353 | bool evict, bool interruptible, |
354 | bool no_wait_reserve, bool no_wait_gpu, | |
771fe6b9 JG |
355 | struct ttm_mem_reg *new_mem) |
356 | { | |
357 | struct radeon_device *rdev; | |
358 | struct ttm_mem_reg *old_mem = &bo->mem; | |
359 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
360 | struct ttm_placement placement; |
361 | u32 placements; | |
771fe6b9 JG |
362 | int r; |
363 | ||
364 | rdev = radeon_get_rdev(bo->bdev); | |
365 | tmp_mem = *new_mem; | |
366 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
367 | placement.fpfn = 0; |
368 | placement.lpfn = 0; | |
369 | placement.num_placement = 1; | |
370 | placement.placement = &placements; | |
371 | placement.num_busy_placement = 1; | |
372 | placement.busy_placement = &placements; | |
373 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
9d87fa21 | 374 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu); |
771fe6b9 JG |
375 | if (unlikely(r)) { |
376 | return r; | |
377 | } | |
9d87fa21 | 378 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem); |
771fe6b9 JG |
379 | if (unlikely(r)) { |
380 | goto out_cleanup; | |
381 | } | |
9d87fa21 | 382 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
383 | if (unlikely(r)) { |
384 | goto out_cleanup; | |
385 | } | |
386 | out_cleanup: | |
42311ff9 | 387 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
388 | return r; |
389 | } | |
390 | ||
391 | static int radeon_bo_move(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
392 | bool evict, bool interruptible, |
393 | bool no_wait_reserve, bool no_wait_gpu, | |
394 | struct ttm_mem_reg *new_mem) | |
771fe6b9 JG |
395 | { |
396 | struct radeon_device *rdev; | |
397 | struct ttm_mem_reg *old_mem = &bo->mem; | |
398 | int r; | |
399 | ||
400 | rdev = radeon_get_rdev(bo->bdev); | |
401 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
402 | radeon_move_null(bo, new_mem); | |
403 | return 0; | |
404 | } | |
405 | if ((old_mem->mem_type == TTM_PL_TT && | |
406 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
407 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
408 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 409 | /* bind is enough */ |
771fe6b9 JG |
410 | radeon_move_null(bo, new_mem); |
411 | return 0; | |
412 | } | |
e32eb50d | 413 | if (!rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready || rdev->asic->copy == NULL) { |
771fe6b9 | 414 | /* use memcpy */ |
1ab2e105 | 415 | goto memcpy; |
771fe6b9 JG |
416 | } |
417 | ||
418 | if (old_mem->mem_type == TTM_PL_VRAM && | |
419 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
1ab2e105 | 420 | r = radeon_move_vram_ram(bo, evict, interruptible, |
9d87fa21 | 421 | no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 JG |
422 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
423 | new_mem->mem_type == TTM_PL_VRAM) { | |
1ab2e105 | 424 | r = radeon_move_ram_vram(bo, evict, interruptible, |
9d87fa21 | 425 | no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 | 426 | } else { |
9d87fa21 | 427 | r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
771fe6b9 | 428 | } |
1ab2e105 MD |
429 | |
430 | if (r) { | |
431 | memcpy: | |
9d87fa21 | 432 | r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
1ab2e105 | 433 | } |
771fe6b9 JG |
434 | return r; |
435 | } | |
436 | ||
0a2d50e3 JG |
437 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
438 | { | |
439 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
440 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
441 | ||
442 | mem->bus.addr = NULL; | |
443 | mem->bus.offset = 0; | |
444 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
445 | mem->bus.base = 0; | |
446 | mem->bus.is_iomem = false; | |
447 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
448 | return -EINVAL; | |
449 | switch (mem->mem_type) { | |
450 | case TTM_PL_SYSTEM: | |
451 | /* system memory */ | |
452 | return 0; | |
453 | case TTM_PL_TT: | |
454 | #if __OS_HAS_AGP | |
455 | if (rdev->flags & RADEON_IS_AGP) { | |
456 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 457 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 458 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 459 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
460 | } |
461 | #endif | |
462 | break; | |
463 | case TTM_PL_VRAM: | |
d961db75 | 464 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
465 | /* check if it's visible */ |
466 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
467 | return -EINVAL; | |
468 | mem->bus.base = rdev->mc.aper_base; | |
469 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
470 | #ifdef __alpha__ |
471 | /* | |
472 | * Alpha: use bus.addr to hold the ioremap() return, | |
473 | * so we can modify bus.base below. | |
474 | */ | |
475 | if (mem->placement & TTM_PL_FLAG_WC) | |
476 | mem->bus.addr = | |
477 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
478 | mem->bus.size); | |
479 | else | |
480 | mem->bus.addr = | |
481 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
482 | mem->bus.size); | |
483 | ||
484 | /* | |
485 | * Alpha: Use just the bus offset plus | |
486 | * the hose/domain memory base for bus.base. | |
487 | * It then can be used to build PTEs for VRAM | |
488 | * access, as done in ttm_bo_vm_fault(). | |
489 | */ | |
490 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
491 | rdev->ddev->hose->dense_mem_base; | |
492 | #endif | |
0a2d50e3 JG |
493 | break; |
494 | default: | |
495 | return -EINVAL; | |
496 | } | |
497 | return 0; | |
498 | } | |
499 | ||
500 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
501 | { | |
502 | } | |
503 | ||
771fe6b9 JG |
504 | static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg, |
505 | bool lazy, bool interruptible) | |
506 | { | |
507 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); | |
508 | } | |
509 | ||
510 | static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg) | |
511 | { | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static void radeon_sync_obj_unref(void **sync_obj) | |
516 | { | |
517 | radeon_fence_unref((struct radeon_fence **)sync_obj); | |
518 | } | |
519 | ||
520 | static void *radeon_sync_obj_ref(void *sync_obj) | |
521 | { | |
522 | return radeon_fence_ref((struct radeon_fence *)sync_obj); | |
523 | } | |
524 | ||
525 | static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg) | |
526 | { | |
527 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); | |
528 | } | |
529 | ||
649bf3ca JG |
530 | /* |
531 | * TTM backend functions. | |
532 | */ | |
533 | struct radeon_ttm_tt { | |
8e7e7052 | 534 | struct ttm_dma_tt ttm; |
649bf3ca JG |
535 | struct radeon_device *rdev; |
536 | u64 offset; | |
537 | }; | |
538 | ||
539 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, | |
540 | struct ttm_mem_reg *bo_mem) | |
541 | { | |
8e7e7052 | 542 | struct radeon_ttm_tt *gtt = (void*)ttm; |
649bf3ca JG |
543 | int r; |
544 | ||
649bf3ca JG |
545 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
546 | if (!ttm->num_pages) { | |
547 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
548 | ttm->num_pages, bo_mem, ttm); | |
549 | } | |
550 | r = radeon_gart_bind(gtt->rdev, gtt->offset, | |
8e7e7052 | 551 | ttm->num_pages, ttm->pages, gtt->ttm.dma_address); |
649bf3ca JG |
552 | if (r) { |
553 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
554 | ttm->num_pages, (unsigned)gtt->offset); | |
555 | return r; | |
556 | } | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
561 | { | |
8e7e7052 | 562 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 563 | |
649bf3ca JG |
564 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
565 | return 0; | |
566 | } | |
567 | ||
568 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
569 | { | |
8e7e7052 | 570 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 571 | |
8e7e7052 | 572 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
573 | kfree(gtt); |
574 | } | |
575 | ||
576 | static struct ttm_backend_func radeon_backend_func = { | |
577 | .bind = &radeon_ttm_backend_bind, | |
578 | .unbind = &radeon_ttm_backend_unbind, | |
579 | .destroy = &radeon_ttm_backend_destroy, | |
580 | }; | |
581 | ||
582 | struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, | |
583 | unsigned long size, uint32_t page_flags, | |
584 | struct page *dummy_read_page) | |
585 | { | |
586 | struct radeon_device *rdev; | |
587 | struct radeon_ttm_tt *gtt; | |
588 | ||
589 | rdev = radeon_get_rdev(bdev); | |
590 | #if __OS_HAS_AGP | |
591 | if (rdev->flags & RADEON_IS_AGP) { | |
592 | return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, | |
593 | size, page_flags, dummy_read_page); | |
594 | } | |
595 | #endif | |
596 | ||
597 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
598 | if (gtt == NULL) { | |
599 | return NULL; | |
600 | } | |
8e7e7052 | 601 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 602 | gtt->rdev = rdev; |
8e7e7052 JG |
603 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { |
604 | kfree(gtt); | |
649bf3ca JG |
605 | return NULL; |
606 | } | |
8e7e7052 | 607 | return >t->ttm.ttm; |
649bf3ca JG |
608 | } |
609 | ||
c52494f6 KRW |
610 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm) |
611 | { | |
612 | struct radeon_device *rdev; | |
8e7e7052 | 613 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 KRW |
614 | unsigned i; |
615 | int r; | |
616 | ||
617 | if (ttm->state != tt_unpopulated) | |
618 | return 0; | |
619 | ||
620 | rdev = radeon_get_rdev(ttm->bdev); | |
621 | ||
622 | #ifdef CONFIG_SWIOTLB | |
623 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 624 | return ttm_dma_populate(>t->ttm, rdev->dev); |
c52494f6 KRW |
625 | } |
626 | #endif | |
627 | ||
628 | r = ttm_pool_populate(ttm); | |
629 | if (r) { | |
630 | return r; | |
631 | } | |
632 | ||
633 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
634 | gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], |
635 | 0, PAGE_SIZE, | |
636 | PCI_DMA_BIDIRECTIONAL); | |
637 | if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { | |
c52494f6 | 638 | while (--i) { |
8e7e7052 | 639 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
c52494f6 | 640 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
8e7e7052 | 641 | gtt->ttm.dma_address[i] = 0; |
c52494f6 KRW |
642 | } |
643 | ttm_pool_unpopulate(ttm); | |
644 | return -EFAULT; | |
645 | } | |
646 | } | |
647 | return 0; | |
648 | } | |
649 | ||
650 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
651 | { | |
652 | struct radeon_device *rdev; | |
8e7e7052 | 653 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 KRW |
654 | unsigned i; |
655 | ||
656 | rdev = radeon_get_rdev(ttm->bdev); | |
657 | ||
658 | #ifdef CONFIG_SWIOTLB | |
659 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 660 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
661 | return; |
662 | } | |
663 | #endif | |
664 | ||
665 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
666 | if (gtt->ttm.dma_address[i]) { |
667 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], | |
c52494f6 KRW |
668 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
669 | } | |
670 | } | |
671 | ||
672 | ttm_pool_unpopulate(ttm); | |
673 | } | |
649bf3ca | 674 | |
771fe6b9 | 675 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 676 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
677 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
678 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
771fe6b9 JG |
679 | .invalidate_caches = &radeon_invalidate_caches, |
680 | .init_mem_type = &radeon_init_mem_type, | |
681 | .evict_flags = &radeon_evict_flags, | |
682 | .move = &radeon_bo_move, | |
683 | .verify_access = &radeon_verify_access, | |
684 | .sync_obj_signaled = &radeon_sync_obj_signaled, | |
685 | .sync_obj_wait = &radeon_sync_obj_wait, | |
686 | .sync_obj_flush = &radeon_sync_obj_flush, | |
687 | .sync_obj_unref = &radeon_sync_obj_unref, | |
688 | .sync_obj_ref = &radeon_sync_obj_ref, | |
e024e110 DA |
689 | .move_notify = &radeon_bo_move_notify, |
690 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 JG |
691 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
692 | .io_mem_free = &radeon_ttm_io_mem_free, | |
771fe6b9 JG |
693 | }; |
694 | ||
695 | int radeon_ttm_init(struct radeon_device *rdev) | |
696 | { | |
697 | int r; | |
698 | ||
699 | r = radeon_ttm_global_init(rdev); | |
700 | if (r) { | |
701 | return r; | |
702 | } | |
703 | /* No others user of address space so set it to 0 */ | |
704 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
a987fcaa | 705 | rdev->mman.bo_global_ref.ref.object, |
ad49f501 DA |
706 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
707 | rdev->need_dma32); | |
771fe6b9 JG |
708 | if (r) { |
709 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
710 | return r; | |
711 | } | |
0a0c7596 | 712 | rdev->mman.initialized = true; |
4c788679 | 713 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
312ea8da | 714 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
771fe6b9 JG |
715 | if (r) { |
716 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
717 | return r; | |
718 | } | |
441921d5 | 719 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
4c788679 JG |
720 | RADEON_GEM_DOMAIN_VRAM, |
721 | &rdev->stollen_vga_memory); | |
771fe6b9 JG |
722 | if (r) { |
723 | return r; | |
724 | } | |
4c788679 JG |
725 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
726 | if (r) | |
727 | return r; | |
728 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); | |
729 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
771fe6b9 | 730 | if (r) { |
4c788679 | 731 | radeon_bo_unref(&rdev->stollen_vga_memory); |
771fe6b9 JG |
732 | return r; |
733 | } | |
734 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
3ce0a23d | 735 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); |
4c788679 | 736 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
312ea8da | 737 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
738 | if (r) { |
739 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
740 | return r; | |
741 | } | |
742 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 743 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
771fe6b9 JG |
744 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
745 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
746 | } | |
fa8a1238 DA |
747 | |
748 | r = radeon_ttm_debugfs_init(rdev); | |
749 | if (r) { | |
750 | DRM_ERROR("Failed to init debugfs\n"); | |
751 | return r; | |
752 | } | |
771fe6b9 JG |
753 | return 0; |
754 | } | |
755 | ||
756 | void radeon_ttm_fini(struct radeon_device *rdev) | |
757 | { | |
4c788679 JG |
758 | int r; |
759 | ||
0a0c7596 JG |
760 | if (!rdev->mman.initialized) |
761 | return; | |
771fe6b9 | 762 | if (rdev->stollen_vga_memory) { |
4c788679 JG |
763 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
764 | if (r == 0) { | |
765 | radeon_bo_unpin(rdev->stollen_vga_memory); | |
766 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
767 | } | |
768 | radeon_bo_unref(&rdev->stollen_vga_memory); | |
771fe6b9 JG |
769 | } |
770 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
771 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
772 | ttm_bo_device_release(&rdev->mman.bdev); | |
773 | radeon_gart_fini(rdev); | |
774 | radeon_ttm_global_fini(rdev); | |
0a0c7596 | 775 | rdev->mman.initialized = false; |
771fe6b9 JG |
776 | DRM_INFO("radeon: ttm finalized\n"); |
777 | } | |
778 | ||
53595338 DA |
779 | /* this should only be called at bootup or when userspace |
780 | * isn't running */ | |
781 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
782 | { | |
783 | struct ttm_mem_type_manager *man; | |
784 | ||
785 | if (!rdev->mman.initialized) | |
786 | return; | |
787 | ||
788 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
789 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
790 | man->size = size >> PAGE_SHIFT; | |
791 | } | |
792 | ||
771fe6b9 | 793 | static struct vm_operations_struct radeon_ttm_vm_ops; |
f0f37e2f | 794 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
771fe6b9 JG |
795 | |
796 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
797 | { | |
798 | struct ttm_buffer_object *bo; | |
5876dd24 | 799 | struct radeon_device *rdev; |
771fe6b9 JG |
800 | int r; |
801 | ||
5876dd24 | 802 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
771fe6b9 JG |
803 | if (bo == NULL) { |
804 | return VM_FAULT_NOPAGE; | |
805 | } | |
5876dd24 MG |
806 | rdev = radeon_get_rdev(bo->bdev); |
807 | mutex_lock(&rdev->vram_mutex); | |
771fe6b9 | 808 | r = ttm_vm_ops->fault(vma, vmf); |
5876dd24 | 809 | mutex_unlock(&rdev->vram_mutex); |
771fe6b9 JG |
810 | return r; |
811 | } | |
812 | ||
813 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) | |
814 | { | |
815 | struct drm_file *file_priv; | |
816 | struct radeon_device *rdev; | |
817 | int r; | |
818 | ||
819 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { | |
820 | return drm_mmap(filp, vma); | |
821 | } | |
822 | ||
40b3be3f | 823 | file_priv = filp->private_data; |
771fe6b9 JG |
824 | rdev = file_priv->minor->dev->dev_private; |
825 | if (rdev == NULL) { | |
826 | return -EINVAL; | |
827 | } | |
828 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); | |
829 | if (unlikely(r != 0)) { | |
830 | return r; | |
831 | } | |
832 | if (unlikely(ttm_vm_ops == NULL)) { | |
833 | ttm_vm_ops = vma->vm_ops; | |
834 | radeon_ttm_vm_ops = *ttm_vm_ops; | |
835 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; | |
836 | } | |
837 | vma->vm_ops = &radeon_ttm_vm_ops; | |
838 | return 0; | |
839 | } | |
840 | ||
841 | ||
fa8a1238 DA |
842 | #define RADEON_DEBUGFS_MEM_TYPES 2 |
843 | ||
fa8a1238 DA |
844 | #if defined(CONFIG_DEBUG_FS) |
845 | static int radeon_mm_dump_table(struct seq_file *m, void *data) | |
846 | { | |
847 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
848 | struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; | |
849 | struct drm_device *dev = node->minor->dev; | |
850 | struct radeon_device *rdev = dev->dev_private; | |
851 | int ret; | |
852 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; | |
853 | ||
854 | spin_lock(&glob->lru_lock); | |
855 | ret = drm_mm_dump_table(m, mm); | |
856 | spin_unlock(&glob->lru_lock); | |
857 | return ret; | |
858 | } | |
859 | #endif | |
860 | ||
861 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
862 | { | |
f4e45d02 | 863 | #if defined(CONFIG_DEBUG_FS) |
c52494f6 KRW |
864 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; |
865 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; | |
fa8a1238 DA |
866 | unsigned i; |
867 | ||
fa8a1238 DA |
868 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { |
869 | if (i == 0) | |
870 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); | |
871 | else | |
872 | sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); | |
873 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
874 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; | |
875 | radeon_mem_types_list[i].driver_features = 0; | |
876 | if (i == 0) | |
16f9fdcb | 877 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; |
fa8a1238 | 878 | else |
16f9fdcb | 879 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; |
fa8a1238 DA |
880 | |
881 | } | |
8d7cddcd PN |
882 | /* Add ttm page pool to debugfs */ |
883 | sprintf(radeon_mem_types_names[i], "ttm_page_pool"); | |
884 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
885 | radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; | |
886 | radeon_mem_types_list[i].driver_features = 0; | |
c52494f6 KRW |
887 | radeon_mem_types_list[i++].data = NULL; |
888 | #ifdef CONFIG_SWIOTLB | |
889 | if (swiotlb_nr_tbl()) { | |
890 | sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); | |
891 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
892 | radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; | |
893 | radeon_mem_types_list[i].driver_features = 0; | |
894 | radeon_mem_types_list[i++].data = NULL; | |
895 | } | |
896 | #endif | |
897 | return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); | |
fa8a1238 DA |
898 | |
899 | #endif | |
900 | return 0; | |
901 | } |