Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <ttm/ttm_bo_api.h> | |
33 | #include <ttm/ttm_bo_driver.h> | |
34 | #include <ttm/ttm_placement.h> | |
35 | #include <ttm/ttm_module.h> | |
8d7cddcd | 36 | #include <ttm/ttm_page_alloc.h> |
771fe6b9 JG |
37 | #include <drm/drmP.h> |
38 | #include <drm/radeon_drm.h> | |
fa8a1238 | 39 | #include <linux/seq_file.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
4cfe7629 | 41 | #include <linux/swiotlb.h> |
f72a113a CK |
42 | #include <linux/swap.h> |
43 | #include <linux/pagemap.h> | |
2014b569 | 44 | #include <linux/debugfs.h> |
771fe6b9 JG |
45 | #include "radeon_reg.h" |
46 | #include "radeon.h" | |
47 | ||
48 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
49 | ||
fa8a1238 | 50 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
2014b569 | 51 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); |
fa8a1238 | 52 | |
771fe6b9 JG |
53 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
54 | { | |
55 | struct radeon_mman *mman; | |
56 | struct radeon_device *rdev; | |
57 | ||
58 | mman = container_of(bdev, struct radeon_mman, bdev); | |
59 | rdev = container_of(mman, struct radeon_device, mman); | |
60 | return rdev; | |
61 | } | |
62 | ||
63 | ||
64 | /* | |
65 | * Global memory. | |
66 | */ | |
ba4420c2 | 67 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
771fe6b9 JG |
68 | { |
69 | return ttm_mem_global_init(ref->object); | |
70 | } | |
71 | ||
ba4420c2 | 72 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
771fe6b9 JG |
73 | { |
74 | ttm_mem_global_release(ref->object); | |
75 | } | |
76 | ||
77 | static int radeon_ttm_global_init(struct radeon_device *rdev) | |
78 | { | |
ba4420c2 | 79 | struct drm_global_reference *global_ref; |
771fe6b9 JG |
80 | int r; |
81 | ||
82 | rdev->mman.mem_global_referenced = false; | |
83 | global_ref = &rdev->mman.mem_global_ref; | |
ba4420c2 | 84 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
771fe6b9 JG |
85 | global_ref->size = sizeof(struct ttm_mem_global); |
86 | global_ref->init = &radeon_ttm_mem_global_init; | |
87 | global_ref->release = &radeon_ttm_mem_global_release; | |
ba4420c2 | 88 | r = drm_global_item_ref(global_ref); |
771fe6b9 | 89 | if (r != 0) { |
a987fcaa TH |
90 | DRM_ERROR("Failed setting up TTM memory accounting " |
91 | "subsystem.\n"); | |
771fe6b9 JG |
92 | return r; |
93 | } | |
a987fcaa TH |
94 | |
95 | rdev->mman.bo_global_ref.mem_glob = | |
96 | rdev->mman.mem_global_ref.object; | |
97 | global_ref = &rdev->mman.bo_global_ref.ref; | |
ba4420c2 | 98 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
7f5f4db2 | 99 | global_ref->size = sizeof(struct ttm_bo_global); |
a987fcaa TH |
100 | global_ref->init = &ttm_bo_global_init; |
101 | global_ref->release = &ttm_bo_global_release; | |
ba4420c2 | 102 | r = drm_global_item_ref(global_ref); |
a987fcaa TH |
103 | if (r != 0) { |
104 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | |
ba4420c2 | 105 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
a987fcaa TH |
106 | return r; |
107 | } | |
108 | ||
771fe6b9 JG |
109 | rdev->mman.mem_global_referenced = true; |
110 | return 0; | |
111 | } | |
112 | ||
113 | static void radeon_ttm_global_fini(struct radeon_device *rdev) | |
114 | { | |
115 | if (rdev->mman.mem_global_referenced) { | |
ba4420c2 DA |
116 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
117 | drm_global_item_unref(&rdev->mman.mem_global_ref); | |
771fe6b9 JG |
118 | rdev->mman.mem_global_referenced = false; |
119 | } | |
120 | } | |
121 | ||
771fe6b9 JG |
122 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
123 | { | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
128 | struct ttm_mem_type_manager *man) | |
129 | { | |
130 | struct radeon_device *rdev; | |
131 | ||
132 | rdev = radeon_get_rdev(bdev); | |
133 | ||
134 | switch (type) { | |
135 | case TTM_PL_SYSTEM: | |
136 | /* System memory */ | |
137 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
138 | man->available_caching = TTM_PL_MASK_CACHING; | |
139 | man->default_caching = TTM_PL_FLAG_CACHED; | |
140 | break; | |
141 | case TTM_PL_TT: | |
d961db75 | 142 | man->func = &ttm_bo_manager_func; |
d594e46a | 143 | man->gpu_offset = rdev->mc.gtt_start; |
771fe6b9 JG |
144 | man->available_caching = TTM_PL_MASK_CACHING; |
145 | man->default_caching = TTM_PL_FLAG_CACHED; | |
55c93278 | 146 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
771fe6b9 JG |
147 | #if __OS_HAS_AGP |
148 | if (rdev->flags & RADEON_IS_AGP) { | |
d9906753 | 149 | if (!rdev->ddev->agp) { |
771fe6b9 JG |
150 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
151 | (unsigned)type); | |
152 | return -EINVAL; | |
153 | } | |
55c93278 | 154 | if (!rdev->ddev->agp->cant_use_aperture) |
0a2d50e3 | 155 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
771fe6b9 JG |
156 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
157 | TTM_PL_FLAG_WC; | |
158 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 | 159 | } |
0c321c79 | 160 | #endif |
771fe6b9 JG |
161 | break; |
162 | case TTM_PL_VRAM: | |
163 | /* "On-card" video ram */ | |
d961db75 | 164 | man->func = &ttm_bo_manager_func; |
d594e46a | 165 | man->gpu_offset = rdev->mc.vram_start; |
771fe6b9 | 166 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
771fe6b9 JG |
167 | TTM_MEMTYPE_FLAG_MAPPABLE; |
168 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
169 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 JG |
170 | break; |
171 | default: | |
172 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
173 | return -EINVAL; | |
174 | } | |
175 | return 0; | |
176 | } | |
177 | ||
312ea8da JG |
178 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
179 | struct ttm_placement *placement) | |
771fe6b9 | 180 | { |
d03d8589 JG |
181 | struct radeon_bo *rbo; |
182 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
183 | ||
184 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
185 | placement->fpfn = 0; | |
186 | placement->lpfn = 0; | |
187 | placement->placement = &placements; | |
188 | placement->busy_placement = &placements; | |
189 | placement->num_placement = 1; | |
190 | placement->num_busy_placement = 1; | |
191 | return; | |
192 | } | |
193 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 194 | switch (bo->mem.mem_type) { |
312ea8da | 195 | case TTM_PL_VRAM: |
e32eb50d | 196 | if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) |
9270eb1b DA |
197 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
198 | else | |
199 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
312ea8da JG |
200 | break; |
201 | case TTM_PL_TT: | |
771fe6b9 | 202 | default: |
312ea8da | 203 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 204 | } |
eaa5fd1a | 205 | *placement = rbo->placement; |
771fe6b9 JG |
206 | } |
207 | ||
208 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
209 | { | |
acb46527 DH |
210 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
211 | ||
212 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); | |
771fe6b9 JG |
213 | } |
214 | ||
215 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
216 | struct ttm_mem_reg *new_mem) | |
217 | { | |
218 | struct ttm_mem_reg *old_mem = &bo->mem; | |
219 | ||
220 | BUG_ON(old_mem->mm_node != NULL); | |
221 | *old_mem = *new_mem; | |
222 | new_mem->mm_node = NULL; | |
223 | } | |
224 | ||
225 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
97a875cb | 226 | bool evict, bool no_wait_gpu, |
9d87fa21 JG |
227 | struct ttm_mem_reg *new_mem, |
228 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
229 | { |
230 | struct radeon_device *rdev; | |
231 | uint64_t old_start, new_start; | |
876dc9f3 | 232 | struct radeon_fence *fence; |
876dc9f3 | 233 | int r, ridx; |
771fe6b9 JG |
234 | |
235 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 236 | ridx = radeon_copy_ring_index(rdev); |
d961db75 BS |
237 | old_start = old_mem->start << PAGE_SHIFT; |
238 | new_start = new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
239 | |
240 | switch (old_mem->mem_type) { | |
241 | case TTM_PL_VRAM: | |
d594e46a | 242 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
243 | break; |
244 | case TTM_PL_TT: | |
d594e46a | 245 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
246 | break; |
247 | default: | |
248 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
249 | return -EINVAL; | |
250 | } | |
251 | switch (new_mem->mem_type) { | |
252 | case TTM_PL_VRAM: | |
d594e46a | 253 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
254 | break; |
255 | case TTM_PL_TT: | |
d594e46a | 256 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
257 | break; |
258 | default: | |
259 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
260 | return -EINVAL; | |
261 | } | |
876dc9f3 | 262 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 263 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
264 | return -EINVAL; |
265 | } | |
003cefe0 AD |
266 | |
267 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
268 | ||
3000bf39 | 269 | /* sync other rings */ |
876dc9f3 | 270 | fence = bo->sync_obj; |
003cefe0 AD |
271 | r = radeon_copy(rdev, old_start, new_start, |
272 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ | |
876dc9f3 | 273 | &fence); |
771fe6b9 | 274 | /* FIXME: handle copy error */ |
b03640b1 | 275 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, |
97a875cb | 276 | evict, no_wait_gpu, new_mem); |
771fe6b9 JG |
277 | radeon_fence_unref(&fence); |
278 | return r; | |
279 | } | |
280 | ||
281 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 | 282 | bool evict, bool interruptible, |
97a875cb | 283 | bool no_wait_gpu, |
771fe6b9 JG |
284 | struct ttm_mem_reg *new_mem) |
285 | { | |
286 | struct radeon_device *rdev; | |
287 | struct ttm_mem_reg *old_mem = &bo->mem; | |
288 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
289 | u32 placements; |
290 | struct ttm_placement placement; | |
771fe6b9 JG |
291 | int r; |
292 | ||
293 | rdev = radeon_get_rdev(bo->bdev); | |
294 | tmp_mem = *new_mem; | |
295 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
296 | placement.fpfn = 0; |
297 | placement.lpfn = 0; | |
298 | placement.num_placement = 1; | |
299 | placement.placement = &placements; | |
300 | placement.num_busy_placement = 1; | |
301 | placement.busy_placement = &placements; | |
302 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
303 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
97a875cb | 304 | interruptible, no_wait_gpu); |
771fe6b9 JG |
305 | if (unlikely(r)) { |
306 | return r; | |
307 | } | |
df67bed9 DA |
308 | |
309 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
310 | if (unlikely(r)) { | |
311 | goto out_cleanup; | |
312 | } | |
313 | ||
771fe6b9 JG |
314 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
315 | if (unlikely(r)) { | |
316 | goto out_cleanup; | |
317 | } | |
97a875cb | 318 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
319 | if (unlikely(r)) { |
320 | goto out_cleanup; | |
321 | } | |
97a875cb | 322 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
771fe6b9 | 323 | out_cleanup: |
42311ff9 | 324 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
325 | return r; |
326 | } | |
327 | ||
328 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 | 329 | bool evict, bool interruptible, |
97a875cb | 330 | bool no_wait_gpu, |
771fe6b9 JG |
331 | struct ttm_mem_reg *new_mem) |
332 | { | |
333 | struct radeon_device *rdev; | |
334 | struct ttm_mem_reg *old_mem = &bo->mem; | |
335 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
336 | struct ttm_placement placement; |
337 | u32 placements; | |
771fe6b9 JG |
338 | int r; |
339 | ||
340 | rdev = radeon_get_rdev(bo->bdev); | |
341 | tmp_mem = *new_mem; | |
342 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
343 | placement.fpfn = 0; |
344 | placement.lpfn = 0; | |
345 | placement.num_placement = 1; | |
346 | placement.placement = &placements; | |
347 | placement.num_busy_placement = 1; | |
348 | placement.busy_placement = &placements; | |
349 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
97a875cb ML |
350 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
351 | interruptible, no_wait_gpu); | |
771fe6b9 JG |
352 | if (unlikely(r)) { |
353 | return r; | |
354 | } | |
97a875cb | 355 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
771fe6b9 JG |
356 | if (unlikely(r)) { |
357 | goto out_cleanup; | |
358 | } | |
97a875cb | 359 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
360 | if (unlikely(r)) { |
361 | goto out_cleanup; | |
362 | } | |
363 | out_cleanup: | |
42311ff9 | 364 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
365 | return r; |
366 | } | |
367 | ||
368 | static int radeon_bo_move(struct ttm_buffer_object *bo, | |
9d87fa21 | 369 | bool evict, bool interruptible, |
97a875cb | 370 | bool no_wait_gpu, |
9d87fa21 | 371 | struct ttm_mem_reg *new_mem) |
771fe6b9 JG |
372 | { |
373 | struct radeon_device *rdev; | |
374 | struct ttm_mem_reg *old_mem = &bo->mem; | |
375 | int r; | |
376 | ||
377 | rdev = radeon_get_rdev(bo->bdev); | |
378 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
379 | radeon_move_null(bo, new_mem); | |
380 | return 0; | |
381 | } | |
382 | if ((old_mem->mem_type == TTM_PL_TT && | |
383 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
384 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
385 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 386 | /* bind is enough */ |
771fe6b9 JG |
387 | radeon_move_null(bo, new_mem); |
388 | return 0; | |
389 | } | |
27cd7769 AD |
390 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
391 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 392 | /* use memcpy */ |
1ab2e105 | 393 | goto memcpy; |
771fe6b9 JG |
394 | } |
395 | ||
396 | if (old_mem->mem_type == TTM_PL_VRAM && | |
397 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
1ab2e105 | 398 | r = radeon_move_vram_ram(bo, evict, interruptible, |
97a875cb | 399 | no_wait_gpu, new_mem); |
771fe6b9 JG |
400 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
401 | new_mem->mem_type == TTM_PL_VRAM) { | |
1ab2e105 | 402 | r = radeon_move_ram_vram(bo, evict, interruptible, |
97a875cb | 403 | no_wait_gpu, new_mem); |
771fe6b9 | 404 | } else { |
97a875cb | 405 | r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); |
771fe6b9 | 406 | } |
1ab2e105 MD |
407 | |
408 | if (r) { | |
409 | memcpy: | |
97a875cb | 410 | r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
67e8e3f9 MO |
411 | if (r) { |
412 | return r; | |
413 | } | |
1ab2e105 | 414 | } |
67e8e3f9 MO |
415 | |
416 | /* update statistics */ | |
417 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); | |
418 | return 0; | |
771fe6b9 JG |
419 | } |
420 | ||
0a2d50e3 JG |
421 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
422 | { | |
423 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
424 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
425 | ||
426 | mem->bus.addr = NULL; | |
427 | mem->bus.offset = 0; | |
428 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
429 | mem->bus.base = 0; | |
430 | mem->bus.is_iomem = false; | |
431 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
432 | return -EINVAL; | |
433 | switch (mem->mem_type) { | |
434 | case TTM_PL_SYSTEM: | |
435 | /* system memory */ | |
436 | return 0; | |
437 | case TTM_PL_TT: | |
438 | #if __OS_HAS_AGP | |
439 | if (rdev->flags & RADEON_IS_AGP) { | |
440 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 441 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 442 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 443 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
444 | } |
445 | #endif | |
446 | break; | |
447 | case TTM_PL_VRAM: | |
d961db75 | 448 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
449 | /* check if it's visible */ |
450 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
451 | return -EINVAL; | |
452 | mem->bus.base = rdev->mc.aper_base; | |
453 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
454 | #ifdef __alpha__ |
455 | /* | |
456 | * Alpha: use bus.addr to hold the ioremap() return, | |
457 | * so we can modify bus.base below. | |
458 | */ | |
459 | if (mem->placement & TTM_PL_FLAG_WC) | |
460 | mem->bus.addr = | |
461 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
462 | mem->bus.size); | |
463 | else | |
464 | mem->bus.addr = | |
465 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
466 | mem->bus.size); | |
467 | ||
468 | /* | |
469 | * Alpha: Use just the bus offset plus | |
470 | * the hose/domain memory base for bus.base. | |
471 | * It then can be used to build PTEs for VRAM | |
472 | * access, as done in ttm_bo_vm_fault(). | |
473 | */ | |
474 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
475 | rdev->ddev->hose->dense_mem_base; | |
476 | #endif | |
0a2d50e3 JG |
477 | break; |
478 | default: | |
479 | return -EINVAL; | |
480 | } | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
485 | { | |
486 | } | |
487 | ||
dedfdffd | 488 | static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) |
771fe6b9 JG |
489 | { |
490 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); | |
491 | } | |
492 | ||
dedfdffd | 493 | static int radeon_sync_obj_flush(void *sync_obj) |
771fe6b9 JG |
494 | { |
495 | return 0; | |
496 | } | |
497 | ||
498 | static void radeon_sync_obj_unref(void **sync_obj) | |
499 | { | |
500 | radeon_fence_unref((struct radeon_fence **)sync_obj); | |
501 | } | |
502 | ||
503 | static void *radeon_sync_obj_ref(void *sync_obj) | |
504 | { | |
505 | return radeon_fence_ref((struct radeon_fence *)sync_obj); | |
506 | } | |
507 | ||
dedfdffd | 508 | static bool radeon_sync_obj_signaled(void *sync_obj) |
771fe6b9 JG |
509 | { |
510 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); | |
511 | } | |
512 | ||
649bf3ca JG |
513 | /* |
514 | * TTM backend functions. | |
515 | */ | |
516 | struct radeon_ttm_tt { | |
8e7e7052 | 517 | struct ttm_dma_tt ttm; |
649bf3ca JG |
518 | struct radeon_device *rdev; |
519 | u64 offset; | |
f72a113a CK |
520 | |
521 | uint64_t userptr; | |
522 | struct mm_struct *usermm; | |
523 | uint32_t userflags; | |
649bf3ca JG |
524 | }; |
525 | ||
f72a113a CK |
526 | /* prepare the sg table with the user pages */ |
527 | static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) | |
528 | { | |
529 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
530 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
531 | unsigned pinned = 0, nents; | |
532 | int r; | |
533 | ||
534 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
535 | enum dma_data_direction direction = write ? | |
536 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
537 | ||
538 | if (current->mm != gtt->usermm) | |
539 | return -EPERM; | |
540 | ||
541 | do { | |
542 | unsigned num_pages = ttm->num_pages - pinned; | |
543 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
544 | struct page **pages = ttm->pages + pinned; | |
545 | ||
546 | r = get_user_pages(current, current->mm, userptr, num_pages, | |
547 | write, 0, pages, NULL); | |
548 | if (r < 0) | |
549 | goto release_pages; | |
550 | ||
551 | pinned += r; | |
552 | ||
553 | } while (pinned < ttm->num_pages); | |
554 | ||
555 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, | |
556 | ttm->num_pages << PAGE_SHIFT, | |
557 | GFP_KERNEL); | |
558 | if (r) | |
559 | goto release_sg; | |
560 | ||
561 | r = -ENOMEM; | |
562 | nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
563 | if (nents != ttm->sg->nents) | |
564 | goto release_sg; | |
565 | ||
566 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
567 | gtt->ttm.dma_address, ttm->num_pages); | |
568 | ||
569 | return 0; | |
570 | ||
571 | release_sg: | |
572 | kfree(ttm->sg); | |
573 | ||
574 | release_pages: | |
575 | release_pages(ttm->pages, pinned, 0); | |
576 | return r; | |
577 | } | |
578 | ||
579 | static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) | |
580 | { | |
581 | struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); | |
582 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
583 | struct scatterlist *sg; | |
584 | int i; | |
585 | ||
586 | int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
587 | enum dma_data_direction direction = write ? | |
588 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
589 | ||
590 | /* free the sg table and pages again */ | |
591 | dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
592 | ||
593 | for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) { | |
594 | struct page *page = sg_page(sg); | |
595 | ||
596 | if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) | |
597 | set_page_dirty(page); | |
598 | ||
599 | mark_page_accessed(page); | |
600 | page_cache_release(page); | |
601 | } | |
602 | ||
603 | sg_free_table(ttm->sg); | |
604 | } | |
605 | ||
649bf3ca JG |
606 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, |
607 | struct ttm_mem_reg *bo_mem) | |
608 | { | |
8e7e7052 | 609 | struct radeon_ttm_tt *gtt = (void*)ttm; |
77497f27 MD |
610 | uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | |
611 | RADEON_GART_PAGE_WRITE; | |
649bf3ca JG |
612 | int r; |
613 | ||
f72a113a CK |
614 | if (gtt->userptr) { |
615 | radeon_ttm_tt_pin_userptr(ttm); | |
616 | flags &= ~RADEON_GART_PAGE_WRITE; | |
617 | } | |
618 | ||
649bf3ca JG |
619 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
620 | if (!ttm->num_pages) { | |
621 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
622 | ttm->num_pages, bo_mem, ttm); | |
623 | } | |
77497f27 MD |
624 | if (ttm->caching_state == tt_cached) |
625 | flags |= RADEON_GART_PAGE_SNOOP; | |
626 | r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, | |
627 | ttm->pages, gtt->ttm.dma_address, flags); | |
649bf3ca JG |
628 | if (r) { |
629 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
630 | ttm->num_pages, (unsigned)gtt->offset); | |
631 | return r; | |
632 | } | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
637 | { | |
8e7e7052 | 638 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 639 | |
649bf3ca | 640 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
f72a113a CK |
641 | |
642 | if (gtt->userptr) | |
643 | radeon_ttm_tt_unpin_userptr(ttm); | |
644 | ||
649bf3ca JG |
645 | return 0; |
646 | } | |
647 | ||
648 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
649 | { | |
8e7e7052 | 650 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 651 | |
8e7e7052 | 652 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
653 | kfree(gtt); |
654 | } | |
655 | ||
656 | static struct ttm_backend_func radeon_backend_func = { | |
657 | .bind = &radeon_ttm_backend_bind, | |
658 | .unbind = &radeon_ttm_backend_unbind, | |
659 | .destroy = &radeon_ttm_backend_destroy, | |
660 | }; | |
661 | ||
1109ca09 | 662 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, |
649bf3ca JG |
663 | unsigned long size, uint32_t page_flags, |
664 | struct page *dummy_read_page) | |
665 | { | |
666 | struct radeon_device *rdev; | |
667 | struct radeon_ttm_tt *gtt; | |
668 | ||
669 | rdev = radeon_get_rdev(bdev); | |
670 | #if __OS_HAS_AGP | |
671 | if (rdev->flags & RADEON_IS_AGP) { | |
672 | return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, | |
673 | size, page_flags, dummy_read_page); | |
674 | } | |
675 | #endif | |
676 | ||
677 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
678 | if (gtt == NULL) { | |
679 | return NULL; | |
680 | } | |
8e7e7052 | 681 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 682 | gtt->rdev = rdev; |
8e7e7052 JG |
683 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { |
684 | kfree(gtt); | |
649bf3ca JG |
685 | return NULL; |
686 | } | |
8e7e7052 | 687 | return >t->ttm.ttm; |
649bf3ca JG |
688 | } |
689 | ||
c52494f6 KRW |
690 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm) |
691 | { | |
692 | struct radeon_device *rdev; | |
8e7e7052 | 693 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 KRW |
694 | unsigned i; |
695 | int r; | |
40f5cf99 | 696 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 KRW |
697 | |
698 | if (ttm->state != tt_unpopulated) | |
699 | return 0; | |
700 | ||
f72a113a CK |
701 | if (gtt->userptr) { |
702 | ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL); | |
703 | if (!ttm->sg) | |
704 | return -ENOMEM; | |
705 | ||
706 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
707 | ttm->state = tt_unbound; | |
708 | return 0; | |
709 | } | |
710 | ||
40f5cf99 AD |
711 | if (slave && ttm->sg) { |
712 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
713 | gtt->ttm.dma_address, ttm->num_pages); | |
714 | ttm->state = tt_unbound; | |
715 | return 0; | |
716 | } | |
717 | ||
c52494f6 | 718 | rdev = radeon_get_rdev(ttm->bdev); |
dea7e0ac JG |
719 | #if __OS_HAS_AGP |
720 | if (rdev->flags & RADEON_IS_AGP) { | |
721 | return ttm_agp_tt_populate(ttm); | |
722 | } | |
723 | #endif | |
c52494f6 KRW |
724 | |
725 | #ifdef CONFIG_SWIOTLB | |
726 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 727 | return ttm_dma_populate(>t->ttm, rdev->dev); |
c52494f6 KRW |
728 | } |
729 | #endif | |
730 | ||
731 | r = ttm_pool_populate(ttm); | |
732 | if (r) { | |
733 | return r; | |
734 | } | |
735 | ||
736 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
737 | gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], |
738 | 0, PAGE_SIZE, | |
739 | PCI_DMA_BIDIRECTIONAL); | |
740 | if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { | |
c52494f6 | 741 | while (--i) { |
8e7e7052 | 742 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
c52494f6 | 743 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
8e7e7052 | 744 | gtt->ttm.dma_address[i] = 0; |
c52494f6 KRW |
745 | } |
746 | ttm_pool_unpopulate(ttm); | |
747 | return -EFAULT; | |
748 | } | |
749 | } | |
750 | return 0; | |
751 | } | |
752 | ||
753 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
754 | { | |
755 | struct radeon_device *rdev; | |
8e7e7052 | 756 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 | 757 | unsigned i; |
40f5cf99 AD |
758 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
759 | ||
f72a113a CK |
760 | if (gtt->userptr) { |
761 | kfree(ttm->sg); | |
762 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
763 | return; | |
764 | } | |
765 | ||
40f5cf99 AD |
766 | if (slave) |
767 | return; | |
c52494f6 KRW |
768 | |
769 | rdev = radeon_get_rdev(ttm->bdev); | |
dea7e0ac JG |
770 | #if __OS_HAS_AGP |
771 | if (rdev->flags & RADEON_IS_AGP) { | |
772 | ttm_agp_tt_unpopulate(ttm); | |
773 | return; | |
774 | } | |
775 | #endif | |
c52494f6 KRW |
776 | |
777 | #ifdef CONFIG_SWIOTLB | |
778 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 779 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
780 | return; |
781 | } | |
782 | #endif | |
783 | ||
784 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
785 | if (gtt->ttm.dma_address[i]) { |
786 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], | |
c52494f6 KRW |
787 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
788 | } | |
789 | } | |
790 | ||
791 | ttm_pool_unpopulate(ttm); | |
792 | } | |
649bf3ca | 793 | |
f72a113a CK |
794 | int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
795 | uint32_t flags) | |
796 | { | |
797 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
798 | ||
799 | if (gtt == NULL) | |
800 | return -EINVAL; | |
801 | ||
802 | gtt->userptr = addr; | |
803 | gtt->usermm = current->mm; | |
804 | gtt->userflags = flags; | |
805 | return 0; | |
806 | } | |
807 | ||
808 | bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) | |
809 | { | |
810 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
811 | ||
812 | if (gtt == NULL) | |
813 | return false; | |
814 | ||
815 | return !!gtt->userptr; | |
816 | } | |
817 | ||
818 | bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) | |
819 | { | |
820 | struct radeon_ttm_tt *gtt = (void *)ttm; | |
821 | ||
822 | if (gtt == NULL) | |
823 | return false; | |
824 | ||
825 | return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); | |
826 | } | |
827 | ||
771fe6b9 | 828 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 829 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
830 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
831 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
771fe6b9 JG |
832 | .invalidate_caches = &radeon_invalidate_caches, |
833 | .init_mem_type = &radeon_init_mem_type, | |
834 | .evict_flags = &radeon_evict_flags, | |
835 | .move = &radeon_bo_move, | |
836 | .verify_access = &radeon_verify_access, | |
837 | .sync_obj_signaled = &radeon_sync_obj_signaled, | |
838 | .sync_obj_wait = &radeon_sync_obj_wait, | |
839 | .sync_obj_flush = &radeon_sync_obj_flush, | |
840 | .sync_obj_unref = &radeon_sync_obj_unref, | |
841 | .sync_obj_ref = &radeon_sync_obj_ref, | |
e024e110 DA |
842 | .move_notify = &radeon_bo_move_notify, |
843 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 JG |
844 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
845 | .io_mem_free = &radeon_ttm_io_mem_free, | |
771fe6b9 JG |
846 | }; |
847 | ||
848 | int radeon_ttm_init(struct radeon_device *rdev) | |
849 | { | |
850 | int r; | |
851 | ||
852 | r = radeon_ttm_global_init(rdev); | |
853 | if (r) { | |
854 | return r; | |
855 | } | |
856 | /* No others user of address space so set it to 0 */ | |
857 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
a987fcaa | 858 | rdev->mman.bo_global_ref.ref.object, |
44d847b7 DH |
859 | &radeon_bo_driver, |
860 | rdev->ddev->anon_inode->i_mapping, | |
861 | DRM_FILE_PAGE_OFFSET, | |
ad49f501 | 862 | rdev->need_dma32); |
771fe6b9 JG |
863 | if (r) { |
864 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
865 | return r; | |
866 | } | |
0a0c7596 | 867 | rdev->mman.initialized = true; |
4c788679 | 868 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
312ea8da | 869 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
771fe6b9 JG |
870 | if (r) { |
871 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
872 | return r; | |
873 | } | |
14eedc32 LK |
874 | /* Change the size here instead of the init above so only lpfn is affected */ |
875 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
876 | ||
441921d5 | 877 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
02376d82 | 878 | RADEON_GEM_DOMAIN_VRAM, 0, |
40f5cf99 | 879 | NULL, &rdev->stollen_vga_memory); |
771fe6b9 JG |
880 | if (r) { |
881 | return r; | |
882 | } | |
4c788679 JG |
883 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
884 | if (r) | |
885 | return r; | |
886 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); | |
887 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
771fe6b9 | 888 | if (r) { |
4c788679 | 889 | radeon_bo_unref(&rdev->stollen_vga_memory); |
771fe6b9 JG |
890 | return r; |
891 | } | |
892 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
fc986034 | 893 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
4c788679 | 894 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
312ea8da | 895 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
896 | if (r) { |
897 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
898 | return r; | |
899 | } | |
900 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 901 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
fa8a1238 DA |
902 | |
903 | r = radeon_ttm_debugfs_init(rdev); | |
904 | if (r) { | |
905 | DRM_ERROR("Failed to init debugfs\n"); | |
906 | return r; | |
907 | } | |
771fe6b9 JG |
908 | return 0; |
909 | } | |
910 | ||
911 | void radeon_ttm_fini(struct radeon_device *rdev) | |
912 | { | |
4c788679 JG |
913 | int r; |
914 | ||
0a0c7596 JG |
915 | if (!rdev->mman.initialized) |
916 | return; | |
2014b569 | 917 | radeon_ttm_debugfs_fini(rdev); |
771fe6b9 | 918 | if (rdev->stollen_vga_memory) { |
4c788679 JG |
919 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
920 | if (r == 0) { | |
921 | radeon_bo_unpin(rdev->stollen_vga_memory); | |
922 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
923 | } | |
924 | radeon_bo_unref(&rdev->stollen_vga_memory); | |
771fe6b9 JG |
925 | } |
926 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
927 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
928 | ttm_bo_device_release(&rdev->mman.bdev); | |
929 | radeon_gart_fini(rdev); | |
930 | radeon_ttm_global_fini(rdev); | |
0a0c7596 | 931 | rdev->mman.initialized = false; |
771fe6b9 JG |
932 | DRM_INFO("radeon: ttm finalized\n"); |
933 | } | |
934 | ||
53595338 DA |
935 | /* this should only be called at bootup or when userspace |
936 | * isn't running */ | |
937 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
938 | { | |
939 | struct ttm_mem_type_manager *man; | |
940 | ||
941 | if (!rdev->mman.initialized) | |
942 | return; | |
943 | ||
944 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
945 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
946 | man->size = size >> PAGE_SHIFT; | |
947 | } | |
948 | ||
771fe6b9 | 949 | static struct vm_operations_struct radeon_ttm_vm_ops; |
f0f37e2f | 950 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
771fe6b9 JG |
951 | |
952 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
953 | { | |
954 | struct ttm_buffer_object *bo; | |
5876dd24 | 955 | struct radeon_device *rdev; |
771fe6b9 JG |
956 | int r; |
957 | ||
5876dd24 | 958 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
771fe6b9 JG |
959 | if (bo == NULL) { |
960 | return VM_FAULT_NOPAGE; | |
961 | } | |
5876dd24 | 962 | rdev = radeon_get_rdev(bo->bdev); |
db7fce39 | 963 | down_read(&rdev->pm.mclk_lock); |
771fe6b9 | 964 | r = ttm_vm_ops->fault(vma, vmf); |
db7fce39 | 965 | up_read(&rdev->pm.mclk_lock); |
771fe6b9 JG |
966 | return r; |
967 | } | |
968 | ||
969 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) | |
970 | { | |
971 | struct drm_file *file_priv; | |
972 | struct radeon_device *rdev; | |
973 | int r; | |
974 | ||
975 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { | |
976 | return drm_mmap(filp, vma); | |
977 | } | |
978 | ||
40b3be3f | 979 | file_priv = filp->private_data; |
771fe6b9 JG |
980 | rdev = file_priv->minor->dev->dev_private; |
981 | if (rdev == NULL) { | |
982 | return -EINVAL; | |
983 | } | |
984 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); | |
985 | if (unlikely(r != 0)) { | |
986 | return r; | |
987 | } | |
988 | if (unlikely(ttm_vm_ops == NULL)) { | |
989 | ttm_vm_ops = vma->vm_ops; | |
990 | radeon_ttm_vm_ops = *ttm_vm_ops; | |
991 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; | |
992 | } | |
993 | vma->vm_ops = &radeon_ttm_vm_ops; | |
994 | return 0; | |
995 | } | |
996 | ||
fa8a1238 | 997 | #if defined(CONFIG_DEBUG_FS) |
893d6e6e | 998 | |
fa8a1238 DA |
999 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
1000 | { | |
1001 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
893d6e6e | 1002 | unsigned ttm_pl = *(int *)node->info_ent->data; |
fa8a1238 DA |
1003 | struct drm_device *dev = node->minor->dev; |
1004 | struct radeon_device *rdev = dev->dev_private; | |
893d6e6e | 1005 | struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; |
fa8a1238 DA |
1006 | int ret; |
1007 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; | |
1008 | ||
1009 | spin_lock(&glob->lru_lock); | |
1010 | ret = drm_mm_dump_table(m, mm); | |
1011 | spin_unlock(&glob->lru_lock); | |
1012 | return ret; | |
1013 | } | |
893d6e6e CK |
1014 | |
1015 | static int ttm_pl_vram = TTM_PL_VRAM; | |
1016 | static int ttm_pl_tt = TTM_PL_TT; | |
1017 | ||
1018 | static struct drm_info_list radeon_ttm_debugfs_list[] = { | |
1019 | {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, | |
1020 | {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, | |
1021 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
1022 | #ifdef CONFIG_SWIOTLB | |
1023 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
1024 | #endif | |
1025 | }; | |
1026 | ||
2014b569 CK |
1027 | static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) |
1028 | { | |
1029 | struct radeon_device *rdev = inode->i_private; | |
1030 | i_size_write(inode, rdev->mc.mc_vram_size); | |
1031 | filep->private_data = inode->i_private; | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, | |
1036 | size_t size, loff_t *pos) | |
1037 | { | |
1038 | struct radeon_device *rdev = f->private_data; | |
1039 | ssize_t result = 0; | |
1040 | int r; | |
1041 | ||
1042 | if (size & 0x3 || *pos & 0x3) | |
1043 | return -EINVAL; | |
1044 | ||
1045 | while (size) { | |
1046 | unsigned long flags; | |
1047 | uint32_t value; | |
1048 | ||
1049 | if (*pos >= rdev->mc.mc_vram_size) | |
1050 | return result; | |
1051 | ||
1052 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
1053 | WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
1054 | if (rdev->family >= CHIP_CEDAR) | |
1055 | WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); | |
1056 | value = RREG32(RADEON_MM_DATA); | |
1057 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
1058 | ||
1059 | r = put_user(value, (uint32_t *)buf); | |
1060 | if (r) | |
1061 | return r; | |
1062 | ||
1063 | result += 4; | |
1064 | buf += 4; | |
1065 | *pos += 4; | |
1066 | size -= 4; | |
1067 | } | |
1068 | ||
1069 | return result; | |
1070 | } | |
1071 | ||
1072 | static const struct file_operations radeon_ttm_vram_fops = { | |
1073 | .owner = THIS_MODULE, | |
1074 | .open = radeon_ttm_vram_open, | |
1075 | .read = radeon_ttm_vram_read, | |
1076 | .llseek = default_llseek | |
1077 | }; | |
1078 | ||
dd66d20e CK |
1079 | static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) |
1080 | { | |
1081 | struct radeon_device *rdev = inode->i_private; | |
1082 | i_size_write(inode, rdev->mc.gtt_size); | |
1083 | filep->private_data = inode->i_private; | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |
1088 | size_t size, loff_t *pos) | |
1089 | { | |
1090 | struct radeon_device *rdev = f->private_data; | |
1091 | ssize_t result = 0; | |
1092 | int r; | |
1093 | ||
1094 | while (size) { | |
1095 | loff_t p = *pos / PAGE_SIZE; | |
1096 | unsigned off = *pos & ~PAGE_MASK; | |
0d997b68 | 1097 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
dd66d20e CK |
1098 | struct page *page; |
1099 | void *ptr; | |
1100 | ||
1101 | if (p >= rdev->gart.num_cpu_pages) | |
1102 | return result; | |
1103 | ||
1104 | page = rdev->gart.pages[p]; | |
1105 | if (page) { | |
1106 | ptr = kmap(page); | |
1107 | ptr += off; | |
1108 | ||
1109 | r = copy_to_user(buf, ptr, cur_size); | |
1110 | kunmap(rdev->gart.pages[p]); | |
1111 | } else | |
1112 | r = clear_user(buf, cur_size); | |
1113 | ||
1114 | if (r) | |
1115 | return -EFAULT; | |
1116 | ||
1117 | result += cur_size; | |
1118 | buf += cur_size; | |
1119 | *pos += cur_size; | |
1120 | size -= cur_size; | |
1121 | } | |
1122 | ||
1123 | return result; | |
1124 | } | |
1125 | ||
1126 | static const struct file_operations radeon_ttm_gtt_fops = { | |
1127 | .owner = THIS_MODULE, | |
1128 | .open = radeon_ttm_gtt_open, | |
1129 | .read = radeon_ttm_gtt_read, | |
1130 | .llseek = default_llseek | |
1131 | }; | |
1132 | ||
fa8a1238 DA |
1133 | #endif |
1134 | ||
1135 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
1136 | { | |
f4e45d02 | 1137 | #if defined(CONFIG_DEBUG_FS) |
2014b569 CK |
1138 | unsigned count; |
1139 | ||
1140 | struct drm_minor *minor = rdev->ddev->primary; | |
1141 | struct dentry *ent, *root = minor->debugfs_root; | |
1142 | ||
1143 | ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, | |
1144 | rdev, &radeon_ttm_vram_fops); | |
1145 | if (IS_ERR(ent)) | |
1146 | return PTR_ERR(ent); | |
1147 | rdev->mman.vram = ent; | |
1148 | ||
dd66d20e CK |
1149 | ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, |
1150 | rdev, &radeon_ttm_gtt_fops); | |
1151 | if (IS_ERR(ent)) | |
1152 | return PTR_ERR(ent); | |
1153 | rdev->mman.gtt = ent; | |
1154 | ||
2014b569 | 1155 | count = ARRAY_SIZE(radeon_ttm_debugfs_list); |
fa8a1238 | 1156 | |
c52494f6 | 1157 | #ifdef CONFIG_SWIOTLB |
893d6e6e CK |
1158 | if (!swiotlb_nr_tbl()) |
1159 | --count; | |
c52494f6 | 1160 | #endif |
fa8a1238 | 1161 | |
893d6e6e CK |
1162 | return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); |
1163 | #else | |
1164 | ||
fa8a1238 | 1165 | return 0; |
893d6e6e | 1166 | #endif |
fa8a1238 | 1167 | } |
2014b569 CK |
1168 | |
1169 | static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) | |
1170 | { | |
1171 | #if defined(CONFIG_DEBUG_FS) | |
1172 | ||
1173 | debugfs_remove(rdev->mman.vram); | |
1174 | rdev->mman.vram = NULL; | |
dd66d20e CK |
1175 | |
1176 | debugfs_remove(rdev->mman.gtt); | |
1177 | rdev->mman.gtt = NULL; | |
2014b569 CK |
1178 | #endif |
1179 | } |