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drm/radeon: fix UVD destroy IB size
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_uvd.c
CommitLineData
f2ba57b5
CK		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "radeon.h"
37#include "r600d.h"
38
55b51c88
CK		 39/* 1 second timeout */
40#define UVD_IDLE_TIMEOUT_MS 1000
41
f2ba57b5
CK		 42/* Firmware Names */
43#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
44#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
45#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
46#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
87167bb1 47#define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"
f2ba57b5
CK		 48
49MODULE_FIRMWARE(FIRMWARE_RV710);
50MODULE_FIRMWARE(FIRMWARE_CYPRESS);
51MODULE_FIRMWARE(FIRMWARE_SUMO);
52MODULE_FIRMWARE(FIRMWARE_TAHITI);
87167bb1 53MODULE_FIRMWARE(FIRMWARE_BONAIRE);
f2ba57b5 54
55b51c88
CK		 55static void radeon_uvd_idle_work_handler(struct work_struct *work);
56
f2ba57b5
CK		 57int radeon_uvd_init(struct radeon_device *rdev)
58{
f2ba57b5
CK		 59 unsigned long bo_size;
60 const char *fw_name;
61 int i, r;
62
55b51c88
CK		 63 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
64
f2ba57b5
CK		 65 switch (rdev->family) {
66 case CHIP_RV710:
67 case CHIP_RV730:
68 case CHIP_RV740:
69 fw_name = FIRMWARE_RV710;
70 break;
71
72 case CHIP_CYPRESS:
73 case CHIP_HEMLOCK:
74 case CHIP_JUNIPER:
75 case CHIP_REDWOOD:
76 case CHIP_CEDAR:
77 fw_name = FIRMWARE_CYPRESS;
78 break;
79
80 case CHIP_SUMO:
81 case CHIP_SUMO2:
82 case CHIP_PALM:
83 case CHIP_CAYMAN:
84 case CHIP_BARTS:
85 case CHIP_TURKS:
86 case CHIP_CAICOS:
87 fw_name = FIRMWARE_SUMO;
88 break;
89
90 case CHIP_TAHITI:
91 case CHIP_VERDE:
92 case CHIP_PITCAIRN:
93 case CHIP_ARUBA:
94 fw_name = FIRMWARE_TAHITI;
95 break;
96
87167bb1
CK		 97 case CHIP_BONAIRE:
98 case CHIP_KABINI:
99 case CHIP_KAVERI:
100 fw_name = FIRMWARE_BONAIRE;
101 break;
102
f2ba57b5
CK		 103 default:
104 return -EINVAL;
105 }
106
4ad9c1c7 107 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
f2ba57b5
CK		 108 if (r) {
109 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
110 fw_name);
f2ba57b5
CK		 111 return r;
112 }
113
4ad9c1c7 114 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
f2ba57b5
CK		 115 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
116 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
117 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
118 if (r) {
119 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
120 return r;
121 }
122
9cc2e0e9
CK		 123 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
124 if (r) {
125 radeon_bo_unref(&rdev->uvd.vcpu_bo);
126 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
f2ba57b5 127 return r;
9cc2e0e9 128 }
f2ba57b5 129
9cc2e0e9
CK		 130 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
131 &rdev->uvd.gpu_addr);
132 if (r) {
133 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
134 radeon_bo_unref(&rdev->uvd.vcpu_bo);
135 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
136 return r;
137 }
f2ba57b5 138
9cc2e0e9
CK		 139 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
140 if (r) {
141 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
f2ba57b5 142 return r;
9cc2e0e9
CK		 143 }
144
145 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
146
f2ba57b5
CK		 147 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
148 atomic_set(&rdev->uvd.handles[i], 0);
149 rdev->uvd.filp[i] = NULL;
85a129ca 150 rdev->uvd.img_size[i] = 0;
f2ba57b5
CK		 151 }
152
153 return 0;
154}
155
156void radeon_uvd_fini(struct radeon_device *rdev)
f2ba57b5
CK		 157{
158 int r;
159
160 if (rdev->uvd.vcpu_bo == NULL)
9cc2e0e9 161 return;
f2ba57b5
CK		 162
163 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
164 if (!r) {
165 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
166 radeon_bo_unpin(rdev->uvd.vcpu_bo);
167 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
168 }
9cc2e0e9
CK		 169
170 radeon_bo_unref(&rdev->uvd.vcpu_bo);
4ad9c1c7
CK		 171
172 release_firmware(rdev->uvd_fw);
f2ba57b5
CK		 173}
174
9cc2e0e9 175int radeon_uvd_suspend(struct radeon_device *rdev)
f2ba57b5 176{
9cc2e0e9 177 unsigned size;
4ad9c1c7
CK		 178 void *ptr;
179 int i;
f2ba57b5
CK		 180
181 if (rdev->uvd.vcpu_bo == NULL)
9cc2e0e9 182 return 0;
f2ba57b5 183
4ad9c1c7
CK		 184 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
185 if (atomic_read(&rdev->uvd.handles[i]))
186 break;
187
188 if (i == RADEON_MAX_UVD_HANDLES)
189 return 0;
190
9cc2e0e9 191 size = radeon_bo_size(rdev->uvd.vcpu_bo);
4ad9c1c7
CK		 192 size -= rdev->uvd_fw->size;
193
194 ptr = rdev->uvd.cpu_addr;
195 ptr += rdev->uvd_fw->size;
196
9cc2e0e9 197 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
4ad9c1c7 198 memcpy(rdev->uvd.saved_bo, ptr, size);
f2ba57b5 199
9cc2e0e9
CK		 200 return 0;
201}
089920f2 202
9cc2e0e9
CK		 203int radeon_uvd_resume(struct radeon_device *rdev)
204{
4ad9c1c7
CK		 205 unsigned size;
206 void *ptr;
207
9cc2e0e9
CK		 208 if (rdev->uvd.vcpu_bo == NULL)
209 return -EINVAL;
f2ba57b5 210
4ad9c1c7
CK		 211 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
212
213 size = radeon_bo_size(rdev->uvd.vcpu_bo);
214 size -= rdev->uvd_fw->size;
215
216 ptr = rdev->uvd.cpu_addr;
217 ptr += rdev->uvd_fw->size;
218
9cc2e0e9 219 if (rdev->uvd.saved_bo != NULL) {
4ad9c1c7 220 memcpy(ptr, rdev->uvd.saved_bo, size);
9cc2e0e9
CK		 221 kfree(rdev->uvd.saved_bo);
222 rdev->uvd.saved_bo = NULL;
4ad9c1c7
CK		 223 } else
224 memset(ptr, 0, size);
f2ba57b5 225
f2ba57b5
CK		 226 return 0;
227}
228
229void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
230{
231 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
232 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
233}
234
235void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
236{
237 int i, r;
238 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
641a0059
CK		 239 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
240 if (handle != 0 && rdev->uvd.filp[i] == filp) {
f2ba57b5
CK		 241 struct radeon_fence *fence;
242
c154a763
CK		 243 radeon_uvd_note_usage(rdev);
244
f2ba57b5
CK		 245 r = radeon_uvd_get_destroy_msg(rdev,
246 R600_RING_TYPE_UVD_INDEX, handle, &fence);
247 if (r) {
248 DRM_ERROR("Error destroying UVD (%d)!\n", r);
249 continue;
250 }
251
252 radeon_fence_wait(fence, false);
253 radeon_fence_unref(&fence);
254
255 rdev->uvd.filp[i] = NULL;
256 atomic_set(&rdev->uvd.handles[i], 0);
257 }
258 }
259}
260
261static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
262{
263 unsigned stream_type = msg[4];
264 unsigned width = msg[6];
265 unsigned height = msg[7];
266 unsigned dpb_size = msg[9];
267 unsigned pitch = msg[28];
268
269 unsigned width_in_mb = width / 16;
270 unsigned height_in_mb = ALIGN(height / 16, 2);
271
272 unsigned image_size, tmp, min_dpb_size;
273
274 image_size = width * height;
275 image_size += image_size / 2;
276 image_size = ALIGN(image_size, 1024);
277
278 switch (stream_type) {
279 case 0: /* H264 */
280
281 /* reference picture buffer */
282 min_dpb_size = image_size * 17;
283
284 /* macroblock context buffer */
285 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
286
287 /* IT surface buffer */
288 min_dpb_size += width_in_mb * height_in_mb * 32;
289 break;
290
291 case 1: /* VC1 */
292
293 /* reference picture buffer */
294 min_dpb_size = image_size * 3;
295
296 /* CONTEXT_BUFFER */
297 min_dpb_size += width_in_mb * height_in_mb * 128;
298
299 /* IT surface buffer */
300 min_dpb_size += width_in_mb * 64;
301
302 /* DB surface buffer */
303 min_dpb_size += width_in_mb * 128;
304
305 /* BP */
306 tmp = max(width_in_mb, height_in_mb);
307 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
308 break;
309
310 case 3: /* MPEG2 */
311
312 /* reference picture buffer */
313 min_dpb_size = image_size * 3;
314 break;
315
316 case 4: /* MPEG4 */
317
318 /* reference picture buffer */
319 min_dpb_size = image_size * 3;
320
321 /* CM */
322 min_dpb_size += width_in_mb * height_in_mb * 64;
323
324 /* IT surface buffer */
325 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
326 break;
327
328 default:
329 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
330 return -EINVAL;
331 }
332
333 if (width > pitch) {
334 DRM_ERROR("Invalid UVD decoding target pitch!\n");
335 return -EINVAL;
336 }
337
338 if (dpb_size < min_dpb_size) {
339 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
340 dpb_size, min_dpb_size);
341 return -EINVAL;
342 }
343
344 buf_sizes[0x1] = dpb_size;
345 buf_sizes[0x2] = image_size;
346 return 0;
347}
348
349static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
350 unsigned offset, unsigned buf_sizes[])
351{
352 int32_t *msg, msg_type, handle;
85a129ca 353 unsigned img_size = 0;
f2ba57b5
CK		 354 void *ptr;
355
356 int i, r;
357
358 if (offset & 0x3F) {
359 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
360 return -EINVAL;
361 }
362
112a6d0c
CK		 363 if (bo->tbo.sync_obj) {
364 r = radeon_fence_wait(bo->tbo.sync_obj, false);
365 if (r) {
366 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
367 return r;
368 }
369 }
370
f2ba57b5 371 r = radeon_bo_kmap(bo, &ptr);
56cc2c15
CK		 372 if (r) {
373 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
f2ba57b5 374 return r;
56cc2c15 375 }
f2ba57b5
CK		 376
377 msg = ptr + offset;
378
379 msg_type = msg[1];
380 handle = msg[2];
381
382 if (handle == 0) {
383 DRM_ERROR("Invalid UVD handle!\n");
384 return -EINVAL;
385 }
386
387 if (msg_type == 1) {
388 /* it's a decode msg, calc buffer sizes */
389 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
85a129ca
AD		 390 /* calc image size (width * height) */
391 img_size = msg[6] * msg[7];
f2ba57b5
CK		 392 radeon_bo_kunmap(bo);
393 if (r)
394 return r;
395
396 } else if (msg_type == 2) {
397 /* it's a destroy msg, free the handle */
398 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
399 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
400 radeon_bo_kunmap(bo);
401 return 0;
402 } else {
85a129ca
AD		 403 /* it's a create msg, calc image size (width * height) */
404 img_size = msg[7] * msg[8];
f2ba57b5 405 radeon_bo_kunmap(bo);
56cc2c15
CK		 406
407 if (msg_type != 0) {
408 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
409 return -EINVAL;
410 }
411
412 /* it's a create msg, no special handling needed */
f2ba57b5
CK		 413 }
414
415 /* create or decode, validate the handle */
416 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
417 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
418 return 0;
419 }
420
421 /* handle not found try to alloc a new one */
422 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
423 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
424 p->rdev->uvd.filp[i] = p->filp;
85a129ca 425 p->rdev->uvd.img_size[i] = img_size;
f2ba57b5
CK		 426 return 0;
427 }
428 }
429
430 DRM_ERROR("No more free UVD handles!\n");
431 return -EINVAL;
432}
433
434static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
435 int data0, int data1,
56cc2c15 436 unsigned buf_sizes[], bool *has_msg_cmd)
f2ba57b5
CK		 437{
438 struct radeon_cs_chunk *relocs_chunk;
439 struct radeon_cs_reloc *reloc;
440 unsigned idx, cmd, offset;
441 uint64_t start, end;
442 int r;
443
444 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
445 offset = radeon_get_ib_value(p, data0);
446 idx = radeon_get_ib_value(p, data1);
447 if (idx >= relocs_chunk->length_dw) {
448 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
449 idx, relocs_chunk->length_dw);
450 return -EINVAL;
451 }
452
453 reloc = p->relocs_ptr[(idx / 4)];
454 start = reloc->lobj.gpu_offset;
455 end = start + radeon_bo_size(reloc->robj);
456 start += offset;
457
458 p->ib.ptr[data0] = start & 0xFFFFFFFF;
459 p->ib.ptr[data1] = start >> 32;
460
461 cmd = radeon_get_ib_value(p, p->idx) >> 1;
462
463 if (cmd < 0x4) {
464 if ((end - start) < buf_sizes[cmd]) {
56cc2c15 465 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
f2ba57b5
CK		 466 (unsigned)(end - start), buf_sizes[cmd]);
467 return -EINVAL;
468 }
469
470 } else if (cmd != 0x100) {
471 DRM_ERROR("invalid UVD command %X!\n", cmd);
472 return -EINVAL;
473 }
474
a92c7d55
CK		 475 if ((start >> 28) != (end >> 28)) {
476 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
477 start, end);
478 return -EINVAL;
f2ba57b5
CK		 479 }
480
4b40e592 481 if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
a92c7d55
CK		 482 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
483 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
f2ba57b5
CK		 484 start, end);
485 return -EINVAL;
486 }
487
a92c7d55 488 if (cmd == 0) {
56cc2c15
CK		 489 if (*has_msg_cmd) {
490 DRM_ERROR("More than one message in a UVD-IB!\n");
491 return -EINVAL;
492 }
493 *has_msg_cmd = true;
a92c7d55
CK		 494 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
495 if (r)
496 return r;
56cc2c15
CK		 497 } else if (!*has_msg_cmd) {
498 DRM_ERROR("Message needed before other commands are send!\n");
499 return -EINVAL;
a92c7d55
CK		 500 }
501
f2ba57b5
CK		 502 return 0;
503}
504
505static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
506 struct radeon_cs_packet *pkt,
507 int *data0, int *data1,
56cc2c15
CK		 508 unsigned buf_sizes[],
509 bool *has_msg_cmd)
f2ba57b5
CK		 510{
511 int i, r;
512
513 p->idx++;
514 for (i = 0; i <= pkt->count; ++i) {
515 switch (pkt->reg + i*4) {
516 case UVD_GPCOM_VCPU_DATA0:
517 *data0 = p->idx;
518 break;
519 case UVD_GPCOM_VCPU_DATA1:
520 *data1 = p->idx;
521 break;
522 case UVD_GPCOM_VCPU_CMD:
56cc2c15
CK		 523 r = radeon_uvd_cs_reloc(p, *data0, *data1,
524 buf_sizes, has_msg_cmd);
f2ba57b5
CK		 525 if (r)
526 return r;
527 break;
528 case UVD_ENGINE_CNTL:
529 break;
530 default:
531 DRM_ERROR("Invalid reg 0x%X!\n",
532 pkt->reg + i*4);
533 return -EINVAL;
534 }
535 p->idx++;
536 }
537 return 0;
538}
539
540int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
541{
542 struct radeon_cs_packet pkt;
543 int r, data0 = 0, data1 = 0;
544
56cc2c15
CK		 545 /* does the IB has a msg command */
546 bool has_msg_cmd = false;
547
f2ba57b5
CK		 548 /* minimum buffer sizes */
549 unsigned buf_sizes[] = {
550 [0x00000000] = 2048,
551 [0x00000001] = 32 * 1024 * 1024,
552 [0x00000002] = 2048 * 1152 * 3,
553 [0x00000003] = 2048,
554 };
555
556 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
557 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
558 p->chunks[p->chunk_ib_idx].length_dw);
559 return -EINVAL;
560 }
561
562 if (p->chunk_relocs_idx == -1) {
563 DRM_ERROR("No relocation chunk !\n");
564 return -EINVAL;
565 }
566
567
568 do {
569 r = radeon_cs_packet_parse(p, &pkt, p->idx);
570 if (r)
571 return r;
572 switch (pkt.type) {
573 case RADEON_PACKET_TYPE0:
56cc2c15
CK		 574 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
575 buf_sizes, &has_msg_cmd);
f2ba57b5
CK		 576 if (r)
577 return r;
578 break;
579 case RADEON_PACKET_TYPE2:
580 p->idx += pkt.count + 2;
581 break;
582 default:
583 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
584 return -EINVAL;
585 }
586 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
56cc2c15
CK		 587
588 if (!has_msg_cmd) {
589 DRM_ERROR("UVD-IBs need a msg command!\n");
590 return -EINVAL;
591 }
592
f2ba57b5
CK		 593 return 0;
594}
595
596static int radeon_uvd_send_msg(struct radeon_device *rdev,
597 int ring, struct radeon_bo *bo,
598 struct radeon_fence **fence)
599{
600 struct ttm_validate_buffer tv;
ecff665f 601 struct ww_acquire_ctx ticket;
f2ba57b5
CK		 602 struct list_head head;
603 struct radeon_ib ib;
604 uint64_t addr;
605 int i, r;
606
607 memset(&tv, 0, sizeof(tv));
608 tv.bo = &bo->tbo;
609
610 INIT_LIST_HEAD(&head);
611 list_add(&tv.head, &head);
612
ecff665f 613 r = ttm_eu_reserve_buffers(&ticket, &head);
f2ba57b5
CK		 614 if (r)
615 return r;
616
617 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
618 radeon_uvd_force_into_uvd_segment(bo);
619
620 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
ecff665f
ML		 621 if (r)
622 goto err;
f2ba57b5 623
727ddc84 624 r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
ecff665f
ML		 625 if (r)
626 goto err;
f2ba57b5
CK		 627
628 addr = radeon_bo_gpu_offset(bo);
629 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
630 ib.ptr[1] = addr;
631 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
632 ib.ptr[3] = addr >> 32;
633 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
634 ib.ptr[5] = 0;
635 for (i = 6; i < 16; ++i)
636 ib.ptr[i] = PACKET2(0);
637 ib.length_dw = 16;
638
639 r = radeon_ib_schedule(rdev, &ib, NULL);
ecff665f
ML		 640 if (r)
641 goto err;
642 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
f2ba57b5
CK		 643
644 if (fence)
645 *fence = radeon_fence_ref(ib.fence);
646
647 radeon_ib_free(rdev, &ib);
648 radeon_bo_unref(&bo);
649 return 0;
ecff665f
ML		 650
651err:
652 ttm_eu_backoff_reservation(&ticket, &head);
653 return r;
f2ba57b5
CK		 654}
655
656/* multiple fence commands without any stream commands in between can
657 crash the vcpu so just try to emmit a dummy create/destroy msg to
658 avoid this */
659int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
660 uint32_t handle, struct radeon_fence **fence)
661{
662 struct radeon_bo *bo;
663 uint32_t *msg;
664 int r, i;
665
666 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
667 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
668 if (r)
669 return r;
670
671 r = radeon_bo_reserve(bo, false);
672 if (r) {
673 radeon_bo_unref(&bo);
674 return r;
675 }
676
677 r = radeon_bo_kmap(bo, (void **)&msg);
678 if (r) {
679 radeon_bo_unreserve(bo);
680 radeon_bo_unref(&bo);
681 return r;
682 }
683
684 /* stitch together an UVD create msg */
9b1be4dc
AD		 685 msg[0] = cpu_to_le32(0x00000de4);
686 msg[1] = cpu_to_le32(0x00000000);
687 msg[2] = cpu_to_le32(handle);
688 msg[3] = cpu_to_le32(0x00000000);
689 msg[4] = cpu_to_le32(0x00000000);
690 msg[5] = cpu_to_le32(0x00000000);
691 msg[6] = cpu_to_le32(0x00000000);
692 msg[7] = cpu_to_le32(0x00000780);
693 msg[8] = cpu_to_le32(0x00000440);
694 msg[9] = cpu_to_le32(0x00000000);
695 msg[10] = cpu_to_le32(0x01b37000);
f2ba57b5 696 for (i = 11; i < 1024; ++i)
9b1be4dc 697 msg[i] = cpu_to_le32(0x0);
f2ba57b5
CK		 698
699 radeon_bo_kunmap(bo);
700 radeon_bo_unreserve(bo);
701
702 return radeon_uvd_send_msg(rdev, ring, bo, fence);
703}
704
705int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
706 uint32_t handle, struct radeon_fence **fence)
707{
708 struct radeon_bo *bo;
709 uint32_t *msg;
710 int r, i;
711
712 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
713 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
714 if (r)
715 return r;
716
717 r = radeon_bo_reserve(bo, false);
718 if (r) {
719 radeon_bo_unref(&bo);
720 return r;
721 }
722
723 r = radeon_bo_kmap(bo, (void **)&msg);
724 if (r) {
725 radeon_bo_unreserve(bo);
726 radeon_bo_unref(&bo);
727 return r;
728 }
729
730 /* stitch together an UVD destroy msg */
9b1be4dc
AD		 731 msg[0] = cpu_to_le32(0x00000de4);
732 msg[1] = cpu_to_le32(0x00000002);
733 msg[2] = cpu_to_le32(handle);
734 msg[3] = cpu_to_le32(0x00000000);
f2ba57b5 735 for (i = 4; i < 1024; ++i)
9b1be4dc 736 msg[i] = cpu_to_le32(0x0);
f2ba57b5
CK		 737
738 radeon_bo_kunmap(bo);
739 radeon_bo_unreserve(bo);
740
741 return radeon_uvd_send_msg(rdev, ring, bo, fence);
742}
55b51c88 743
85a129ca
AD		 744/**
745 * radeon_uvd_count_handles - count number of open streams
746 *
747 * @rdev: radeon_device pointer
748 * @sd: number of SD streams
749 * @hd: number of HD streams
750 *
751 * Count the number of open SD/HD streams as a hint for power mangement
752 */
753static void radeon_uvd_count_handles(struct radeon_device *rdev,
754 unsigned *sd, unsigned *hd)
755{
756 unsigned i;
757
758 *sd = 0;
759 *hd = 0;
760
761 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
762 if (!atomic_read(&rdev->uvd.handles[i]))
763 continue;
764
765 if (rdev->uvd.img_size[i] >= 720*576)
766 ++(*hd);
767 else
768 ++(*sd);
769 }
770}
771
55b51c88
CK		 772static void radeon_uvd_idle_work_handler(struct work_struct *work)
773{
774 struct radeon_device *rdev =
775 container_of(work, struct radeon_device, uvd.idle_work.work);
776
8a227555
AD		 777 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
778 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
ce3537d5 779 radeon_dpm_enable_uvd(rdev, false);
8a227555
AD		 780 } else {
781 radeon_set_uvd_clocks(rdev, 0, 0);
782 }
783 } else {
55b51c88
CK		 784 schedule_delayed_work(&rdev->uvd.idle_work,
785 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
8a227555 786 }
55b51c88
CK		 787}
788
789void radeon_uvd_note_usage(struct radeon_device *rdev)
790{
ce3537d5 791 bool streams_changed = false;
55b51c88
CK		 792 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
793 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
794 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
ce3537d5
AD		 795
796 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
797 unsigned hd = 0, sd = 0;
798 radeon_uvd_count_handles(rdev, &sd, &hd);
799 if ((rdev->pm.dpm.sd != sd) ||
800 (rdev->pm.dpm.hd != hd)) {
801 rdev->pm.dpm.sd = sd;
802 rdev->pm.dpm.hd = hd;
803 streams_changed = true;
804 }
805 }
806
807 if (set_clocks || streams_changed) {
8a227555 808 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
ce3537d5 809 radeon_dpm_enable_uvd(rdev, true);
8a227555
AD		 810 } else {
811 radeon_set_uvd_clocks(rdev, 53300, 40000);
812 }
813 }
55b51c88 814}
facd112d
CK		 815
816static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
817 unsigned target_freq,
818 unsigned pd_min,
819 unsigned pd_even)
820{
821 unsigned post_div = vco_freq / target_freq;
822
823 /* adjust to post divider minimum value */
824 if (post_div < pd_min)
825 post_div = pd_min;
826
827 /* we alway need a frequency less than or equal the target */
828 if ((vco_freq / post_div) > target_freq)
829 post_div += 1;
830
831 /* post dividers above a certain value must be even */
832 if (post_div > pd_even && post_div % 2)
833 post_div += 1;
834
835 return post_div;
836}
837
838/**
839 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
840 *
841 * @rdev: radeon_device pointer
842 * @vclk: wanted VCLK
843 * @dclk: wanted DCLK
844 * @vco_min: minimum VCO frequency
845 * @vco_max: maximum VCO frequency
846 * @fb_factor: factor to multiply vco freq with
847 * @fb_mask: limit and bitmask for feedback divider
848 * @pd_min: post divider minimum
849 * @pd_max: post divider maximum
850 * @pd_even: post divider must be even above this value
851 * @optimal_fb_div: resulting feedback divider
852 * @optimal_vclk_div: resulting vclk post divider
853 * @optimal_dclk_div: resulting dclk post divider
854 *
855 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
856 * Returns zero on success -EINVAL on error.
857 */
858int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
859 unsigned vclk, unsigned dclk,
860 unsigned vco_min, unsigned vco_max,
861 unsigned fb_factor, unsigned fb_mask,
862 unsigned pd_min, unsigned pd_max,
863 unsigned pd_even,
864 unsigned *optimal_fb_div,
865 unsigned *optimal_vclk_div,
866 unsigned *optimal_dclk_div)
867{
868 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
869
870 /* start off with something large */
871 unsigned optimal_score = ~0;
872
873 /* loop through vco from low to high */
874 vco_min = max(max(vco_min, vclk), dclk);
875 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
876
877 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
878 unsigned vclk_div, dclk_div, score;
879
880 do_div(fb_div, ref_freq);
881
882 /* fb div out of range ? */
883 if (fb_div > fb_mask)
884 break; /* it can oly get worse */
885
886 fb_div &= fb_mask;
887
888 /* calc vclk divider with current vco freq */
889 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
890 pd_min, pd_even);
891 if (vclk_div > pd_max)
892 break; /* vco is too big, it has to stop */
893
894 /* calc dclk divider with current vco freq */
895 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
896 pd_min, pd_even);
897 if (vclk_div > pd_max)
898 break; /* vco is too big, it has to stop */
899
900 /* calc score with current vco freq */
901 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
902
903 /* determine if this vco setting is better than current optimal settings */
904 if (score < optimal_score) {
905 *optimal_fb_div = fb_div;
906 *optimal_vclk_div = vclk_div;
907 *optimal_dclk_div = dclk_div;
908 optimal_score = score;
909 if (optimal_score == 0)
910 break; /* it can't get better than this */
911 }
912 }
913
914 /* did we found a valid setup ? */
915 if (optimal_score == ~0)
916 return -EINVAL;
917
918 return 0;
919}
920
921int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
922 unsigned cg_upll_func_cntl)
923{
924 unsigned i;
925
926 /* make sure UPLL_CTLREQ is deasserted */
927 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
928
929 mdelay(10);
930
931 /* assert UPLL_CTLREQ */
932 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
933
934 /* wait for CTLACK and CTLACK2 to get asserted */
935 for (i = 0; i < 100; ++i) {
936 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
937 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
938 break;
939 mdelay(10);
940 }
941
942 /* deassert UPLL_CTLREQ */
943 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
944
945 if (i == 100) {
946 DRM_ERROR("Timeout setting UVD clocks!\n");
947 return -ETIMEDOUT;
948 }
949
950 return 0;
951}
Linux kernel - Deliverables
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