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drm/radeon: separate vblank and pflip crtc handling
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
760285e7 38#include <drm/drmP.h>
771fe6b9 39#include "radeon.h"
e6990375 40#include "radeon_asic.h"
c010f800
JG		 41#include "atom.h"
42#include "rs600d.h"
771fe6b9 43
3f7dc91a
DA		 44#include "rs600_reg_safe.h"
45
1109ca09 46static void rs600_gpu_init(struct radeon_device *rdev);
771fe6b9 47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 48
75104fa4
AD		 49static const u32 crtc_offsets[2] =
50{
51 0,
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53};
54
bea5497b
AD		 55static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
56{
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
58 return true;
59 else
60 return false;
61}
62
63static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
64{
65 u32 pos1, pos2;
66
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69
70 if (pos1 != pos2)
71 return true;
72 else
73 return false;
74}
75
76/**
77 * avivo_wait_for_vblank - vblank wait asic callback.
78 *
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
81 *
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
83 */
3ae19b75
AD		 84void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
85{
bea5497b 86 unsigned i = 0;
3ae19b75 87
75104fa4
AD		 88 if (crtc >= rdev->num_crtc)
89 return;
90
bea5497b
AD		 91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
92 return;
93
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
96 */
97 while (avivo_is_in_vblank(rdev, crtc)) {
98 if (i++ % 100 == 0) {
99 if (!avivo_is_counter_moving(rdev, crtc))
3ae19b75 100 break;
3ae19b75 101 }
bea5497b
AD		 102 }
103
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
3ae19b75 107 break;
3ae19b75
AD		 108 }
109 }
110}
111
157fa14d 112void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
6f34be50
AD		 113{
114 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
115 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 116 int i;
6f34be50
AD		 117
118 /* Lock the graphics update lock */
119 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
120 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
121
122 /* update the scanout addresses */
123 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
124 (u32)crtc_base);
125 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
126 (u32)crtc_base);
127
128 /* Wait for update_pending to go high. */
f6496479
AD		 129 for (i = 0; i < rdev->usec_timeout; i++) {
130 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
131 break;
132 udelay(1);
133 }
6f34be50
AD		 134 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
135
136 /* Unlock the lock, so double-buffering can take place inside vblank */
137 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
138 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
157fa14d
CK		 139}
140
141bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
142{
143 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
6f34be50
AD		 144
145 /* Return current update_pending status: */
157fa14d
CK		 146 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
147 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
6f34be50
AD		 148}
149
134b480f
AD		 150void avivo_program_fmt(struct drm_encoder *encoder)
151{
152 struct drm_device *dev = encoder->dev;
153 struct radeon_device *rdev = dev->dev_private;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
156 int bpc = 0;
157 u32 tmp = 0;
6214bb74 158 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
134b480f 159
6214bb74
AD		 160 if (connector) {
161 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
134b480f 162 bpc = radeon_get_monitor_bpc(connector);
6214bb74
AD		 163 dither = radeon_connector->dither;
164 }
134b480f
AD		 165
166 /* LVDS FMT is set up by atom */
167 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
168 return;
169
170 if (bpc == 0)
171 return;
172
173 switch (bpc) {
174 case 6:
6214bb74 175 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 176 /* XXX sort out optimal dither settings */
177 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
178 else
179 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
180 break;
181 case 8:
6214bb74 182 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 183 /* XXX sort out optimal dither settings */
184 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
185 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
186 else
187 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
188 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
189 break;
190 case 10:
191 default:
192 /* not needed */
193 break;
194 }
195
196 switch (radeon_encoder->encoder_id) {
197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
198 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
199 break;
200 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
201 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
202 break;
203 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
204 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
205 break;
206 case ENCODER_OBJECT_ID_INTERNAL_DDI:
207 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
208 break;
209 default:
210 break;
211 }
212}
213
49e02b73
AD		 214void rs600_pm_misc(struct radeon_device *rdev)
215{
49e02b73
AD		 216 int requested_index = rdev->pm.requested_power_state_index;
217 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
218 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
219 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
536fcd51 220 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
49e02b73
AD		 221
222 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
223 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
224 tmp = RREG32(voltage->gpio.reg);
225 if (voltage->active_high)
226 tmp |= voltage->gpio.mask;
227 else
228 tmp &= ~(voltage->gpio.mask);
229 WREG32(voltage->gpio.reg, tmp);
230 if (voltage->delay)
231 udelay(voltage->delay);
232 } else {
233 tmp = RREG32(voltage->gpio.reg);
234 if (voltage->active_high)
235 tmp &= ~voltage->gpio.mask;
236 else
237 tmp |= voltage->gpio.mask;
238 WREG32(voltage->gpio.reg, tmp);
239 if (voltage->delay)
240 udelay(voltage->delay);
241 }
7ac9aa5a 242 } else if (voltage->type == VOLTAGE_VDDC)
8a83ec5e 243 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
49e02b73
AD		 244
245 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
246 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
247 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
248 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
249 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
250 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
251 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
252 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
253 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
254 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
255 }
256 } else {
257 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
258 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
259 }
260 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
261
262 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
263 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
264 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
265 if (voltage->delay) {
266 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
267 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
268 } else
269 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
270 } else
271 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
272 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
273
274 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
275 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
276 hdp_dyn_cntl &= ~HDP_FORCEON;
277 else
278 hdp_dyn_cntl |= HDP_FORCEON;
279 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
536fcd51
AD		 280#if 0
281 /* mc_host_dyn seems to cause hangs from time to time */
49e02b73
AD		 282 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
283 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
284 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
285 else
286 mc_host_dyn_cntl |= MC_HOST_FORCEON;
287 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
536fcd51
AD		 288#endif
289 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
290 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
291 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
292 else
293 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
294 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
49e02b73
AD		 295
296 /* set pcie lanes */
297 if ((rdev->flags & RADEON_IS_PCIE) &&
298 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 299 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 300 (ps->pcie_lanes !=
301 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
302 radeon_set_pcie_lanes(rdev,
303 ps->pcie_lanes);
ce8a3eb2 304 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 305 }
49e02b73
AD		 306}
307
308void rs600_pm_prepare(struct radeon_device *rdev)
309{
310 struct drm_device *ddev = rdev->ddev;
311 struct drm_crtc *crtc;
312 struct radeon_crtc *radeon_crtc;
313 u32 tmp;
314
315 /* disable any active CRTCs */
316 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
317 radeon_crtc = to_radeon_crtc(crtc);
318 if (radeon_crtc->enabled) {
319 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
320 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
321 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
322 }
323 }
324}
325
326void rs600_pm_finish(struct radeon_device *rdev)
327{
328 struct drm_device *ddev = rdev->ddev;
329 struct drm_crtc *crtc;
330 struct radeon_crtc *radeon_crtc;
331 u32 tmp;
332
333 /* enable any active CRTCs */
334 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
335 radeon_crtc = to_radeon_crtc(crtc);
336 if (radeon_crtc->enabled) {
337 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
338 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
339 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
340 }
341 }
342}
343
dcfdd408
AD		 344/* hpd for digital panel detect/disconnect */
345bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
346{
347 u32 tmp;
348 bool connected = false;
349
350 switch (hpd) {
351 case RADEON_HPD_1:
352 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
353 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
354 connected = true;
355 break;
356 case RADEON_HPD_2:
357 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
358 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
359 connected = true;
360 break;
361 default:
362 break;
363 }
364 return connected;
365}
366
367void rs600_hpd_set_polarity(struct radeon_device *rdev,
368 enum radeon_hpd_id hpd)
369{
370 u32 tmp;
371 bool connected = rs600_hpd_sense(rdev, hpd);
372
373 switch (hpd) {
374 case RADEON_HPD_1:
375 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
376 if (connected)
377 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
378 else
379 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
380 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
381 break;
382 case RADEON_HPD_2:
383 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
384 if (connected)
385 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
386 else
387 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
388 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
389 break;
390 default:
391 break;
392 }
393}
394
395void rs600_hpd_init(struct radeon_device *rdev)
396{
397 struct drm_device *dev = rdev->ddev;
398 struct drm_connector *connector;
fb98257a 399 unsigned enable = 0;
dcfdd408
AD		 400
401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
402 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
403 switch (radeon_connector->hpd.hpd) {
404 case RADEON_HPD_1:
405 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
406 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
dcfdd408
AD		 407 break;
408 case RADEON_HPD_2:
409 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
410 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
dcfdd408
AD		 411 break;
412 default:
413 break;
414 }
fb98257a 415 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 416 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
dcfdd408 417 }
fb98257a 418 radeon_irq_kms_enable_hpd(rdev, enable);
dcfdd408
AD		 419}
420
421void rs600_hpd_fini(struct radeon_device *rdev)
422{
423 struct drm_device *dev = rdev->ddev;
424 struct drm_connector *connector;
fb98257a 425 unsigned disable = 0;
dcfdd408
AD		 426
427 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
428 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
429 switch (radeon_connector->hpd.hpd) {
430 case RADEON_HPD_1:
431 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
432 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
dcfdd408
AD		 433 break;
434 case RADEON_HPD_2:
435 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
436 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
dcfdd408
AD		 437 break;
438 default:
439 break;
440 }
fb98257a 441 disable |= 1 << radeon_connector->hpd.hpd;
dcfdd408 442 }
fb98257a 443 radeon_irq_kms_disable_hpd(rdev, disable);
dcfdd408
AD		 444}
445
90aca4d2
JG		 446int rs600_asic_reset(struct radeon_device *rdev)
447{
90aca4d2 448 struct rv515_mc_save save;
25b2ec5b
AD		 449 u32 status, tmp;
450 int ret = 0;
90aca4d2 451
90aca4d2
JG		 452 status = RREG32(R_000E40_RBBM_STATUS);
453 if (!G_000E40_GUI_ACTIVE(status)) {
454 return 0;
455 }
25b2ec5b
AD		 456 /* Stops all mc clients */
457 rv515_mc_stop(rdev, &save);
90aca4d2
JG		 458 status = RREG32(R_000E40_RBBM_STATUS);
459 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
460 /* stop CP */
461 WREG32(RADEON_CP_CSQ_CNTL, 0);
462 tmp = RREG32(RADEON_CP_RB_CNTL);
463 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
464 WREG32(RADEON_CP_RB_RPTR_WR, 0);
465 WREG32(RADEON_CP_RB_WPTR, 0);
466 WREG32(RADEON_CP_RB_CNTL, tmp);
467 pci_save_state(rdev->pdev);
468 /* disable bus mastering */
642ce525
MD		 469 pci_clear_master(rdev->pdev);
470 mdelay(1);
90aca4d2
JG		 471 /* reset GA+VAP */
472 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
473 S_0000F0_SOFT_RESET_GA(1));
474 RREG32(R_0000F0_RBBM_SOFT_RESET);
475 mdelay(500);
476 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
477 mdelay(1);
478 status = RREG32(R_000E40_RBBM_STATUS);
479 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
480 /* reset CP */
481 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
482 RREG32(R_0000F0_RBBM_SOFT_RESET);
483 mdelay(500);
484 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
485 mdelay(1);
486 status = RREG32(R_000E40_RBBM_STATUS);
487 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
488 /* reset MC */
489 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
490 RREG32(R_0000F0_RBBM_SOFT_RESET);
491 mdelay(500);
492 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
493 mdelay(1);
494 status = RREG32(R_000E40_RBBM_STATUS);
495 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
496 /* restore PCI & busmastering */
497 pci_restore_state(rdev->pdev);
498 /* Check if GPU is idle */
499 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
500 dev_err(rdev->dev, "failed to reset GPU\n");
25b2ec5b
AD		 501 ret = -1;
502 } else
503 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 504 rv515_mc_resume(rdev, &save);
25b2ec5b 505 return ret;
90aca4d2
JG		 506}
507
771fe6b9
JG		 508/*
509 * GART.
510 */
511void rs600_gart_tlb_flush(struct radeon_device *rdev)
512{
513 uint32_t tmp;
514
c010f800
JG		 515 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
516 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
517 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 518
c010f800 519 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
30f69f3f 520 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
c010f800 521 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 522
c010f800
JG		 523 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
524 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
525 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
526 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 527}
528
1109ca09 529static int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 530{
771fe6b9
JG		 531 int r;
532
c9a1be96 533 if (rdev->gart.robj) {
fce7d61b 534 WARN(1, "RS600 GART already initialized\n");
4aac0473
JG		 535 return 0;
536 }
771fe6b9
JG		 537 /* Initialize common gart structure */
538 r = radeon_gart_init(rdev);
539 if (r) {
540 return r;
541 }
542 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 543 return radeon_gart_table_vram_alloc(rdev);
544}
545
e22e6d20 546static int rs600_gart_enable(struct radeon_device *rdev)
4aac0473 547{
c010f800 548 u32 tmp;
4aac0473
JG		 549 int r, i;
550
c9a1be96 551 if (rdev->gart.robj == NULL) {
4aac0473
JG		 552 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
553 return -EINVAL;
771fe6b9 554 }
4aac0473
JG		 555 r = radeon_gart_table_vram_pin(rdev);
556 if (r)
557 return r;
82568565 558 radeon_gart_restore(rdev);
c010f800 559 /* Enable bus master */
e22e6d20
AD		 560 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
561 WREG32(RADEON_BUS_CNTL, tmp);
771fe6b9 562 /* FIXME: setup default page */
c010f800 563 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 564 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
565 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
566
771fe6b9 567 for (i = 0; i < 19; i++) {
c010f800 568 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 569 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
570 S_00016C_SYSTEM_ACCESS_MODE_MASK(
571 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
572 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
573 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
574 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
575 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
576 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 577 }
771fe6b9 578 /* enable first context */
c010f800 579 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 580 S_000102_ENABLE_PAGE_TABLE(1) |
581 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
582
771fe6b9 583 /* disable all other contexts */
4f15d24a 584 for (i = 1; i < 8; i++)
c010f800 585 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 586
587 /* setup the page table */
c010f800 588 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 589 rdev->gart.table_addr);
590 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
591 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 592 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 593
4f15d24a
AD		 594 /* System context maps to VRAM space */
595 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
596 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
597
771fe6b9 598 /* enable page tables */
c010f800
JG		 599 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
600 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
601 tmp = RREG32_MC(R_000009_MC_CNTL1);
602 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9 603 rs600_gart_tlb_flush(rdev);
fcf4de5a
TV		 604 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
605 (unsigned)(rdev->mc.gtt_size >> 20),
606 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 607 rdev->gart.ready = true;
608 return 0;
609}
610
1109ca09 611static void rs600_gart_disable(struct radeon_device *rdev)
771fe6b9 612{
4c788679 613 u32 tmp;
771fe6b9
JG		 614
615 /* FIXME: disable out of gart access */
c010f800
JG		 616 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
617 tmp = RREG32_MC(R_000009_MC_CNTL1);
618 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
c9a1be96 619 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 620}
621
1109ca09 622static void rs600_gart_fini(struct radeon_device *rdev)
4aac0473 623{
f9274562 624 radeon_gart_fini(rdev);
4aac0473
JG		 625 rs600_gart_disable(rdev);
626 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 627}
628
629#define R600_PTE_VALID (1 << 0)
630#define R600_PTE_SYSTEM (1 << 1)
631#define R600_PTE_SNOOPED (1 << 2)
632#define R600_PTE_READABLE (1 << 5)
633#define R600_PTE_WRITEABLE (1 << 6)
634
635int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
636{
c9a1be96 637 void __iomem *ptr = (void *)rdev->gart.ptr;
771fe6b9
JG		 638
639 if (i < 0 || i > rdev->gart.num_gpu_pages) {
640 return -EINVAL;
641 }
642 addr = addr & 0xFFFFFFFFFFFFF000ULL;
643 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
644 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
a0533fbf 645 writeq(addr, ptr + (i * 8));
771fe6b9
JG		 646 return 0;
647}
648
7ed220d7
MD		 649int rs600_irq_set(struct radeon_device *rdev)
650{
651 uint32_t tmp = 0;
652 uint32_t mode_int = 0;
dcfdd408
AD		 653 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
654 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
655 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
656 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
f122c610
AD		 657 u32 hdmi0;
658 if (ASIC_IS_DCE2(rdev))
659 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
660 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
661 else
662 hdmi0 = 0;
7ed220d7 663
003e69f9 664 if (!rdev->irq.installed) {
fce7d61b 665 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 666 WREG32(R_000040_GEN_INT_CNTL, 0);
667 return -EINVAL;
668 }
736fc37f 669 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
c010f800 670 tmp |= S_000040_SW_INT_EN(1);
7ed220d7 671 }
6f34be50 672 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 673 atomic_read(&rdev->irq.pflip[0])) {
c010f800 674 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7 675 }
6f34be50 676 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 677 atomic_read(&rdev->irq.pflip[1])) {
c010f800 678 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 679 }
dcfdd408
AD		 680 if (rdev->irq.hpd[0]) {
681 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
682 }
683 if (rdev->irq.hpd[1]) {
684 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
685 }
f122c610
AD		 686 if (rdev->irq.afmt[0]) {
687 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
688 }
c010f800
JG		 689 WREG32(R_000040_GEN_INT_CNTL, tmp);
690 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 691 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
692 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
f122c610
AD		 693 if (ASIC_IS_DCE2(rdev))
694 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
7ed220d7
MD		 695 return 0;
696}
697
6f34be50 698static inline u32 rs600_irq_ack(struct radeon_device *rdev)
7ed220d7 699{
01ceae8e 700 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
2031f77c 701 uint32_t irq_mask = S_000044_SW_INT(1);
dcfdd408 702 u32 tmp;
c010f800 703
01ceae8e 704 if (G_000044_DISPLAY_INT_STAT(irqs)) {
6f34be50
AD		 705 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
706 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
c010f800
JG		 707 WREG32(R_006534_D1MODE_VBLANK_STATUS,
708 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 709 }
6f34be50 710 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
c010f800
JG		 711 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
712 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 713 }
6f34be50 714 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
dcfdd408
AD		 715 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
716 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
717 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
718 }
6f34be50 719 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
dcfdd408
AD		 720 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
721 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
722 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
723 }
7ed220d7 724 } else {
6f34be50 725 rdev->irq.stat_regs.r500.disp_int = 0;
7ed220d7
MD		 726 }
727
f122c610
AD		 728 if (ASIC_IS_DCE2(rdev)) {
729 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
730 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
731 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
732 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
733 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
734 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
735 }
736 } else
737 rdev->irq.stat_regs.r500.hdmi0_status = 0;
738
7ed220d7 739 if (irqs) {
01ceae8e 740 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 741 }
742 return irqs & irq_mask;
743}
744
ac447df4
JG		 745void rs600_irq_disable(struct radeon_device *rdev)
746{
f122c610
AD		 747 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
748 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
749 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
ac447df4
JG		 750 WREG32(R_000040_GEN_INT_CNTL, 0);
751 WREG32(R_006540_DxMODE_INT_MASK, 0);
752 /* Wait and acknowledge irq */
753 mdelay(1);
6f34be50 754 rs600_irq_ack(rdev);
ac447df4
JG		 755}
756
7ed220d7
MD		 757int rs600_irq_process(struct radeon_device *rdev)
758{
6f34be50 759 u32 status, msi_rearm;
d4877cf2 760 bool queue_hotplug = false;
f122c610 761 bool queue_hdmi = false;
7ed220d7 762
6f34be50 763 status = rs600_irq_ack(rdev);
f122c610
AD		 764 if (!status &&
765 !rdev->irq.stat_regs.r500.disp_int &&
766 !rdev->irq.stat_regs.r500.hdmi0_status) {
7ed220d7
MD		 767 return IRQ_NONE;
768 }
f122c610
AD		 769 while (status ||
770 rdev->irq.stat_regs.r500.disp_int ||
771 rdev->irq.stat_regs.r500.hdmi0_status) {
7ed220d7 772 /* SW interrupt */
6f34be50 773 if (G_000044_SW_INT(status)) {
7465280c 774 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6f34be50 775 }
7ed220d7 776 /* Vertical blank interrupts */
6f34be50 777 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
6f34be50
AD		 778 if (rdev->irq.crtc_vblank_int[0]) {
779 drm_handle_vblank(rdev->ddev, 0);
780 rdev->pm.vblank_sync = true;
781 wake_up(&rdev->irq.vblank_queue);
782 }
736fc37f 783 if (atomic_read(&rdev->irq.pflip[0]))
1a0e7918 784 radeon_crtc_handle_vblank(rdev, 0);
c913e23a 785 }
6f34be50 786 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
6f34be50
AD		 787 if (rdev->irq.crtc_vblank_int[1]) {
788 drm_handle_vblank(rdev->ddev, 1);
789 rdev->pm.vblank_sync = true;
790 wake_up(&rdev->irq.vblank_queue);
791 }
736fc37f 792 if (atomic_read(&rdev->irq.pflip[1]))
1a0e7918 793 radeon_crtc_handle_vblank(rdev, 1);
c913e23a 794 }
6f34be50 795 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
d4877cf2
AD		 796 queue_hotplug = true;
797 DRM_DEBUG("HPD1\n");
dcfdd408 798 }
6f34be50 799 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
d4877cf2
AD		 800 queue_hotplug = true;
801 DRM_DEBUG("HPD2\n");
dcfdd408 802 }
f122c610
AD		 803 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
804 queue_hdmi = true;
805 DRM_DEBUG("HDMI0\n");
806 }
6f34be50 807 status = rs600_irq_ack(rdev);
7ed220d7 808 }
d4877cf2 809 if (queue_hotplug)
32c87fca 810 schedule_work(&rdev->hotplug_work);
f122c610
AD		 811 if (queue_hdmi)
812 schedule_work(&rdev->audio_work);
3e5cb98d
AD		 813 if (rdev->msi_enabled) {
814 switch (rdev->family) {
815 case CHIP_RS600:
816 case CHIP_RS690:
817 case CHIP_RS740:
818 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
819 WREG32(RADEON_BUS_CNTL, msi_rearm);
820 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
821 break;
822 default:
b7f5b7de 823 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 824 break;
825 }
826 }
7ed220d7
MD		 827 return IRQ_HANDLED;
828}
829
830u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
831{
832 if (crtc == 0)
c010f800 833 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 834 else
c010f800 835 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 836}
837
771fe6b9
JG		 838int rs600_mc_wait_for_idle(struct radeon_device *rdev)
839{
840 unsigned i;
771fe6b9
JG		 841
842 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 843 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 844 return 0;
c010f800 845 udelay(1);
771fe6b9
JG		 846 }
847 return -1;
848}
849
1109ca09 850static void rs600_gpu_init(struct radeon_device *rdev)
771fe6b9 851{
771fe6b9 852 r420_pipes_init(rdev);
c010f800
JG		 853 /* Wait for mc idle */
854 if (rs600_mc_wait_for_idle(rdev))
855 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 856}
857
1109ca09 858static void rs600_mc_init(struct radeon_device *rdev)
771fe6b9 859{
d594e46a
JG		 860 u64 base;
861
01d73a69
JC		 862 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
863 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
771fe6b9
JG		 864 rdev->mc.vram_is_ddr = true;
865 rdev->mc.vram_width = 128;
722f2943
AD		 866 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
867 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
51e5fcd3 868 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 869 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
870 base = RREG32_MC(R_000004_MC_FB_LOCATION);
871 base = G_000004_MC_FB_START(base) << 16;
872 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 873 rdev->mc.gtt_base_align = 0;
d594e46a 874 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 875 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 876}
877
c93bb85b
JG		 878void rs600_bandwidth_update(struct radeon_device *rdev)
879{
f46c0120
AD		 880 struct drm_display_mode *mode0 = NULL;
881 struct drm_display_mode *mode1 = NULL;
882 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
883 /* FIXME: implement full support */
884
885 radeon_update_display_priority(rdev);
886
887 if (rdev->mode_info.crtcs[0]->base.enabled)
888 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
889 if (rdev->mode_info.crtcs[1]->base.enabled)
890 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
891
892 rs690_line_buffer_adjust(rdev, mode0, mode1);
893
894 if (rdev->disp_priority == 2) {
895 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
896 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
897 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
898 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
899 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
900 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
901 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
902 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
903 }
c93bb85b
JG		 904}
905
771fe6b9
JG		 906uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
907{
0a5b7b0b
AD		 908 unsigned long flags;
909 u32 r;
910
911 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
c010f800
JG		 912 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
913 S_000070_MC_IND_CITF_ARB0(1));
0a5b7b0b
AD		 914 r = RREG32(R_000074_MC_IND_DATA);
915 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
916 return r;
771fe6b9
JG		 917}
918
919void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
920{
0a5b7b0b
AD		 921 unsigned long flags;
922
923 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
c010f800
JG		 924 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
925 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
926 WREG32(R_000074_MC_IND_DATA, v);
0a5b7b0b 927 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
c010f800
JG		 928}
929
1109ca09 930static void rs600_debugfs(struct radeon_device *rdev)
c010f800
JG		 931{
932 if (r100_debugfs_rbbm_init(rdev))
933 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 934}
3f7dc91a 935
3bc68535 936void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 937{
938 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
939 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 940}
941
c010f800
JG		 942static void rs600_mc_program(struct radeon_device *rdev)
943{
944 struct rv515_mc_save save;
945
946 /* Stops all mc clients */
947 rv515_mc_stop(rdev, &save);
948
949 /* Wait for mc idle */
950 if (rs600_mc_wait_for_idle(rdev))
951 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
952
953 /* FIXME: What does AGP means for such chipset ? */
954 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
955 WREG32_MC(R_000006_AGP_BASE, 0);
956 WREG32_MC(R_000007_AGP_BASE_2, 0);
957 /* Program MC */
958 WREG32_MC(R_000004_MC_FB_LOCATION,
959 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
960 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
961 WREG32(R_000134_HDP_FB_LOCATION,
962 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
963
964 rv515_mc_resume(rdev, &save);
965}
966
967static int rs600_startup(struct radeon_device *rdev)
968{
969 int r;
970
971 rs600_mc_program(rdev);
972 /* Resume clock */
973 rv515_clock_startup(rdev);
974 /* Initialize GPU configuration (# pipes, ...) */
975 rs600_gpu_init(rdev);
976 /* Initialize GART (initialize after TTM so we can allocate
977 * memory through TTM but finalize after TTM) */
978 r = rs600_gart_enable(rdev);
979 if (r)
980 return r;
724c80e1
AD		 981
982 /* allocate wb buffer */
983 r = radeon_wb_init(rdev);
984 if (r)
985 return r;
986
30eb77f4
JG		 987 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
988 if (r) {
989 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
990 return r;
991 }
992
c010f800 993 /* Enable IRQ */
e49f3959
AH		 994 if (!rdev->irq.installed) {
995 r = radeon_irq_kms_init(rdev);
996 if (r)
997 return r;
998 }
999
c010f800 1000 rs600_irq_set(rdev);
cafe6609 1001 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 1002 /* 1M ring buffer */
1003 r = r100_cp_init(rdev, 1024 * 1024);
1004 if (r) {
ec4f2ac4 1005 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
c010f800
JG		 1006 return r;
1007 }
b15ba512 1008
2898c348
CK		 1009 r = radeon_ib_pool_init(rdev);
1010 if (r) {
1011 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 1012 return r;
2898c348 1013 }
b15ba512 1014
d4e30ef0
AD		 1015 r = r600_audio_init(rdev);
1016 if (r) {
1017 dev_err(rdev->dev, "failed initializing audio\n");
1018 return r;
1019 }
1020
c010f800
JG		 1021 return 0;
1022}
1023
1024int rs600_resume(struct radeon_device *rdev)
1025{
6b7746e8
JG		 1026 int r;
1027
c010f800
JG		 1028 /* Make sur GART are not working */
1029 rs600_gart_disable(rdev);
1030 /* Resume clock before doing reset */
1031 rv515_clock_startup(rdev);
1032 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 1033 if (radeon_asic_reset(rdev)) {
c010f800
JG		 1034 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1035 RREG32(R_000E40_RBBM_STATUS),
1036 RREG32(R_0007C0_CP_STAT));
1037 }
1038 /* post */
1039 atom_asic_init(rdev->mode_info.atom_context);
1040 /* Resume clock after posting */
1041 rv515_clock_startup(rdev);
550e2d92
DA		 1042 /* Initialize surface registers */
1043 radeon_surface_init(rdev);
b15ba512
JG		 1044
1045 rdev->accel_working = true;
6b7746e8
JG		 1046 r = rs600_startup(rdev);
1047 if (r) {
1048 rdev->accel_working = false;
1049 }
1050 return r;
c010f800
JG		 1051}
1052
1053int rs600_suspend(struct radeon_device *rdev)
1054{
6c7bccea 1055 radeon_pm_suspend(rdev);
fe50ac78 1056 r600_audio_fini(rdev);
c010f800 1057 r100_cp_disable(rdev);
724c80e1 1058 radeon_wb_disable(rdev);
ac447df4 1059 rs600_irq_disable(rdev);
c010f800
JG		 1060 rs600_gart_disable(rdev);
1061 return 0;
1062}
1063
1064void rs600_fini(struct radeon_device *rdev)
1065{
6c7bccea 1066 radeon_pm_fini(rdev);
fe50ac78 1067 r600_audio_fini(rdev);
c010f800 1068 r100_cp_fini(rdev);
724c80e1 1069 radeon_wb_fini(rdev);
2898c348 1070 radeon_ib_pool_fini(rdev);
c010f800
JG		 1071 radeon_gem_fini(rdev);
1072 rs600_gart_fini(rdev);
1073 radeon_irq_kms_fini(rdev);
1074 radeon_fence_driver_fini(rdev);
4c788679 1075 radeon_bo_fini(rdev);
c010f800
JG		 1076 radeon_atombios_fini(rdev);
1077 kfree(rdev->bios);
1078 rdev->bios = NULL;
1079}
1080
3bc68535
JG		 1081int rs600_init(struct radeon_device *rdev)
1082{
c010f800
JG		 1083 int r;
1084
c010f800
JG		 1085 /* Disable VGA */
1086 rv515_vga_render_disable(rdev);
1087 /* Initialize scratch registers */
1088 radeon_scratch_init(rdev);
1089 /* Initialize surface registers */
1090 radeon_surface_init(rdev);
4c712e6c
DA		 1091 /* restore some register to sane defaults */
1092 r100_restore_sanity(rdev);
c010f800
JG		 1093 /* BIOS */
1094 if (!radeon_get_bios(rdev)) {
1095 if (ASIC_IS_AVIVO(rdev))
1096 return -EINVAL;
1097 }
1098 if (rdev->is_atom_bios) {
1099 r = radeon_atombios_init(rdev);
1100 if (r)
1101 return r;
1102 } else {
1103 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1104 return -EINVAL;
1105 }
1106 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 1107 if (radeon_asic_reset(rdev)) {
c010f800
JG		 1108 dev_warn(rdev->dev,
1109 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1110 RREG32(R_000E40_RBBM_STATUS),
1111 RREG32(R_0007C0_CP_STAT));
1112 }
1113 /* check if cards are posted or not */
72542d77
DA		 1114 if (radeon_boot_test_post_card(rdev) == false)
1115 return -EINVAL;
1116
c010f800
JG		 1117 /* Initialize clocks */
1118 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 1119 /* initialize memory controller */
1120 rs600_mc_init(rdev);
c010f800
JG		 1121 rs600_debugfs(rdev);
1122 /* Fence driver */
30eb77f4 1123 r = radeon_fence_driver_init(rdev);
c010f800
JG		 1124 if (r)
1125 return r;
1126 /* Memory manager */
4c788679 1127 r = radeon_bo_init(rdev);
c010f800
JG		 1128 if (r)
1129 return r;
1130 r = rs600_gart_init(rdev);
1131 if (r)
1132 return r;
1133 rs600_set_safe_registers(rdev);
b15ba512 1134
6c7bccea
AD		 1135 /* Initialize power management */
1136 radeon_pm_init(rdev);
1137
c010f800
JG		 1138 rdev->accel_working = true;
1139 r = rs600_startup(rdev);
1140 if (r) {
1141 /* Somethings want wront with the accel init stop accel */
1142 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800 1143 r100_cp_fini(rdev);
724c80e1 1144 radeon_wb_fini(rdev);
2898c348 1145 radeon_ib_pool_fini(rdev);
c010f800
JG		 1146 rs600_gart_fini(rdev);
1147 radeon_irq_kms_fini(rdev);
1148 rdev->accel_working = false;
1149 }
3f7dc91a
DA		 1150 return 0;
1151}
Linux kernel - Deliverables
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