[deliverable/linux.git] / drivers / gpu / drm / radeon / rs600.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"

#include "rs600_reg_safe.h"

/* rs600 depends on : */
void r100_hdp_reset(struct radeon_device *rdev);
int r100_gui_wait_for_idle(struct radeon_device *rdev);
int r300_mc_wait_for_idle(struct radeon_device *rdev);
void r420_pipes_init(struct radeon_device *rdev);

/* This files gather functions specifics to :
 * rs600
 *
 * Some of these functions might be used by newer ASICs.
 */
void rs600_gpu_init(struct radeon_device *rdev);
int rs600_mc_wait_for_idle(struct radeon_device *rdev);
void rs600_disable_vga(struct radeon_device *rdev);


/*
 * GART.
 */
void rs600_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;

	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
	WREG32_MC(RS600_MC_PT0_CNTL, tmp);

	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
	WREG32_MC(RS600_MC_PT0_CNTL, tmp);

	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
	WREG32_MC(RS600_MC_PT0_CNTL, tmp);
	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
}

int rs600_gart_enable(struct radeon_device *rdev)
{
	uint32_t tmp;
	int i;
	int r;

	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r) {
		return r;
	}
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	r = radeon_gart_table_vram_alloc(rdev);
	if (r) {
		return r;
	}
	/* FIXME: setup default page */
	WREG32_MC(RS600_MC_PT0_CNTL,
		 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
		  RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
	for (i = 0; i < 19; i++) {
		WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i,
			 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
			  RS600_SYSTEM_ACCESS_MODE_IN_SYS |
			  RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE |
			  RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
			  RS600_ENABLE_FRAGMENT_PROCESSING |
			  RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
	}

	/* System context map to GART space */
	WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location);
	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
	WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp);

	/* enable first context */
	WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location);
	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
	WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp);
	WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL,
		 (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT));
	/* disable all other contexts */
	for (i = 1; i < 8; i++) {
		WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
	}

	/* setup the page table */
	WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
		 rdev->gart.table_addr);
	WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);

	/* enable page tables */
	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT));
	tmp = RREG32_MC(RS600_MC_CNTL1);
	WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES));
	rs600_gart_tlb_flush(rdev);
	rdev->gart.ready = true;
	return 0;
}

void rs600_gart_disable(struct radeon_device *rdev)
{
	uint32_t tmp;

	/* FIXME: disable out of gart access */
	WREG32_MC(RS600_MC_PT0_CNTL, 0);
	tmp = RREG32_MC(RS600_MC_CNTL1);
	tmp &= ~RS600_ENABLE_PAGE_TABLES;
	WREG32_MC(RS600_MC_CNTL1, tmp);
	radeon_object_kunmap(rdev->gart.table.vram.robj);
	radeon_object_unpin(rdev->gart.table.vram.robj);
}

#define R600_PTE_VALID     (1 << 0)
#define R600_PTE_SYSTEM    (1 << 1)
#define R600_PTE_SNOOPED   (1 << 2)
#define R600_PTE_READABLE  (1 << 5)
#define R600_PTE_WRITEABLE (1 << 6)

int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;

	if (i < 0 || i > rdev->gart.num_gpu_pages) {
		return -EINVAL;
	}
	addr = addr & 0xFFFFFFFFFFFFF000ULL;
	addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
	addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
	writeq(addr, ((void __iomem *)ptr) + (i * 8));
	return 0;
}


/*
 * MC.
 */
void rs600_mc_disable_clients(struct radeon_device *rdev)
{
	unsigned tmp;

	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}

	tmp = RREG32(AVIVO_D1VGA_CONTROL);
	WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
	tmp = RREG32(AVIVO_D2VGA_CONTROL);
	WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);

	tmp = RREG32(AVIVO_D1CRTC_CONTROL);
	WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
	tmp = RREG32(AVIVO_D2CRTC_CONTROL);
	WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);

	/* make sure all previous write got through */
	tmp = RREG32(AVIVO_D2CRTC_CONTROL);

	mdelay(1);
}

int rs600_mc_init(struct radeon_device *rdev)
{
	uint32_t tmp;
	int r;

	if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	}

	rs600_gpu_init(rdev);
	rs600_gart_disable(rdev);

	/* Setup GPU memory space */
	rdev->mc.vram_location = 0xFFFFFFFFUL;
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
	r = radeon_mc_setup(rdev);
	if (r) {
		return r;
	}

	/* Program GPU memory space */
	/* Enable bus master */
	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
	WREG32(RADEON_BUS_CNTL, tmp);
	/* FIXME: What does AGP means for such chipset ? */
	WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF);
	/* FIXME: are this AGP reg in indirect MC range ? */
	WREG32_MC(RS600_MC_AGP_BASE, 0);
	WREG32_MC(RS600_MC_AGP_BASE_2, 0);
	rs600_mc_disable_clients(rdev);
	if (rs600_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
	tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
	tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
	WREG32_MC(RS600_MC_FB_LOCATION, tmp);
	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
	return 0;
}

void rs600_mc_fini(struct radeon_device *rdev)
{
	rs600_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
	radeon_gart_fini(rdev);
}


/*
 * Interrupts
 */
int rs600_irq_set(struct radeon_device *rdev)
{
	uint32_t tmp = 0;
	uint32_t mode_int = 0;

	if (rdev->irq.sw_int) {
		tmp |= RADEON_SW_INT_ENABLE;
	}
	if (rdev->irq.crtc_vblank_int[0]) {
		tmp |= AVIVO_DISPLAY_INT_STATUS;
		mode_int |= AVIVO_D1MODE_INT_MASK;
	}
	if (rdev->irq.crtc_vblank_int[1]) {
		tmp |= AVIVO_DISPLAY_INT_STATUS;
		mode_int |= AVIVO_D2MODE_INT_MASK;
	}
	WREG32(RADEON_GEN_INT_CNTL, tmp);
	WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
	return 0;
}

static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
{
	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
	uint32_t irq_mask = RADEON_SW_INT_TEST;

	if (irqs & AVIVO_DISPLAY_INT_STATUS) {
		*r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
		if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
			WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
		}
		if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
			WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
		}
	} else {
		*r500_disp_int = 0;
	}

	if (irqs) {
		WREG32(RADEON_GEN_INT_STATUS, irqs);
	}
	return irqs & irq_mask;
}

int rs600_irq_process(struct radeon_device *rdev)
{
	uint32_t status;
	uint32_t r500_disp_int;

	status = rs600_irq_ack(rdev, &r500_disp_int);
	if (!status && !r500_disp_int) {
		return IRQ_NONE;
	}
	while (status || r500_disp_int) {
		/* SW interrupt */
		if (status & RADEON_SW_INT_TEST) {
			radeon_fence_process(rdev);
		}
		/* Vertical blank interrupts */
		if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
			drm_handle_vblank(rdev->ddev, 0);
		}
		if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
			drm_handle_vblank(rdev->ddev, 1);
		}
		status = rs600_irq_ack(rdev, &r500_disp_int);
	}
	return IRQ_HANDLED;
}

u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
{
	if (crtc == 0)
		return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
	else
		return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
}


/*
 * Global GPU functions
 */
void rs600_disable_vga(struct radeon_device *rdev)
{
	unsigned tmp;

	WREG32(0x330, 0);
	WREG32(0x338, 0);
	tmp = RREG32(0x300);
	tmp &= ~(3 << 16);
	WREG32(0x300, tmp);
	WREG32(0x308, (1 << 8));
	WREG32(0x310, rdev->mc.vram_location);
	WREG32(0x594, 0);
}

int rs600_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;

	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32_MC(RS600_MC_STATUS);
		if (tmp & RS600_MC_STATUS_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}

void rs600_errata(struct radeon_device *rdev)
{
	rdev->pll_errata = 0;
}

void rs600_gpu_init(struct radeon_device *rdev)
{
	/* FIXME: HDP same place on rs600 ? */
	r100_hdp_reset(rdev);
	rs600_disable_vga(rdev);
	/* FIXME: is this correct ? */
	r420_pipes_init(rdev);
	if (rs600_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
}


/*
 * VRAM info.
 */
void rs600_vram_info(struct radeon_device *rdev)
{
	/* FIXME: to do or is these values sane ? */
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
}

void rs600_bandwidth_update(struct radeon_device *rdev)
{
	/* FIXME: implement, should this be like rs690 ? */
}


/*
 * Indirect registers accessor
 */
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(RS600_MC_INDEX,
	       ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0));
	r = RREG32(RS600_MC_DATA);
	return r;
}

void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RS600_MC_INDEX,
		RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 |
		((reg) & RS600_MC_ADDR_MASK));
	WREG32(RS600_MC_DATA, v);
}

int rs600_init(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
3f7dc91a DA	32	#include "rs600_reg_safe.h"
3f7dc91a DA	33
771fe6b9 JG	34	/* rs600 depends on : */
	35	void r100_hdp_reset(struct radeon_device *rdev);
	36	int r100_gui_wait_for_idle(struct radeon_device *rdev);
	37	int r300_mc_wait_for_idle(struct radeon_device *rdev);
	38	void r420_pipes_init(struct radeon_device *rdev);
	39
	40	/* This files gather functions specifics to :
	41	* rs600
	42	*
	43	* Some of these functions might be used by newer ASICs.
	44	*/
	45	void rs600_gpu_init(struct radeon_device *rdev);
	46	int rs600_mc_wait_for_idle(struct radeon_device *rdev);
	47	void rs600_disable_vga(struct radeon_device *rdev);
	48
	49
	50	/*
	51	* GART.
	52	*/
	53	void rs600_gart_tlb_flush(struct radeon_device *rdev)
	54	{
	55	uint32_t tmp;
	56
	57	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	58	tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS \| RS600_INVALIDATE_L2_CACHE);
	59	WREG32_MC(RS600_MC_PT0_CNTL, tmp);
	60
	61	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	62	tmp \|= RS600_INVALIDATE_ALL_L1_TLBS \| RS600_INVALIDATE_L2_CACHE;
	63	WREG32_MC(RS600_MC_PT0_CNTL, tmp);
	64
	65	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	66	tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS \| RS600_INVALIDATE_L2_CACHE);
	67	WREG32_MC(RS600_MC_PT0_CNTL, tmp);
	68	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
	69	}
	70
	71	int rs600_gart_enable(struct radeon_device *rdev)
	72	{
	73	uint32_t tmp;
	74	int i;
	75	int r;
	76
	77	/* Initialize common gart structure */
	78	r = radeon_gart_init(rdev);
	79	if (r) {
	80	return r;
	81	}
	82	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	83	r = radeon_gart_table_vram_alloc(rdev);
	84	if (r) {
	85	return r;
	86	}
	87	/* FIXME: setup default page */
	88	WREG32_MC(RS600_MC_PT0_CNTL,
	89	(RS600_EFFECTIVE_L2_CACHE_SIZE(6) \|
	90	RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
	91	for (i = 0; i < 19; i++) {
	92	WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i,
	93	(RS600_ENABLE_TRANSLATION_MODE_OVERRIDE \|
	94	RS600_SYSTEM_ACCESS_MODE_IN_SYS \|
	95	RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE \|
	96	RS600_EFFECTIVE_L1_CACHE_SIZE(3) \|
	97	RS600_ENABLE_FRAGMENT_PROCESSING \|
98	RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
99	}
100
101	/* System context map to GART space */
102	WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location);
103	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
104	WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp);
105
106	/* enable first context */
107	WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location);
108	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
109	WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp);
110	WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL,
111	(RS600_ENABLE_PAGE_TABLE \| RS600_PAGE_TABLE_TYPE_FLAT));
112	/* disable all other contexts */
113	for (i = 1; i < 8; i++) {
114	WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
115	}
116
117	/* setup the page table */
118	WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
119	rdev->gart.table_addr);
120	WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
121
122	/* enable page tables */
123	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
124	WREG32_MC(RS600_MC_PT0_CNTL, (tmp \| RS600_ENABLE_PT));
125	tmp = RREG32_MC(RS600_MC_CNTL1);
126	WREG32_MC(RS600_MC_CNTL1, (tmp \| RS600_ENABLE_PAGE_TABLES));
127	rs600_gart_tlb_flush(rdev);
128	rdev->gart.ready = true;
129	return 0;
130	}
131
132	void rs600_gart_disable(struct radeon_device *rdev)
133	{
134	uint32_t tmp;
135
136	/* FIXME: disable out of gart access */
137	WREG32_MC(RS600_MC_PT0_CNTL, 0);
138	tmp = RREG32_MC(RS600_MC_CNTL1);
139	tmp &= ~RS600_ENABLE_PAGE_TABLES;
140	WREG32_MC(RS600_MC_CNTL1, tmp);
141	radeon_object_kunmap(rdev->gart.table.vram.robj);
142	radeon_object_unpin(rdev->gart.table.vram.robj);
143	}
144
145	#define R600_PTE_VALID (1 << 0)
146	#define R600_PTE_SYSTEM (1 << 1)
147	#define R600_PTE_SNOOPED (1 << 2)
148	#define R600_PTE_READABLE (1 << 5)
149	#define R600_PTE_WRITEABLE (1 << 6)
150
151	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
152	{
153	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
154
155	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
156	return -EINVAL;
157	}
158	addr = addr & 0xFFFFFFFFFFFFF000ULL;
159	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;
160	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;
161	writeq(addr, ((void __iomem )ptr) + (i 8));
162	return 0;
163	}
164
165
166	/*
167	* MC.
168	*/
169	void rs600_mc_disable_clients(struct radeon_device *rdev)
170	{
171	unsigned tmp;
172
173	if (r100_gui_wait_for_idle(rdev)) {
174	printk(KERN_WARNING "Failed to wait GUI idle while "
175	"programming pipes. Bad things might happen.\n");
176	}
177
178	tmp = RREG32(AVIVO_D1VGA_CONTROL);
179	WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
180	tmp = RREG32(AVIVO_D2VGA_CONTROL);
181	WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
182
183	tmp = RREG32(AVIVO_D1CRTC_CONTROL);
184	WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
185	tmp = RREG32(AVIVO_D2CRTC_CONTROL);
186	WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
187
188	/* make sure all previous write got through */
189	tmp = RREG32(AVIVO_D2CRTC_CONTROL);
190
191	mdelay(1);
192	}
193
194	int rs600_mc_init(struct radeon_device *rdev)
195	{
196	uint32_t tmp;
197	int r;
198
199	if (r100_debugfs_rbbm_init(rdev)) {
200	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
201	}
202
203	rs600_gpu_init(rdev);
204	rs600_gart_disable(rdev);
205
206	/* Setup GPU memory space */
207	rdev->mc.vram_location = 0xFFFFFFFFUL;
208	rdev->mc.gtt_location = 0xFFFFFFFFUL;
209	r = radeon_mc_setup(rdev);
210	if (r) {
211	return r;
212	}
213
214	/* Program GPU memory space */
215	/* Enable bus master */
216	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
217	WREG32(RADEON_BUS_CNTL, tmp);
218	/* FIXME: What does AGP means for such chipset ? */
219	WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF);
220	/* FIXME: are this AGP reg in indirect MC range ? */
221	WREG32_MC(RS600_MC_AGP_BASE, 0);
222	WREG32_MC(RS600_MC_AGP_BASE_2, 0);
223	rs600_mc_disable_clients(rdev);
224	if (rs600_mc_wait_for_idle(rdev)) {
225	printk(KERN_WARNING "Failed to wait MC idle while "
226	"programming pipes. Bad things might happen.\n");
227	}
7a50f01a	228	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
771fe6b9 JG	229	tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
	230	tmp \|= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
	231	WREG32_MC(RS600_MC_FB_LOCATION, tmp);
	232	WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
	233	return 0;
	234	}
	235
	236	void rs600_mc_fini(struct radeon_device *rdev)
	237	{
	238	rs600_gart_disable(rdev);
	239	radeon_gart_table_vram_free(rdev);
	240	radeon_gart_fini(rdev);
	241	}
	242
	243
7ed220d7 MD	244	/*
	245	* Interrupts
	246	*/
	247	int rs600_irq_set(struct radeon_device *rdev)
	248	{
	249	uint32_t tmp = 0;
	250	uint32_t mode_int = 0;
	251
	252	if (rdev->irq.sw_int) {
	253	tmp \|= RADEON_SW_INT_ENABLE;
	254	}
	255	if (rdev->irq.crtc_vblank_int[0]) {
	256	tmp \|= AVIVO_DISPLAY_INT_STATUS;
	257	mode_int \|= AVIVO_D1MODE_INT_MASK;
	258	}
	259	if (rdev->irq.crtc_vblank_int[1]) {
	260	tmp \|= AVIVO_DISPLAY_INT_STATUS;
	261	mode_int \|= AVIVO_D2MODE_INT_MASK;
	262	}
	263	WREG32(RADEON_GEN_INT_CNTL, tmp);
	264	WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
	265	return 0;
	266	}
	267
	268	static inline uint32_t rs600_irq_ack(struct radeon_device rdev, u32 r500_disp_int)
	269	{
	270	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
	271	uint32_t irq_mask = RADEON_SW_INT_TEST;
	272
	273	if (irqs & AVIVO_DISPLAY_INT_STATUS) {
	274	*r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
	275	if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
	276	WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
	277	}
	278	if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
	279	WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
	280	}
	281	} else {
	282	*r500_disp_int = 0;
	283	}
	284
	285	if (irqs) {
	286	WREG32(RADEON_GEN_INT_STATUS, irqs);
	287	}
	288	return irqs & irq_mask;
	289	}
	290
	291	int rs600_irq_process(struct radeon_device *rdev)
	292	{
	293	uint32_t status;
	294	uint32_t r500_disp_int;
	295
	296	status = rs600_irq_ack(rdev, &r500_disp_int);
	297	if (!status && !r500_disp_int) {
	298	return IRQ_NONE;
	299	}
	300	while (status \|\| r500_disp_int) {
	301	/* SW interrupt */
	302	if (status & RADEON_SW_INT_TEST) {
	303	radeon_fence_process(rdev);
	304	}
	305	/* Vertical blank interrupts */
	306	if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
	307	drm_handle_vblank(rdev->ddev, 0);
308	}
309	if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
310	drm_handle_vblank(rdev->ddev, 1);
311	}
312	status = rs600_irq_ack(rdev, &r500_disp_int);
313	}
314	return IRQ_HANDLED;
315	}
316
317	u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
318	{
319	if (crtc == 0)
320	return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
321	else
322	return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
323	}
324
325
771fe6b9 JG	326	/*
	327	* Global GPU functions
	328	*/
	329	void rs600_disable_vga(struct radeon_device *rdev)
	330	{
	331	unsigned tmp;
	332
	333	WREG32(0x330, 0);
	334	WREG32(0x338, 0);
	335	tmp = RREG32(0x300);
	336	tmp &= ~(3 << 16);
	337	WREG32(0x300, tmp);
	338	WREG32(0x308, (1 << 8));
	339	WREG32(0x310, rdev->mc.vram_location);
	340	WREG32(0x594, 0);
	341	}
	342
	343	int rs600_mc_wait_for_idle(struct radeon_device *rdev)
	344	{
	345	unsigned i;
	346	uint32_t tmp;
	347
	348	for (i = 0; i < rdev->usec_timeout; i++) {
	349	/* read MC_STATUS */
	350	tmp = RREG32_MC(RS600_MC_STATUS);
	351	if (tmp & RS600_MC_STATUS_IDLE) {
	352	return 0;
	353	}
	354	DRM_UDELAY(1);
	355	}
	356	return -1;
	357	}
	358
	359	void rs600_errata(struct radeon_device *rdev)
	360	{
	361	rdev->pll_errata = 0;
	362	}
	363
	364	void rs600_gpu_init(struct radeon_device *rdev)
	365	{
	366	/* FIXME: HDP same place on rs600 ? */
	367	r100_hdp_reset(rdev);
	368	rs600_disable_vga(rdev);
	369	/* FIXME: is this correct ? */
	370	r420_pipes_init(rdev);
	371	if (rs600_mc_wait_for_idle(rdev)) {
	372	printk(KERN_WARNING "Failed to wait MC idle while "
	373	"programming pipes. Bad things might happen.\n");
	374	}
	375	}
	376
	377
	378	/*
	379	* VRAM info.
	380	*/
	381	void rs600_vram_info(struct radeon_device *rdev)
	382	{
	383	/* FIXME: to do or is these values sane ? */
	384	rdev->mc.vram_is_ddr = true;
	385	rdev->mc.vram_width = 128;
	386	}
	387
c93bb85b JG	388	void rs600_bandwidth_update(struct radeon_device *rdev)
	389	{
	390	/* FIXME: implement, should this be like rs690 ? */
	391	}
	392
771fe6b9 JG	393
	394	/*
	395	* Indirect registers accessor
	396	*/
	397	uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
	398	{
	399	uint32_t r;
	400
	401	WREG32(RS600_MC_INDEX,
	402	((reg & RS600_MC_ADDR_MASK) \| RS600_MC_IND_CITF_ARB0));
	403	r = RREG32(RS600_MC_DATA);
	404	return r;
	405	}
	406
	407	void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
	408	{
	409	WREG32(RS600_MC_INDEX,
	410	RS600_MC_IND_WR_EN \| RS600_MC_IND_CITF_ARB0 \|
	411	((reg) & RS600_MC_ADDR_MASK));
	412	WREG32(RS600_MC_DATA, v);
	413	}
3f7dc91a DA	414
	415	int rs600_init(struct radeon_device *rdev)
	416	{
	417	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	418	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
	419	return 0;
	420	}