Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
c010f800 JG |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * | |
30 | * This file gather function specific to RS600 which is the IGP of | |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 | |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are | |
33 | * the avivo one, bios is an atombios, 3D block are the one of the | |
34 | * R4XX family. The GART is different from the RS400 one and is very | |
35 | * close to the one of the R600 family (R600 likely being an evolution | |
36 | * of the RS600 GART block). | |
37 | */ | |
771fe6b9 | 38 | #include "drmP.h" |
771fe6b9 | 39 | #include "radeon.h" |
c010f800 JG |
40 | #include "atom.h" |
41 | #include "rs600d.h" | |
771fe6b9 | 42 | |
3f7dc91a DA |
43 | #include "rs600_reg_safe.h" |
44 | ||
771fe6b9 JG |
45 | void rs600_gpu_init(struct radeon_device *rdev); |
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); | |
771fe6b9 | 47 | |
64bffd03 DA |
48 | int rs600_mc_init(struct radeon_device *rdev) |
49 | { | |
50 | /* read back the MC value from the hw */ | |
64bffd03 | 51 | int r; |
22dd5013 | 52 | u32 tmp; |
64bffd03 | 53 | |
22dd5013 AD |
54 | /* Setup GPU memory space */ |
55 | tmp = RREG32_MC(R_000004_MC_FB_LOCATION); | |
56 | rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; | |
64bffd03 DA |
57 | rdev->mc.gtt_location = 0xffffffffUL; |
58 | r = radeon_mc_setup(rdev); | |
59 | if (r) | |
60 | return r; | |
61 | return 0; | |
62 | } | |
dcfdd408 AD |
63 | |
64 | /* hpd for digital panel detect/disconnect */ | |
65 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
66 | { | |
67 | u32 tmp; | |
68 | bool connected = false; | |
69 | ||
70 | switch (hpd) { | |
71 | case RADEON_HPD_1: | |
72 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); | |
73 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) | |
74 | connected = true; | |
75 | break; | |
76 | case RADEON_HPD_2: | |
77 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); | |
78 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) | |
79 | connected = true; | |
80 | break; | |
81 | default: | |
82 | break; | |
83 | } | |
84 | return connected; | |
85 | } | |
86 | ||
87 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
88 | enum radeon_hpd_id hpd) | |
89 | { | |
90 | u32 tmp; | |
91 | bool connected = rs600_hpd_sense(rdev, hpd); | |
92 | ||
93 | switch (hpd) { | |
94 | case RADEON_HPD_1: | |
95 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
96 | if (connected) | |
97 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); | |
98 | else | |
99 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); | |
100 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
101 | break; | |
102 | case RADEON_HPD_2: | |
103 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
104 | if (connected) | |
105 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); | |
106 | else | |
107 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); | |
108 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
109 | break; | |
110 | default: | |
111 | break; | |
112 | } | |
113 | } | |
114 | ||
115 | void rs600_hpd_init(struct radeon_device *rdev) | |
116 | { | |
117 | struct drm_device *dev = rdev->ddev; | |
118 | struct drm_connector *connector; | |
119 | ||
120 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
121 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
122 | switch (radeon_connector->hpd.hpd) { | |
123 | case RADEON_HPD_1: | |
124 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, | |
125 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); | |
126 | rdev->irq.hpd[0] = true; | |
127 | break; | |
128 | case RADEON_HPD_2: | |
129 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, | |
130 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); | |
131 | rdev->irq.hpd[1] = true; | |
132 | break; | |
133 | default: | |
134 | break; | |
135 | } | |
136 | } | |
137 | rs600_irq_set(rdev); | |
138 | } | |
139 | ||
140 | void rs600_hpd_fini(struct radeon_device *rdev) | |
141 | { | |
142 | struct drm_device *dev = rdev->ddev; | |
143 | struct drm_connector *connector; | |
144 | ||
145 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
146 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
147 | switch (radeon_connector->hpd.hpd) { | |
148 | case RADEON_HPD_1: | |
149 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, | |
150 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); | |
151 | rdev->irq.hpd[0] = false; | |
152 | break; | |
153 | case RADEON_HPD_2: | |
154 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, | |
155 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); | |
156 | rdev->irq.hpd[1] = false; | |
157 | break; | |
158 | default: | |
159 | break; | |
160 | } | |
161 | } | |
162 | } | |
163 | ||
771fe6b9 JG |
164 | /* |
165 | * GART. | |
166 | */ | |
167 | void rs600_gart_tlb_flush(struct radeon_device *rdev) | |
168 | { | |
169 | uint32_t tmp; | |
170 | ||
c010f800 JG |
171 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
172 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
173 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 174 | |
c010f800 JG |
175 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
176 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); | |
177 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 178 | |
c010f800 JG |
179 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
180 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
181 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
182 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); | |
771fe6b9 JG |
183 | } |
184 | ||
4aac0473 | 185 | int rs600_gart_init(struct radeon_device *rdev) |
771fe6b9 | 186 | { |
771fe6b9 JG |
187 | int r; |
188 | ||
4aac0473 JG |
189 | if (rdev->gart.table.vram.robj) { |
190 | WARN(1, "RS600 GART already initialized.\n"); | |
191 | return 0; | |
192 | } | |
771fe6b9 JG |
193 | /* Initialize common gart structure */ |
194 | r = radeon_gart_init(rdev); | |
195 | if (r) { | |
196 | return r; | |
197 | } | |
198 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; | |
4aac0473 JG |
199 | return radeon_gart_table_vram_alloc(rdev); |
200 | } | |
201 | ||
202 | int rs600_gart_enable(struct radeon_device *rdev) | |
203 | { | |
c010f800 | 204 | u32 tmp; |
4aac0473 JG |
205 | int r, i; |
206 | ||
207 | if (rdev->gart.table.vram.robj == NULL) { | |
208 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
209 | return -EINVAL; | |
771fe6b9 | 210 | } |
4aac0473 JG |
211 | r = radeon_gart_table_vram_pin(rdev); |
212 | if (r) | |
213 | return r; | |
c010f800 JG |
214 | /* Enable bus master */ |
215 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; | |
216 | WREG32(R_00004C_BUS_CNTL, tmp); | |
771fe6b9 | 217 | /* FIXME: setup default page */ |
c010f800 | 218 | WREG32_MC(R_000100_MC_PT0_CNTL, |
4f15d24a AD |
219 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
220 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); | |
221 | ||
771fe6b9 | 222 | for (i = 0; i < 19; i++) { |
c010f800 | 223 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
4f15d24a AD |
224 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
225 | S_00016C_SYSTEM_ACCESS_MODE_MASK( | |
226 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | | |
227 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( | |
228 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | | |
229 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | | |
230 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | | |
231 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); | |
771fe6b9 | 232 | } |
771fe6b9 | 233 | /* enable first context */ |
c010f800 | 234 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
4f15d24a AD |
235 | S_000102_ENABLE_PAGE_TABLE(1) | |
236 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); | |
237 | ||
771fe6b9 | 238 | /* disable all other contexts */ |
4f15d24a | 239 | for (i = 1; i < 8; i++) |
c010f800 | 240 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
771fe6b9 JG |
241 | |
242 | /* setup the page table */ | |
c010f800 | 243 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
4f15d24a AD |
244 | rdev->gart.table_addr); |
245 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); | |
246 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); | |
c010f800 | 247 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
771fe6b9 | 248 | |
4f15d24a AD |
249 | /* System context maps to VRAM space */ |
250 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); | |
251 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); | |
252 | ||
771fe6b9 | 253 | /* enable page tables */ |
c010f800 JG |
254 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
255 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); | |
256 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
257 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); | |
771fe6b9 JG |
258 | rs600_gart_tlb_flush(rdev); |
259 | rdev->gart.ready = true; | |
260 | return 0; | |
261 | } | |
262 | ||
263 | void rs600_gart_disable(struct radeon_device *rdev) | |
264 | { | |
4c788679 JG |
265 | u32 tmp; |
266 | int r; | |
771fe6b9 JG |
267 | |
268 | /* FIXME: disable out of gart access */ | |
c010f800 JG |
269 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
270 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
271 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); | |
4aac0473 | 272 | if (rdev->gart.table.vram.robj) { |
4c788679 JG |
273 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
274 | if (r == 0) { | |
275 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
276 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
277 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
278 | } | |
4aac0473 JG |
279 | } |
280 | } | |
281 | ||
282 | void rs600_gart_fini(struct radeon_device *rdev) | |
283 | { | |
284 | rs600_gart_disable(rdev); | |
285 | radeon_gart_table_vram_free(rdev); | |
286 | radeon_gart_fini(rdev); | |
771fe6b9 JG |
287 | } |
288 | ||
289 | #define R600_PTE_VALID (1 << 0) | |
290 | #define R600_PTE_SYSTEM (1 << 1) | |
291 | #define R600_PTE_SNOOPED (1 << 2) | |
292 | #define R600_PTE_READABLE (1 << 5) | |
293 | #define R600_PTE_WRITEABLE (1 << 6) | |
294 | ||
295 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
296 | { | |
297 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | |
298 | ||
299 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
300 | return -EINVAL; | |
301 | } | |
302 | addr = addr & 0xFFFFFFFFFFFFF000ULL; | |
303 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
304 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
305 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); | |
306 | return 0; | |
307 | } | |
308 | ||
7ed220d7 MD |
309 | int rs600_irq_set(struct radeon_device *rdev) |
310 | { | |
311 | uint32_t tmp = 0; | |
312 | uint32_t mode_int = 0; | |
dcfdd408 AD |
313 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
314 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | |
315 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & | |
316 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | |
7ed220d7 MD |
317 | |
318 | if (rdev->irq.sw_int) { | |
c010f800 | 319 | tmp |= S_000040_SW_INT_EN(1); |
7ed220d7 MD |
320 | } |
321 | if (rdev->irq.crtc_vblank_int[0]) { | |
c010f800 | 322 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
7ed220d7 MD |
323 | } |
324 | if (rdev->irq.crtc_vblank_int[1]) { | |
c010f800 | 325 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
7ed220d7 | 326 | } |
dcfdd408 AD |
327 | if (rdev->irq.hpd[0]) { |
328 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | |
329 | } | |
330 | if (rdev->irq.hpd[1]) { | |
331 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | |
332 | } | |
c010f800 JG |
333 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
334 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); | |
dcfdd408 AD |
335 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
336 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
7ed220d7 MD |
337 | return 0; |
338 | } | |
339 | ||
340 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) | |
341 | { | |
01ceae8e JG |
342 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
343 | uint32_t irq_mask = ~C_000044_SW_INT; | |
dcfdd408 | 344 | u32 tmp; |
c010f800 | 345 | |
01ceae8e | 346 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
c010f800 JG |
347 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
348 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { | |
349 | WREG32(R_006534_D1MODE_VBLANK_STATUS, | |
350 | S_006534_D1MODE_VBLANK_ACK(1)); | |
7ed220d7 | 351 | } |
c010f800 JG |
352 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
353 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, | |
354 | S_006D34_D2MODE_VBLANK_ACK(1)); | |
7ed220d7 | 355 | } |
dcfdd408 AD |
356 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
357 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
358 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); | |
359 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
360 | } | |
361 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { | |
362 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
363 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); | |
364 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
365 | } | |
7ed220d7 MD |
366 | } else { |
367 | *r500_disp_int = 0; | |
368 | } | |
369 | ||
370 | if (irqs) { | |
01ceae8e | 371 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
7ed220d7 MD |
372 | } |
373 | return irqs & irq_mask; | |
374 | } | |
375 | ||
ac447df4 JG |
376 | void rs600_irq_disable(struct radeon_device *rdev) |
377 | { | |
378 | u32 tmp; | |
379 | ||
380 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
381 | WREG32(R_006540_DxMODE_INT_MASK, 0); | |
382 | /* Wait and acknowledge irq */ | |
383 | mdelay(1); | |
384 | rs600_irq_ack(rdev, &tmp); | |
385 | } | |
386 | ||
7ed220d7 MD |
387 | int rs600_irq_process(struct radeon_device *rdev) |
388 | { | |
3e5cb98d | 389 | uint32_t status, msi_rearm; |
7ed220d7 MD |
390 | uint32_t r500_disp_int; |
391 | ||
392 | status = rs600_irq_ack(rdev, &r500_disp_int); | |
393 | if (!status && !r500_disp_int) { | |
394 | return IRQ_NONE; | |
395 | } | |
396 | while (status || r500_disp_int) { | |
397 | /* SW interrupt */ | |
c010f800 | 398 | if (G_000040_SW_INT_EN(status)) |
7ed220d7 | 399 | radeon_fence_process(rdev); |
7ed220d7 | 400 | /* Vertical blank interrupts */ |
c010f800 | 401 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) |
7ed220d7 | 402 | drm_handle_vblank(rdev->ddev, 0); |
c010f800 | 403 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) |
7ed220d7 | 404 | drm_handle_vblank(rdev->ddev, 1); |
dcfdd408 AD |
405 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { |
406 | DRM_INFO("HPD1\n"); | |
407 | } | |
408 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) { | |
409 | DRM_INFO("HPD2\n"); | |
410 | } | |
7ed220d7 MD |
411 | status = rs600_irq_ack(rdev, &r500_disp_int); |
412 | } | |
3e5cb98d AD |
413 | if (rdev->msi_enabled) { |
414 | switch (rdev->family) { | |
415 | case CHIP_RS600: | |
416 | case CHIP_RS690: | |
417 | case CHIP_RS740: | |
418 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; | |
419 | WREG32(RADEON_BUS_CNTL, msi_rearm); | |
420 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); | |
421 | break; | |
422 | default: | |
423 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; | |
424 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); | |
425 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); | |
426 | break; | |
427 | } | |
428 | } | |
7ed220d7 MD |
429 | return IRQ_HANDLED; |
430 | } | |
431 | ||
432 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
433 | { | |
434 | if (crtc == 0) | |
c010f800 | 435 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
7ed220d7 | 436 | else |
c010f800 | 437 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
7ed220d7 MD |
438 | } |
439 | ||
771fe6b9 JG |
440 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
441 | { | |
442 | unsigned i; | |
771fe6b9 JG |
443 | |
444 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c010f800 | 445 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
771fe6b9 | 446 | return 0; |
c010f800 | 447 | udelay(1); |
771fe6b9 JG |
448 | } |
449 | return -1; | |
450 | } | |
451 | ||
771fe6b9 JG |
452 | void rs600_gpu_init(struct radeon_device *rdev) |
453 | { | |
771fe6b9 | 454 | r100_hdp_reset(rdev); |
771fe6b9 | 455 | r420_pipes_init(rdev); |
c010f800 JG |
456 | /* Wait for mc idle */ |
457 | if (rs600_mc_wait_for_idle(rdev)) | |
458 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
771fe6b9 JG |
459 | } |
460 | ||
771fe6b9 JG |
461 | void rs600_vram_info(struct radeon_device *rdev) |
462 | { | |
771fe6b9 JG |
463 | rdev->mc.vram_is_ddr = true; |
464 | rdev->mc.vram_width = 128; | |
722f2943 AD |
465 | |
466 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | |
467 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
468 | ||
469 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | |
470 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
0088dbdb AD |
471 | |
472 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) | |
473 | rdev->mc.mc_vram_size = rdev->mc.aper_size; | |
474 | ||
475 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) | |
476 | rdev->mc.real_vram_size = rdev->mc.aper_size; | |
771fe6b9 JG |
477 | } |
478 | ||
c93bb85b JG |
479 | void rs600_bandwidth_update(struct radeon_device *rdev) |
480 | { | |
481 | /* FIXME: implement, should this be like rs690 ? */ | |
482 | } | |
483 | ||
771fe6b9 JG |
484 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
485 | { | |
c010f800 JG |
486 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
487 | S_000070_MC_IND_CITF_ARB0(1)); | |
488 | return RREG32(R_000074_MC_IND_DATA); | |
771fe6b9 JG |
489 | } |
490 | ||
491 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
492 | { | |
c010f800 JG |
493 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
494 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); | |
495 | WREG32(R_000074_MC_IND_DATA, v); | |
496 | } | |
497 | ||
498 | void rs600_debugfs(struct radeon_device *rdev) | |
499 | { | |
500 | if (r100_debugfs_rbbm_init(rdev)) | |
501 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
771fe6b9 | 502 | } |
3f7dc91a | 503 | |
3bc68535 | 504 | void rs600_set_safe_registers(struct radeon_device *rdev) |
3f7dc91a DA |
505 | { |
506 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; | |
507 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); | |
3bc68535 JG |
508 | } |
509 | ||
c010f800 JG |
510 | static void rs600_mc_program(struct radeon_device *rdev) |
511 | { | |
512 | struct rv515_mc_save save; | |
513 | ||
514 | /* Stops all mc clients */ | |
515 | rv515_mc_stop(rdev, &save); | |
516 | ||
517 | /* Wait for mc idle */ | |
518 | if (rs600_mc_wait_for_idle(rdev)) | |
519 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
520 | ||
521 | /* FIXME: What does AGP means for such chipset ? */ | |
522 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); | |
523 | WREG32_MC(R_000006_AGP_BASE, 0); | |
524 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
525 | /* Program MC */ | |
526 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
527 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
528 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
529 | WREG32(R_000134_HDP_FB_LOCATION, | |
530 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
531 | ||
532 | rv515_mc_resume(rdev, &save); | |
533 | } | |
534 | ||
535 | static int rs600_startup(struct radeon_device *rdev) | |
536 | { | |
537 | int r; | |
538 | ||
539 | rs600_mc_program(rdev); | |
540 | /* Resume clock */ | |
541 | rv515_clock_startup(rdev); | |
542 | /* Initialize GPU configuration (# pipes, ...) */ | |
543 | rs600_gpu_init(rdev); | |
544 | /* Initialize GART (initialize after TTM so we can allocate | |
545 | * memory through TTM but finalize after TTM) */ | |
546 | r = rs600_gart_enable(rdev); | |
547 | if (r) | |
548 | return r; | |
549 | /* Enable IRQ */ | |
c010f800 JG |
550 | rs600_irq_set(rdev); |
551 | /* 1M ring buffer */ | |
552 | r = r100_cp_init(rdev, 1024 * 1024); | |
553 | if (r) { | |
554 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
555 | return r; | |
556 | } | |
557 | r = r100_wb_init(rdev); | |
558 | if (r) | |
559 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
560 | r = r100_ib_init(rdev); | |
561 | if (r) { | |
562 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
563 | return r; | |
564 | } | |
565 | return 0; | |
566 | } | |
567 | ||
568 | int rs600_resume(struct radeon_device *rdev) | |
569 | { | |
570 | /* Make sur GART are not working */ | |
571 | rs600_gart_disable(rdev); | |
572 | /* Resume clock before doing reset */ | |
573 | rv515_clock_startup(rdev); | |
574 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
575 | if (radeon_gpu_reset(rdev)) { | |
576 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
577 | RREG32(R_000E40_RBBM_STATUS), | |
578 | RREG32(R_0007C0_CP_STAT)); | |
579 | } | |
580 | /* post */ | |
581 | atom_asic_init(rdev->mode_info.atom_context); | |
582 | /* Resume clock after posting */ | |
583 | rv515_clock_startup(rdev); | |
584 | return rs600_startup(rdev); | |
585 | } | |
586 | ||
587 | int rs600_suspend(struct radeon_device *rdev) | |
588 | { | |
589 | r100_cp_disable(rdev); | |
590 | r100_wb_disable(rdev); | |
ac447df4 | 591 | rs600_irq_disable(rdev); |
c010f800 JG |
592 | rs600_gart_disable(rdev); |
593 | return 0; | |
594 | } | |
595 | ||
596 | void rs600_fini(struct radeon_device *rdev) | |
597 | { | |
598 | rs600_suspend(rdev); | |
599 | r100_cp_fini(rdev); | |
600 | r100_wb_fini(rdev); | |
601 | r100_ib_fini(rdev); | |
602 | radeon_gem_fini(rdev); | |
603 | rs600_gart_fini(rdev); | |
604 | radeon_irq_kms_fini(rdev); | |
605 | radeon_fence_driver_fini(rdev); | |
4c788679 | 606 | radeon_bo_fini(rdev); |
c010f800 JG |
607 | radeon_atombios_fini(rdev); |
608 | kfree(rdev->bios); | |
609 | rdev->bios = NULL; | |
610 | } | |
611 | ||
3bc68535 JG |
612 | int rs600_init(struct radeon_device *rdev) |
613 | { | |
c010f800 JG |
614 | int r; |
615 | ||
c010f800 JG |
616 | /* Disable VGA */ |
617 | rv515_vga_render_disable(rdev); | |
618 | /* Initialize scratch registers */ | |
619 | radeon_scratch_init(rdev); | |
620 | /* Initialize surface registers */ | |
621 | radeon_surface_init(rdev); | |
622 | /* BIOS */ | |
623 | if (!radeon_get_bios(rdev)) { | |
624 | if (ASIC_IS_AVIVO(rdev)) | |
625 | return -EINVAL; | |
626 | } | |
627 | if (rdev->is_atom_bios) { | |
628 | r = radeon_atombios_init(rdev); | |
629 | if (r) | |
630 | return r; | |
631 | } else { | |
632 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); | |
633 | return -EINVAL; | |
634 | } | |
635 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
636 | if (radeon_gpu_reset(rdev)) { | |
637 | dev_warn(rdev->dev, | |
638 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
639 | RREG32(R_000E40_RBBM_STATUS), | |
640 | RREG32(R_0007C0_CP_STAT)); | |
641 | } | |
642 | /* check if cards are posted or not */ | |
72542d77 DA |
643 | if (radeon_boot_test_post_card(rdev) == false) |
644 | return -EINVAL; | |
645 | ||
c010f800 JG |
646 | /* Initialize clocks */ |
647 | radeon_get_clock_info(rdev->ddev); | |
7433874e RM |
648 | /* Initialize power management */ |
649 | radeon_pm_init(rdev); | |
c010f800 JG |
650 | /* Get vram informations */ |
651 | rs600_vram_info(rdev); | |
652 | /* Initialize memory controller (also test AGP) */ | |
64bffd03 | 653 | r = rs600_mc_init(rdev); |
c010f800 JG |
654 | if (r) |
655 | return r; | |
656 | rs600_debugfs(rdev); | |
657 | /* Fence driver */ | |
658 | r = radeon_fence_driver_init(rdev); | |
659 | if (r) | |
660 | return r; | |
661 | r = radeon_irq_kms_init(rdev); | |
662 | if (r) | |
663 | return r; | |
664 | /* Memory manager */ | |
4c788679 | 665 | r = radeon_bo_init(rdev); |
c010f800 JG |
666 | if (r) |
667 | return r; | |
668 | r = rs600_gart_init(rdev); | |
669 | if (r) | |
670 | return r; | |
671 | rs600_set_safe_registers(rdev); | |
672 | rdev->accel_working = true; | |
673 | r = rs600_startup(rdev); | |
674 | if (r) { | |
675 | /* Somethings want wront with the accel init stop accel */ | |
676 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
677 | rs600_suspend(rdev); | |
678 | r100_cp_fini(rdev); | |
679 | r100_wb_fini(rdev); | |
680 | r100_ib_fini(rdev); | |
681 | rs600_gart_fini(rdev); | |
682 | radeon_irq_kms_fini(rdev); | |
683 | rdev->accel_working = false; | |
684 | } | |
3f7dc91a DA |
685 | return 0; |
686 | } |