projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: Add asic hook for dma copy to r200 cards.
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
771fe6b9 38#include "drmP.h"
771fe6b9 39#include "radeon.h"
c010f800
JG		 40#include "atom.h"
41#include "rs600d.h"
771fe6b9 42
3f7dc91a
DA		 43#include "rs600_reg_safe.h"
44
771fe6b9
JG		 45void rs600_gpu_init(struct radeon_device *rdev);
46int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 47
64bffd03
DA		 48int rs600_mc_init(struct radeon_device *rdev)
49{
50 /* read back the MC value from the hw */
64bffd03 51 int r;
22dd5013 52 u32 tmp;
64bffd03 53
22dd5013
AD		 54 /* Setup GPU memory space */
55 tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
56 rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
64bffd03
DA		 57 rdev->mc.gtt_location = 0xffffffffUL;
58 r = radeon_mc_setup(rdev);
06b6476d 59 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
64bffd03
DA		 60 if (r)
61 return r;
62 return 0;
63}
dcfdd408
AD		 64
65/* hpd for digital panel detect/disconnect */
66bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
67{
68 u32 tmp;
69 bool connected = false;
70
71 switch (hpd) {
72 case RADEON_HPD_1:
73 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
74 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
75 connected = true;
76 break;
77 case RADEON_HPD_2:
78 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
79 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void rs600_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = rs600_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
97 if (connected)
98 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
99 else
100 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
101 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
105 if (connected)
106 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
107 else
108 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
109 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void rs600_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
126 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
127 rdev->irq.hpd[0] = true;
128 break;
129 case RADEON_HPD_2:
130 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
131 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
132 rdev->irq.hpd[1] = true;
133 break;
134 default:
135 break;
136 }
137 }
003e69f9
JG		 138 if (rdev->irq.installed)
139 rs600_irq_set(rdev);
dcfdd408
AD		 140}
141
142void rs600_hpd_fini(struct radeon_device *rdev)
143{
144 struct drm_device *dev = rdev->ddev;
145 struct drm_connector *connector;
146
147 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
148 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
149 switch (radeon_connector->hpd.hpd) {
150 case RADEON_HPD_1:
151 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
152 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
153 rdev->irq.hpd[0] = false;
154 break;
155 case RADEON_HPD_2:
156 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
157 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
158 rdev->irq.hpd[1] = false;
159 break;
160 default:
161 break;
162 }
163 }
164}
165
771fe6b9
JG		 166/*
167 * GART.
168 */
169void rs600_gart_tlb_flush(struct radeon_device *rdev)
170{
171 uint32_t tmp;
172
c010f800
JG		 173 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
174 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
175 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 176
c010f800
JG		 177 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
178 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
179 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 180
c010f800
JG		 181 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
182 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
183 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
184 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 185}
186
4aac0473 187int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 188{
771fe6b9
JG		 189 int r;
190
4aac0473
JG		 191 if (rdev->gart.table.vram.robj) {
192 WARN(1, "RS600 GART already initialized.\n");
193 return 0;
194 }
771fe6b9
JG		 195 /* Initialize common gart structure */
196 r = radeon_gart_init(rdev);
197 if (r) {
198 return r;
199 }
200 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 201 return radeon_gart_table_vram_alloc(rdev);
202}
203
204int rs600_gart_enable(struct radeon_device *rdev)
205{
c010f800 206 u32 tmp;
4aac0473
JG		 207 int r, i;
208
209 if (rdev->gart.table.vram.robj == NULL) {
210 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
211 return -EINVAL;
771fe6b9 212 }
4aac0473
JG		 213 r = radeon_gart_table_vram_pin(rdev);
214 if (r)
215 return r;
82568565 216 radeon_gart_restore(rdev);
c010f800
JG		 217 /* Enable bus master */
218 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
219 WREG32(R_00004C_BUS_CNTL, tmp);
771fe6b9 220 /* FIXME: setup default page */
c010f800 221 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 222 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
223 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
224
771fe6b9 225 for (i = 0; i < 19; i++) {
c010f800 226 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 227 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
228 S_00016C_SYSTEM_ACCESS_MODE_MASK(
229 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
230 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
231 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
232 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
233 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
234 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 235 }
771fe6b9 236 /* enable first context */
c010f800 237 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 238 S_000102_ENABLE_PAGE_TABLE(1) |
239 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
240
771fe6b9 241 /* disable all other contexts */
4f15d24a 242 for (i = 1; i < 8; i++)
c010f800 243 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 244
245 /* setup the page table */
c010f800 246 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 247 rdev->gart.table_addr);
248 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
249 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 250 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 251
4f15d24a
AD		 252 /* System context maps to VRAM space */
253 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
254 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
255
771fe6b9 256 /* enable page tables */
c010f800
JG		 257 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
258 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
259 tmp = RREG32_MC(R_000009_MC_CNTL1);
260 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9
JG		 261 rs600_gart_tlb_flush(rdev);
262 rdev->gart.ready = true;
263 return 0;
264}
265
266void rs600_gart_disable(struct radeon_device *rdev)
267{
4c788679
JG		 268 u32 tmp;
269 int r;
771fe6b9
JG		 270
271 /* FIXME: disable out of gart access */
c010f800
JG		 272 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
273 tmp = RREG32_MC(R_000009_MC_CNTL1);
274 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
4aac0473 275 if (rdev->gart.table.vram.robj) {
4c788679
JG		 276 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
277 if (r == 0) {
278 radeon_bo_kunmap(rdev->gart.table.vram.robj);
279 radeon_bo_unpin(rdev->gart.table.vram.robj);
280 radeon_bo_unreserve(rdev->gart.table.vram.robj);
281 }
4aac0473
JG		 282 }
283}
284
285void rs600_gart_fini(struct radeon_device *rdev)
286{
287 rs600_gart_disable(rdev);
288 radeon_gart_table_vram_free(rdev);
289 radeon_gart_fini(rdev);
771fe6b9
JG		 290}
291
292#define R600_PTE_VALID (1 << 0)
293#define R600_PTE_SYSTEM (1 << 1)
294#define R600_PTE_SNOOPED (1 << 2)
295#define R600_PTE_READABLE (1 << 5)
296#define R600_PTE_WRITEABLE (1 << 6)
297
298int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
299{
300 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
301
302 if (i < 0 || i > rdev->gart.num_gpu_pages) {
303 return -EINVAL;
304 }
305 addr = addr & 0xFFFFFFFFFFFFF000ULL;
306 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
307 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
308 writeq(addr, ((void __iomem *)ptr) + (i * 8));
309 return 0;
310}
311
7ed220d7
MD		 312int rs600_irq_set(struct radeon_device *rdev)
313{
314 uint32_t tmp = 0;
315 uint32_t mode_int = 0;
dcfdd408
AD		 316 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
317 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
318 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
319 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
7ed220d7 320
003e69f9
JG		 321 if (!rdev->irq.installed) {
322 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
323 WREG32(R_000040_GEN_INT_CNTL, 0);
324 return -EINVAL;
325 }
7ed220d7 326 if (rdev->irq.sw_int) {
c010f800 327 tmp |= S_000040_SW_INT_EN(1);
7ed220d7
MD		 328 }
329 if (rdev->irq.crtc_vblank_int[0]) {
c010f800 330 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7
MD		 331 }
332 if (rdev->irq.crtc_vblank_int[1]) {
c010f800 333 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 334 }
dcfdd408
AD		 335 if (rdev->irq.hpd[0]) {
336 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
337 }
338 if (rdev->irq.hpd[1]) {
339 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
340 }
c010f800
JG		 341 WREG32(R_000040_GEN_INT_CNTL, tmp);
342 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 343 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
344 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
7ed220d7
MD		 345 return 0;
346}
347
348static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
349{
01ceae8e
JG		 350 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
351 uint32_t irq_mask = ~C_000044_SW_INT;
dcfdd408 352 u32 tmp;
c010f800 353
01ceae8e 354 if (G_000044_DISPLAY_INT_STAT(irqs)) {
c010f800
JG		 355 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
356 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
357 WREG32(R_006534_D1MODE_VBLANK_STATUS,
358 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 359 }
c010f800
JG		 360 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
361 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
362 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 363 }
dcfdd408
AD		 364 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
365 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
366 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
367 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
368 }
369 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
370 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
371 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
372 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
373 }
7ed220d7
MD		 374 } else {
375 *r500_disp_int = 0;
376 }
377
378 if (irqs) {
01ceae8e 379 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 380 }
381 return irqs & irq_mask;
382}
383
ac447df4
JG		 384void rs600_irq_disable(struct radeon_device *rdev)
385{
386 u32 tmp;
387
388 WREG32(R_000040_GEN_INT_CNTL, 0);
389 WREG32(R_006540_DxMODE_INT_MASK, 0);
390 /* Wait and acknowledge irq */
391 mdelay(1);
392 rs600_irq_ack(rdev, &tmp);
393}
394
7ed220d7
MD		 395int rs600_irq_process(struct radeon_device *rdev)
396{
3e5cb98d 397 uint32_t status, msi_rearm;
7ed220d7 398 uint32_t r500_disp_int;
d4877cf2 399 bool queue_hotplug = false;
7ed220d7
MD		 400
401 status = rs600_irq_ack(rdev, &r500_disp_int);
402 if (!status && !r500_disp_int) {
403 return IRQ_NONE;
404 }
405 while (status || r500_disp_int) {
406 /* SW interrupt */
43b19f16 407 if (G_000044_SW_INT(status))
7ed220d7 408 radeon_fence_process(rdev);
7ed220d7 409 /* Vertical blank interrupts */
c913e23a 410 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 411 drm_handle_vblank(rdev->ddev, 0);
73a6d3fc 412 wake_up(&rdev->irq.vblank_queue);
c913e23a
RM		 413 }
414 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 415 drm_handle_vblank(rdev->ddev, 1);
73a6d3fc 416 wake_up(&rdev->irq.vblank_queue);
c913e23a 417 }
dcfdd408 418 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 419 queue_hotplug = true;
420 DRM_DEBUG("HPD1\n");
dcfdd408
AD		 421 }
422 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 423 queue_hotplug = true;
424 DRM_DEBUG("HPD2\n");
dcfdd408 425 }
7ed220d7
MD		 426 status = rs600_irq_ack(rdev, &r500_disp_int);
427 }
d4877cf2
AD		 428 if (queue_hotplug)
429 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 430 if (rdev->msi_enabled) {
431 switch (rdev->family) {
432 case CHIP_RS600:
433 case CHIP_RS690:
434 case CHIP_RS740:
435 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
436 WREG32(RADEON_BUS_CNTL, msi_rearm);
437 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
438 break;
439 default:
440 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
441 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
442 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
443 break;
444 }
445 }
7ed220d7
MD		 446 return IRQ_HANDLED;
447}
448
449u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
450{
451 if (crtc == 0)
c010f800 452 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 453 else
c010f800 454 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 455}
456
771fe6b9
JG		 457int rs600_mc_wait_for_idle(struct radeon_device *rdev)
458{
459 unsigned i;
771fe6b9
JG		 460
461 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 462 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 463 return 0;
c010f800 464 udelay(1);
771fe6b9
JG		 465 }
466 return -1;
467}
468
771fe6b9
JG		 469void rs600_gpu_init(struct radeon_device *rdev)
470{
771fe6b9 471 r100_hdp_reset(rdev);
771fe6b9 472 r420_pipes_init(rdev);
c010f800
JG		 473 /* Wait for mc idle */
474 if (rs600_mc_wait_for_idle(rdev))
475 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 476}
477
771fe6b9
JG		 478void rs600_vram_info(struct radeon_device *rdev)
479{
771fe6b9
JG		 480 rdev->mc.vram_is_ddr = true;
481 rdev->mc.vram_width = 128;
722f2943
AD		 482
483 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
484 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
485
486 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
487 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
0088dbdb
AD		 488
489 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
490 rdev->mc.mc_vram_size = rdev->mc.aper_size;
491
492 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
493 rdev->mc.real_vram_size = rdev->mc.aper_size;
771fe6b9
JG		 494}
495
c93bb85b
JG		 496void rs600_bandwidth_update(struct radeon_device *rdev)
497{
498 /* FIXME: implement, should this be like rs690 ? */
499}
500
771fe6b9
JG		 501uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
502{
c010f800
JG		 503 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
504 S_000070_MC_IND_CITF_ARB0(1));
505 return RREG32(R_000074_MC_IND_DATA);
771fe6b9
JG		 506}
507
508void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
509{
c010f800
JG		 510 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
511 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
512 WREG32(R_000074_MC_IND_DATA, v);
513}
514
515void rs600_debugfs(struct radeon_device *rdev)
516{
517 if (r100_debugfs_rbbm_init(rdev))
518 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 519}
3f7dc91a 520
3bc68535 521void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 522{
523 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
524 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 525}
526
c010f800
JG		 527static void rs600_mc_program(struct radeon_device *rdev)
528{
529 struct rv515_mc_save save;
530
531 /* Stops all mc clients */
532 rv515_mc_stop(rdev, &save);
533
534 /* Wait for mc idle */
535 if (rs600_mc_wait_for_idle(rdev))
536 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
537
538 /* FIXME: What does AGP means for such chipset ? */
539 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
540 WREG32_MC(R_000006_AGP_BASE, 0);
541 WREG32_MC(R_000007_AGP_BASE_2, 0);
542 /* Program MC */
543 WREG32_MC(R_000004_MC_FB_LOCATION,
544 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
545 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
546 WREG32(R_000134_HDP_FB_LOCATION,
547 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
548
549 rv515_mc_resume(rdev, &save);
550}
551
552static int rs600_startup(struct radeon_device *rdev)
553{
554 int r;
555
556 rs600_mc_program(rdev);
557 /* Resume clock */
558 rv515_clock_startup(rdev);
559 /* Initialize GPU configuration (# pipes, ...) */
560 rs600_gpu_init(rdev);
561 /* Initialize GART (initialize after TTM so we can allocate
562 * memory through TTM but finalize after TTM) */
563 r = rs600_gart_enable(rdev);
564 if (r)
565 return r;
566 /* Enable IRQ */
c010f800 567 rs600_irq_set(rdev);
cafe6609 568 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 569 /* 1M ring buffer */
570 r = r100_cp_init(rdev, 1024 * 1024);
571 if (r) {
572 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
573 return r;
574 }
575 r = r100_wb_init(rdev);
576 if (r)
577 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
578 r = r100_ib_init(rdev);
579 if (r) {
580 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
581 return r;
582 }
583 return 0;
584}
585
586int rs600_resume(struct radeon_device *rdev)
587{
588 /* Make sur GART are not working */
589 rs600_gart_disable(rdev);
590 /* Resume clock before doing reset */
591 rv515_clock_startup(rdev);
592 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
593 if (radeon_gpu_reset(rdev)) {
594 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
595 RREG32(R_000E40_RBBM_STATUS),
596 RREG32(R_0007C0_CP_STAT));
597 }
598 /* post */
599 atom_asic_init(rdev->mode_info.atom_context);
600 /* Resume clock after posting */
601 rv515_clock_startup(rdev);
550e2d92
DA		 602 /* Initialize surface registers */
603 radeon_surface_init(rdev);
c010f800
JG		 604 return rs600_startup(rdev);
605}
606
607int rs600_suspend(struct radeon_device *rdev)
608{
609 r100_cp_disable(rdev);
610 r100_wb_disable(rdev);
ac447df4 611 rs600_irq_disable(rdev);
c010f800
JG		 612 rs600_gart_disable(rdev);
613 return 0;
614}
615
616void rs600_fini(struct radeon_device *rdev)
617{
c010f800
JG		 618 r100_cp_fini(rdev);
619 r100_wb_fini(rdev);
620 r100_ib_fini(rdev);
621 radeon_gem_fini(rdev);
622 rs600_gart_fini(rdev);
623 radeon_irq_kms_fini(rdev);
624 radeon_fence_driver_fini(rdev);
4c788679 625 radeon_bo_fini(rdev);
c010f800
JG		 626 radeon_atombios_fini(rdev);
627 kfree(rdev->bios);
628 rdev->bios = NULL;
629}
630
3bc68535
JG		 631int rs600_init(struct radeon_device *rdev)
632{
c010f800
JG		 633 int r;
634
c010f800
JG		 635 /* Disable VGA */
636 rv515_vga_render_disable(rdev);
637 /* Initialize scratch registers */
638 radeon_scratch_init(rdev);
639 /* Initialize surface registers */
640 radeon_surface_init(rdev);
641 /* BIOS */
642 if (!radeon_get_bios(rdev)) {
643 if (ASIC_IS_AVIVO(rdev))
644 return -EINVAL;
645 }
646 if (rdev->is_atom_bios) {
647 r = radeon_atombios_init(rdev);
648 if (r)
649 return r;
650 } else {
651 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
652 return -EINVAL;
653 }
654 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
655 if (radeon_gpu_reset(rdev)) {
656 dev_warn(rdev->dev,
657 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
658 RREG32(R_000E40_RBBM_STATUS),
659 RREG32(R_0007C0_CP_STAT));
660 }
661 /* check if cards are posted or not */
72542d77
DA		 662 if (radeon_boot_test_post_card(rdev) == false)
663 return -EINVAL;
664
c010f800
JG		 665 /* Initialize clocks */
666 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 667 /* Initialize power management */
668 radeon_pm_init(rdev);
c010f800
JG		 669 /* Get vram informations */
670 rs600_vram_info(rdev);
671 /* Initialize memory controller (also test AGP) */
64bffd03 672 r = rs600_mc_init(rdev);
c010f800
JG		 673 if (r)
674 return r;
675 rs600_debugfs(rdev);
676 /* Fence driver */
677 r = radeon_fence_driver_init(rdev);
678 if (r)
679 return r;
680 r = radeon_irq_kms_init(rdev);
681 if (r)
682 return r;
683 /* Memory manager */
4c788679 684 r = radeon_bo_init(rdev);
c010f800
JG		 685 if (r)
686 return r;
687 r = rs600_gart_init(rdev);
688 if (r)
689 return r;
690 rs600_set_safe_registers(rdev);
691 rdev->accel_working = true;
692 r = rs600_startup(rdev);
693 if (r) {
694 /* Somethings want wront with the accel init stop accel */
695 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800
JG		 696 r100_cp_fini(rdev);
697 r100_wb_fini(rdev);
698 r100_ib_fini(rdev);
699 rs600_gart_fini(rdev);
700 radeon_irq_kms_fini(rdev);
701 rdev->accel_working = false;
702 }
3f7dc91a
DA		 703 return 0;
704}
Linux kernel - Deliverables
This page took 0.147963 seconds and 5 git commands to generate.