Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
c010f800 JG |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * | |
30 | * This file gather function specific to RS600 which is the IGP of | |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 | |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are | |
33 | * the avivo one, bios is an atombios, 3D block are the one of the | |
34 | * R4XX family. The GART is different from the RS400 one and is very | |
35 | * close to the one of the R600 family (R600 likely being an evolution | |
36 | * of the RS600 GART block). | |
37 | */ | |
771fe6b9 | 38 | #include "drmP.h" |
771fe6b9 | 39 | #include "radeon.h" |
c010f800 JG |
40 | #include "atom.h" |
41 | #include "rs600d.h" | |
771fe6b9 | 42 | |
3f7dc91a DA |
43 | #include "rs600_reg_safe.h" |
44 | ||
771fe6b9 JG |
45 | void rs600_gpu_init(struct radeon_device *rdev); |
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); | |
771fe6b9 | 47 | |
771fe6b9 JG |
48 | /* |
49 | * GART. | |
50 | */ | |
51 | void rs600_gart_tlb_flush(struct radeon_device *rdev) | |
52 | { | |
53 | uint32_t tmp; | |
54 | ||
c010f800 JG |
55 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
56 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
57 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 58 | |
c010f800 JG |
59 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
60 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); | |
61 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 62 | |
c010f800 JG |
63 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
64 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
65 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
66 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); | |
771fe6b9 JG |
67 | } |
68 | ||
4aac0473 | 69 | int rs600_gart_init(struct radeon_device *rdev) |
771fe6b9 | 70 | { |
771fe6b9 JG |
71 | int r; |
72 | ||
4aac0473 JG |
73 | if (rdev->gart.table.vram.robj) { |
74 | WARN(1, "RS600 GART already initialized.\n"); | |
75 | return 0; | |
76 | } | |
771fe6b9 JG |
77 | /* Initialize common gart structure */ |
78 | r = radeon_gart_init(rdev); | |
79 | if (r) { | |
80 | return r; | |
81 | } | |
82 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; | |
4aac0473 JG |
83 | return radeon_gart_table_vram_alloc(rdev); |
84 | } | |
85 | ||
86 | int rs600_gart_enable(struct radeon_device *rdev) | |
87 | { | |
c010f800 | 88 | u32 tmp; |
4aac0473 JG |
89 | int r, i; |
90 | ||
91 | if (rdev->gart.table.vram.robj == NULL) { | |
92 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
93 | return -EINVAL; | |
771fe6b9 | 94 | } |
4aac0473 JG |
95 | r = radeon_gart_table_vram_pin(rdev); |
96 | if (r) | |
97 | return r; | |
c010f800 JG |
98 | /* Enable bus master */ |
99 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; | |
100 | WREG32(R_00004C_BUS_CNTL, tmp); | |
771fe6b9 | 101 | /* FIXME: setup default page */ |
c010f800 JG |
102 | WREG32_MC(R_000100_MC_PT0_CNTL, |
103 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | | |
104 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); | |
771fe6b9 | 105 | for (i = 0; i < 19; i++) { |
c010f800 JG |
106 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
107 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | | |
108 | S_00016C_SYSTEM_ACCESS_MODE_MASK( | |
109 | V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) | | |
110 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( | |
111 | V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) | | |
112 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) | | |
113 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | | |
114 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1)); | |
771fe6b9 JG |
115 | } |
116 | ||
117 | /* System context map to GART space */ | |
c010f800 JG |
118 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start); |
119 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end); | |
771fe6b9 JG |
120 | |
121 | /* enable first context */ | |
c010f800 JG |
122 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
123 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); | |
124 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, | |
125 | S_000102_ENABLE_PAGE_TABLE(1) | | |
126 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); | |
771fe6b9 JG |
127 | /* disable all other contexts */ |
128 | for (i = 1; i < 8; i++) { | |
c010f800 | 129 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
771fe6b9 JG |
130 | } |
131 | ||
132 | /* setup the page table */ | |
c010f800 JG |
133 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
134 | rdev->gart.table_addr); | |
135 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); | |
771fe6b9 JG |
136 | |
137 | /* enable page tables */ | |
c010f800 JG |
138 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
139 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); | |
140 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
141 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); | |
771fe6b9 JG |
142 | rs600_gart_tlb_flush(rdev); |
143 | rdev->gart.ready = true; | |
144 | return 0; | |
145 | } | |
146 | ||
147 | void rs600_gart_disable(struct radeon_device *rdev) | |
148 | { | |
149 | uint32_t tmp; | |
150 | ||
151 | /* FIXME: disable out of gart access */ | |
c010f800 JG |
152 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
153 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
154 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); | |
4aac0473 JG |
155 | if (rdev->gart.table.vram.robj) { |
156 | radeon_object_kunmap(rdev->gart.table.vram.robj); | |
157 | radeon_object_unpin(rdev->gart.table.vram.robj); | |
158 | } | |
159 | } | |
160 | ||
161 | void rs600_gart_fini(struct radeon_device *rdev) | |
162 | { | |
163 | rs600_gart_disable(rdev); | |
164 | radeon_gart_table_vram_free(rdev); | |
165 | radeon_gart_fini(rdev); | |
771fe6b9 JG |
166 | } |
167 | ||
168 | #define R600_PTE_VALID (1 << 0) | |
169 | #define R600_PTE_SYSTEM (1 << 1) | |
170 | #define R600_PTE_SNOOPED (1 << 2) | |
171 | #define R600_PTE_READABLE (1 << 5) | |
172 | #define R600_PTE_WRITEABLE (1 << 6) | |
173 | ||
174 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
175 | { | |
176 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | |
177 | ||
178 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
179 | return -EINVAL; | |
180 | } | |
181 | addr = addr & 0xFFFFFFFFFFFFF000ULL; | |
182 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
183 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
184 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); | |
185 | return 0; | |
186 | } | |
187 | ||
7ed220d7 MD |
188 | int rs600_irq_set(struct radeon_device *rdev) |
189 | { | |
190 | uint32_t tmp = 0; | |
191 | uint32_t mode_int = 0; | |
192 | ||
193 | if (rdev->irq.sw_int) { | |
c010f800 | 194 | tmp |= S_000040_SW_INT_EN(1); |
7ed220d7 MD |
195 | } |
196 | if (rdev->irq.crtc_vblank_int[0]) { | |
c010f800 | 197 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
7ed220d7 MD |
198 | } |
199 | if (rdev->irq.crtc_vblank_int[1]) { | |
c010f800 | 200 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
7ed220d7 | 201 | } |
c010f800 JG |
202 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
203 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); | |
7ed220d7 MD |
204 | return 0; |
205 | } | |
206 | ||
207 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) | |
208 | { | |
c010f800 JG |
209 | uint32_t irqs = RREG32(R_000040_GEN_INT_CNTL); |
210 | uint32_t irq_mask = ~C_000040_SW_INT_EN; | |
211 | ||
212 | if (G_000040_DISPLAY_INT_STATUS(irqs)) { | |
213 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); | |
214 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { | |
215 | WREG32(R_006534_D1MODE_VBLANK_STATUS, | |
216 | S_006534_D1MODE_VBLANK_ACK(1)); | |
7ed220d7 | 217 | } |
c010f800 JG |
218 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
219 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, | |
220 | S_006D34_D2MODE_VBLANK_ACK(1)); | |
7ed220d7 MD |
221 | } |
222 | } else { | |
223 | *r500_disp_int = 0; | |
224 | } | |
225 | ||
226 | if (irqs) { | |
c010f800 | 227 | WREG32(R_000040_GEN_INT_CNTL, irqs); |
7ed220d7 MD |
228 | } |
229 | return irqs & irq_mask; | |
230 | } | |
231 | ||
232 | int rs600_irq_process(struct radeon_device *rdev) | |
233 | { | |
234 | uint32_t status; | |
235 | uint32_t r500_disp_int; | |
236 | ||
237 | status = rs600_irq_ack(rdev, &r500_disp_int); | |
238 | if (!status && !r500_disp_int) { | |
239 | return IRQ_NONE; | |
240 | } | |
241 | while (status || r500_disp_int) { | |
242 | /* SW interrupt */ | |
c010f800 | 243 | if (G_000040_SW_INT_EN(status)) |
7ed220d7 | 244 | radeon_fence_process(rdev); |
7ed220d7 | 245 | /* Vertical blank interrupts */ |
c010f800 | 246 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) |
7ed220d7 | 247 | drm_handle_vblank(rdev->ddev, 0); |
c010f800 | 248 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) |
7ed220d7 | 249 | drm_handle_vblank(rdev->ddev, 1); |
7ed220d7 MD |
250 | status = rs600_irq_ack(rdev, &r500_disp_int); |
251 | } | |
252 | return IRQ_HANDLED; | |
253 | } | |
254 | ||
255 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
256 | { | |
257 | if (crtc == 0) | |
c010f800 | 258 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
7ed220d7 | 259 | else |
c010f800 | 260 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
7ed220d7 MD |
261 | } |
262 | ||
771fe6b9 JG |
263 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
264 | { | |
265 | unsigned i; | |
771fe6b9 JG |
266 | |
267 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c010f800 | 268 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
771fe6b9 | 269 | return 0; |
c010f800 | 270 | udelay(1); |
771fe6b9 JG |
271 | } |
272 | return -1; | |
273 | } | |
274 | ||
771fe6b9 JG |
275 | void rs600_gpu_init(struct radeon_device *rdev) |
276 | { | |
277 | /* FIXME: HDP same place on rs600 ? */ | |
278 | r100_hdp_reset(rdev); | |
771fe6b9 JG |
279 | /* FIXME: is this correct ? */ |
280 | r420_pipes_init(rdev); | |
c010f800 JG |
281 | /* Wait for mc idle */ |
282 | if (rs600_mc_wait_for_idle(rdev)) | |
283 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
771fe6b9 JG |
284 | } |
285 | ||
771fe6b9 JG |
286 | void rs600_vram_info(struct radeon_device *rdev) |
287 | { | |
288 | /* FIXME: to do or is these values sane ? */ | |
289 | rdev->mc.vram_is_ddr = true; | |
290 | rdev->mc.vram_width = 128; | |
291 | } | |
292 | ||
c93bb85b JG |
293 | void rs600_bandwidth_update(struct radeon_device *rdev) |
294 | { | |
295 | /* FIXME: implement, should this be like rs690 ? */ | |
296 | } | |
297 | ||
771fe6b9 JG |
298 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
299 | { | |
c010f800 JG |
300 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
301 | S_000070_MC_IND_CITF_ARB0(1)); | |
302 | return RREG32(R_000074_MC_IND_DATA); | |
771fe6b9 JG |
303 | } |
304 | ||
305 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
306 | { | |
c010f800 JG |
307 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
308 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); | |
309 | WREG32(R_000074_MC_IND_DATA, v); | |
310 | } | |
311 | ||
312 | void rs600_debugfs(struct radeon_device *rdev) | |
313 | { | |
314 | if (r100_debugfs_rbbm_init(rdev)) | |
315 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
771fe6b9 | 316 | } |
3f7dc91a | 317 | |
3bc68535 | 318 | void rs600_set_safe_registers(struct radeon_device *rdev) |
3f7dc91a DA |
319 | { |
320 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; | |
321 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); | |
3bc68535 JG |
322 | } |
323 | ||
c010f800 JG |
324 | static void rs600_mc_program(struct radeon_device *rdev) |
325 | { | |
326 | struct rv515_mc_save save; | |
327 | ||
328 | /* Stops all mc clients */ | |
329 | rv515_mc_stop(rdev, &save); | |
330 | ||
331 | /* Wait for mc idle */ | |
332 | if (rs600_mc_wait_for_idle(rdev)) | |
333 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
334 | ||
335 | /* FIXME: What does AGP means for such chipset ? */ | |
336 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); | |
337 | WREG32_MC(R_000006_AGP_BASE, 0); | |
338 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
339 | /* Program MC */ | |
340 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
341 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
342 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
343 | WREG32(R_000134_HDP_FB_LOCATION, | |
344 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
345 | ||
346 | rv515_mc_resume(rdev, &save); | |
347 | } | |
348 | ||
349 | static int rs600_startup(struct radeon_device *rdev) | |
350 | { | |
351 | int r; | |
352 | ||
353 | rs600_mc_program(rdev); | |
354 | /* Resume clock */ | |
355 | rv515_clock_startup(rdev); | |
356 | /* Initialize GPU configuration (# pipes, ...) */ | |
357 | rs600_gpu_init(rdev); | |
358 | /* Initialize GART (initialize after TTM so we can allocate | |
359 | * memory through TTM but finalize after TTM) */ | |
360 | r = rs600_gart_enable(rdev); | |
361 | if (r) | |
362 | return r; | |
363 | /* Enable IRQ */ | |
364 | rdev->irq.sw_int = true; | |
365 | rs600_irq_set(rdev); | |
366 | /* 1M ring buffer */ | |
367 | r = r100_cp_init(rdev, 1024 * 1024); | |
368 | if (r) { | |
369 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
370 | return r; | |
371 | } | |
372 | r = r100_wb_init(rdev); | |
373 | if (r) | |
374 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
375 | r = r100_ib_init(rdev); | |
376 | if (r) { | |
377 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
378 | return r; | |
379 | } | |
380 | return 0; | |
381 | } | |
382 | ||
383 | int rs600_resume(struct radeon_device *rdev) | |
384 | { | |
385 | /* Make sur GART are not working */ | |
386 | rs600_gart_disable(rdev); | |
387 | /* Resume clock before doing reset */ | |
388 | rv515_clock_startup(rdev); | |
389 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
390 | if (radeon_gpu_reset(rdev)) { | |
391 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
392 | RREG32(R_000E40_RBBM_STATUS), | |
393 | RREG32(R_0007C0_CP_STAT)); | |
394 | } | |
395 | /* post */ | |
396 | atom_asic_init(rdev->mode_info.atom_context); | |
397 | /* Resume clock after posting */ | |
398 | rv515_clock_startup(rdev); | |
399 | return rs600_startup(rdev); | |
400 | } | |
401 | ||
402 | int rs600_suspend(struct radeon_device *rdev) | |
403 | { | |
404 | r100_cp_disable(rdev); | |
405 | r100_wb_disable(rdev); | |
406 | r100_irq_disable(rdev); | |
407 | rs600_gart_disable(rdev); | |
408 | return 0; | |
409 | } | |
410 | ||
411 | void rs600_fini(struct radeon_device *rdev) | |
412 | { | |
413 | rs600_suspend(rdev); | |
414 | r100_cp_fini(rdev); | |
415 | r100_wb_fini(rdev); | |
416 | r100_ib_fini(rdev); | |
417 | radeon_gem_fini(rdev); | |
418 | rs600_gart_fini(rdev); | |
419 | radeon_irq_kms_fini(rdev); | |
420 | radeon_fence_driver_fini(rdev); | |
421 | radeon_object_fini(rdev); | |
422 | radeon_atombios_fini(rdev); | |
423 | kfree(rdev->bios); | |
424 | rdev->bios = NULL; | |
425 | } | |
426 | ||
3bc68535 JG |
427 | int rs600_init(struct radeon_device *rdev) |
428 | { | |
c010f800 JG |
429 | int r; |
430 | ||
c010f800 JG |
431 | /* Disable VGA */ |
432 | rv515_vga_render_disable(rdev); | |
433 | /* Initialize scratch registers */ | |
434 | radeon_scratch_init(rdev); | |
435 | /* Initialize surface registers */ | |
436 | radeon_surface_init(rdev); | |
437 | /* BIOS */ | |
438 | if (!radeon_get_bios(rdev)) { | |
439 | if (ASIC_IS_AVIVO(rdev)) | |
440 | return -EINVAL; | |
441 | } | |
442 | if (rdev->is_atom_bios) { | |
443 | r = radeon_atombios_init(rdev); | |
444 | if (r) | |
445 | return r; | |
446 | } else { | |
447 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); | |
448 | return -EINVAL; | |
449 | } | |
450 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
451 | if (radeon_gpu_reset(rdev)) { | |
452 | dev_warn(rdev->dev, | |
453 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
454 | RREG32(R_000E40_RBBM_STATUS), | |
455 | RREG32(R_0007C0_CP_STAT)); | |
456 | } | |
457 | /* check if cards are posted or not */ | |
458 | if (!radeon_card_posted(rdev) && rdev->bios) { | |
459 | DRM_INFO("GPU not posted. posting now...\n"); | |
460 | atom_asic_init(rdev->mode_info.atom_context); | |
461 | } | |
462 | /* Initialize clocks */ | |
463 | radeon_get_clock_info(rdev->ddev); | |
464 | /* Get vram informations */ | |
465 | rs600_vram_info(rdev); | |
466 | /* Initialize memory controller (also test AGP) */ | |
467 | r = r420_mc_init(rdev); | |
468 | if (r) | |
469 | return r; | |
470 | rs600_debugfs(rdev); | |
471 | /* Fence driver */ | |
472 | r = radeon_fence_driver_init(rdev); | |
473 | if (r) | |
474 | return r; | |
475 | r = radeon_irq_kms_init(rdev); | |
476 | if (r) | |
477 | return r; | |
478 | /* Memory manager */ | |
479 | r = radeon_object_init(rdev); | |
480 | if (r) | |
481 | return r; | |
482 | r = rs600_gart_init(rdev); | |
483 | if (r) | |
484 | return r; | |
485 | rs600_set_safe_registers(rdev); | |
486 | rdev->accel_working = true; | |
487 | r = rs600_startup(rdev); | |
488 | if (r) { | |
489 | /* Somethings want wront with the accel init stop accel */ | |
490 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
491 | rs600_suspend(rdev); | |
492 | r100_cp_fini(rdev); | |
493 | r100_wb_fini(rdev); | |
494 | r100_ib_fini(rdev); | |
495 | rs600_gart_fini(rdev); | |
496 | radeon_irq_kms_fini(rdev); | |
497 | rdev->accel_working = false; | |
498 | } | |
3f7dc91a DA |
499 | return 0; |
500 | } |