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drm/radeon/kms: simplify & improve GPU reset V2
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
771fe6b9 38#include "drmP.h"
771fe6b9 39#include "radeon.h"
e6990375 40#include "radeon_asic.h"
c010f800
JG		 41#include "atom.h"
42#include "rs600d.h"
771fe6b9 43
3f7dc91a
DA		 44#include "rs600_reg_safe.h"
45
771fe6b9
JG		 46void rs600_gpu_init(struct radeon_device *rdev);
47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 48
dcfdd408
AD		 49/* hpd for digital panel detect/disconnect */
50bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
51{
52 u32 tmp;
53 bool connected = false;
54
55 switch (hpd) {
56 case RADEON_HPD_1:
57 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
58 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
59 connected = true;
60 break;
61 case RADEON_HPD_2:
62 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
63 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
64 connected = true;
65 break;
66 default:
67 break;
68 }
69 return connected;
70}
71
72void rs600_hpd_set_polarity(struct radeon_device *rdev,
73 enum radeon_hpd_id hpd)
74{
75 u32 tmp;
76 bool connected = rs600_hpd_sense(rdev, hpd);
77
78 switch (hpd) {
79 case RADEON_HPD_1:
80 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
81 if (connected)
82 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
83 else
84 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
85 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
86 break;
87 case RADEON_HPD_2:
88 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
89 if (connected)
90 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
91 else
92 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
93 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
94 break;
95 default:
96 break;
97 }
98}
99
100void rs600_hpd_init(struct radeon_device *rdev)
101{
102 struct drm_device *dev = rdev->ddev;
103 struct drm_connector *connector;
104
105 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
106 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
107 switch (radeon_connector->hpd.hpd) {
108 case RADEON_HPD_1:
109 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
110 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
111 rdev->irq.hpd[0] = true;
112 break;
113 case RADEON_HPD_2:
114 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
115 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
116 rdev->irq.hpd[1] = true;
117 break;
118 default:
119 break;
120 }
121 }
003e69f9
JG		 122 if (rdev->irq.installed)
123 rs600_irq_set(rdev);
dcfdd408
AD		 124}
125
126void rs600_hpd_fini(struct radeon_device *rdev)
127{
128 struct drm_device *dev = rdev->ddev;
129 struct drm_connector *connector;
130
131 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
132 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
133 switch (radeon_connector->hpd.hpd) {
134 case RADEON_HPD_1:
135 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
136 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
137 rdev->irq.hpd[0] = false;
138 break;
139 case RADEON_HPD_2:
140 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
141 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
142 rdev->irq.hpd[1] = false;
143 break;
144 default:
145 break;
146 }
147 }
148}
149
90aca4d2
JG		 150void rs600_bm_disable(struct radeon_device *rdev)
151{
152 u32 tmp;
153
154 /* disable bus mastering */
155 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
156 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
157 mdelay(1);
158}
159
160int rs600_asic_reset(struct radeon_device *rdev)
161{
162 u32 status, tmp;
163
164 struct rv515_mc_save save;
165
166 /* Stops all mc clients */
167 rv515_mc_stop(rdev, &save);
168 status = RREG32(R_000E40_RBBM_STATUS);
169 if (!G_000E40_GUI_ACTIVE(status)) {
170 return 0;
171 }
172 status = RREG32(R_000E40_RBBM_STATUS);
173 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
174 /* stop CP */
175 WREG32(RADEON_CP_CSQ_CNTL, 0);
176 tmp = RREG32(RADEON_CP_RB_CNTL);
177 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
178 WREG32(RADEON_CP_RB_RPTR_WR, 0);
179 WREG32(RADEON_CP_RB_WPTR, 0);
180 WREG32(RADEON_CP_RB_CNTL, tmp);
181 pci_save_state(rdev->pdev);
182 /* disable bus mastering */
183 rs600_bm_disable(rdev);
184 /* reset GA+VAP */
185 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
186 S_0000F0_SOFT_RESET_GA(1));
187 RREG32(R_0000F0_RBBM_SOFT_RESET);
188 mdelay(500);
189 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
190 mdelay(1);
191 status = RREG32(R_000E40_RBBM_STATUS);
192 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
193 /* reset CP */
194 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
195 RREG32(R_0000F0_RBBM_SOFT_RESET);
196 mdelay(500);
197 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
198 mdelay(1);
199 status = RREG32(R_000E40_RBBM_STATUS);
200 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
201 /* reset MC */
202 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
203 RREG32(R_0000F0_RBBM_SOFT_RESET);
204 mdelay(500);
205 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
206 mdelay(1);
207 status = RREG32(R_000E40_RBBM_STATUS);
208 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
209 /* restore PCI & busmastering */
210 pci_restore_state(rdev->pdev);
211 /* Check if GPU is idle */
212 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
213 dev_err(rdev->dev, "failed to reset GPU\n");
214 rdev->gpu_lockup = true;
215 return -1;
216 }
217 rv515_mc_resume(rdev, &save);
218 dev_info(rdev->dev, "GPU reset succeed\n");
219 return 0;
220}
221
771fe6b9
JG		 222/*
223 * GART.
224 */
225void rs600_gart_tlb_flush(struct radeon_device *rdev)
226{
227 uint32_t tmp;
228
c010f800
JG		 229 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
230 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
231 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 232
c010f800
JG		 233 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
234 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
235 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 236
c010f800
JG		 237 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
238 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
239 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
240 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 241}
242
4aac0473 243int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 244{
771fe6b9
JG		 245 int r;
246
4aac0473
JG		 247 if (rdev->gart.table.vram.robj) {
248 WARN(1, "RS600 GART already initialized.\n");
249 return 0;
250 }
771fe6b9
JG		 251 /* Initialize common gart structure */
252 r = radeon_gart_init(rdev);
253 if (r) {
254 return r;
255 }
256 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 257 return radeon_gart_table_vram_alloc(rdev);
258}
259
260int rs600_gart_enable(struct radeon_device *rdev)
261{
c010f800 262 u32 tmp;
4aac0473
JG		 263 int r, i;
264
265 if (rdev->gart.table.vram.robj == NULL) {
266 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
267 return -EINVAL;
771fe6b9 268 }
4aac0473
JG		 269 r = radeon_gart_table_vram_pin(rdev);
270 if (r)
271 return r;
82568565 272 radeon_gart_restore(rdev);
c010f800
JG		 273 /* Enable bus master */
274 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
275 WREG32(R_00004C_BUS_CNTL, tmp);
771fe6b9 276 /* FIXME: setup default page */
c010f800 277 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 278 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
279 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
280
771fe6b9 281 for (i = 0; i < 19; i++) {
c010f800 282 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 283 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
284 S_00016C_SYSTEM_ACCESS_MODE_MASK(
285 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
286 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
287 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
288 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
289 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
290 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 291 }
771fe6b9 292 /* enable first context */
c010f800 293 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 294 S_000102_ENABLE_PAGE_TABLE(1) |
295 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
296
771fe6b9 297 /* disable all other contexts */
4f15d24a 298 for (i = 1; i < 8; i++)
c010f800 299 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 300
301 /* setup the page table */
c010f800 302 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 303 rdev->gart.table_addr);
304 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
305 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 306 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 307
4f15d24a
AD		 308 /* System context maps to VRAM space */
309 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
310 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
311
771fe6b9 312 /* enable page tables */
c010f800
JG		 313 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
314 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
315 tmp = RREG32_MC(R_000009_MC_CNTL1);
316 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9
JG		 317 rs600_gart_tlb_flush(rdev);
318 rdev->gart.ready = true;
319 return 0;
320}
321
322void rs600_gart_disable(struct radeon_device *rdev)
323{
4c788679
JG		 324 u32 tmp;
325 int r;
771fe6b9
JG		 326
327 /* FIXME: disable out of gart access */
c010f800
JG		 328 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
329 tmp = RREG32_MC(R_000009_MC_CNTL1);
330 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
4aac0473 331 if (rdev->gart.table.vram.robj) {
4c788679
JG		 332 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
333 if (r == 0) {
334 radeon_bo_kunmap(rdev->gart.table.vram.robj);
335 radeon_bo_unpin(rdev->gart.table.vram.robj);
336 radeon_bo_unreserve(rdev->gart.table.vram.robj);
337 }
4aac0473
JG		 338 }
339}
340
341void rs600_gart_fini(struct radeon_device *rdev)
342{
f9274562 343 radeon_gart_fini(rdev);
4aac0473
JG		 344 rs600_gart_disable(rdev);
345 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 346}
347
348#define R600_PTE_VALID (1 << 0)
349#define R600_PTE_SYSTEM (1 << 1)
350#define R600_PTE_SNOOPED (1 << 2)
351#define R600_PTE_READABLE (1 << 5)
352#define R600_PTE_WRITEABLE (1 << 6)
353
354int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
355{
356 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
357
358 if (i < 0 || i > rdev->gart.num_gpu_pages) {
359 return -EINVAL;
360 }
361 addr = addr & 0xFFFFFFFFFFFFF000ULL;
362 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
363 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
364 writeq(addr, ((void __iomem *)ptr) + (i * 8));
365 return 0;
366}
367
7ed220d7
MD		 368int rs600_irq_set(struct radeon_device *rdev)
369{
370 uint32_t tmp = 0;
371 uint32_t mode_int = 0;
dcfdd408
AD		 372 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
373 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
374 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
375 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
7ed220d7 376
003e69f9
JG		 377 if (!rdev->irq.installed) {
378 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
379 WREG32(R_000040_GEN_INT_CNTL, 0);
380 return -EINVAL;
381 }
7ed220d7 382 if (rdev->irq.sw_int) {
c010f800 383 tmp |= S_000040_SW_INT_EN(1);
7ed220d7
MD		 384 }
385 if (rdev->irq.crtc_vblank_int[0]) {
c010f800 386 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7
MD		 387 }
388 if (rdev->irq.crtc_vblank_int[1]) {
c010f800 389 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 390 }
dcfdd408
AD		 391 if (rdev->irq.hpd[0]) {
392 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
393 }
394 if (rdev->irq.hpd[1]) {
395 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
396 }
c010f800
JG		 397 WREG32(R_000040_GEN_INT_CNTL, tmp);
398 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 399 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
400 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
7ed220d7
MD		 401 return 0;
402}
403
404static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
405{
01ceae8e
JG		 406 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
407 uint32_t irq_mask = ~C_000044_SW_INT;
dcfdd408 408 u32 tmp;
c010f800 409
01ceae8e 410 if (G_000044_DISPLAY_INT_STAT(irqs)) {
c010f800
JG		 411 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
412 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
413 WREG32(R_006534_D1MODE_VBLANK_STATUS,
414 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 415 }
c010f800
JG		 416 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
417 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
418 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 419 }
dcfdd408
AD		 420 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
421 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
422 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
423 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
424 }
425 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
426 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
427 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
428 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
429 }
7ed220d7
MD		 430 } else {
431 *r500_disp_int = 0;
432 }
433
434 if (irqs) {
01ceae8e 435 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 436 }
437 return irqs & irq_mask;
438}
439
ac447df4
JG		 440void rs600_irq_disable(struct radeon_device *rdev)
441{
442 u32 tmp;
443
444 WREG32(R_000040_GEN_INT_CNTL, 0);
445 WREG32(R_006540_DxMODE_INT_MASK, 0);
446 /* Wait and acknowledge irq */
447 mdelay(1);
448 rs600_irq_ack(rdev, &tmp);
449}
450
7ed220d7
MD		 451int rs600_irq_process(struct radeon_device *rdev)
452{
3e5cb98d 453 uint32_t status, msi_rearm;
7ed220d7 454 uint32_t r500_disp_int;
d4877cf2 455 bool queue_hotplug = false;
7ed220d7
MD		 456
457 status = rs600_irq_ack(rdev, &r500_disp_int);
458 if (!status && !r500_disp_int) {
459 return IRQ_NONE;
460 }
461 while (status || r500_disp_int) {
462 /* SW interrupt */
43b19f16 463 if (G_000044_SW_INT(status))
7ed220d7 464 radeon_fence_process(rdev);
7ed220d7 465 /* Vertical blank interrupts */
c913e23a 466 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 467 drm_handle_vblank(rdev->ddev, 0);
839461d3 468 rdev->pm.vblank_sync = true;
73a6d3fc 469 wake_up(&rdev->irq.vblank_queue);
c913e23a
RM		 470 }
471 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 472 drm_handle_vblank(rdev->ddev, 1);
839461d3 473 rdev->pm.vblank_sync = true;
73a6d3fc 474 wake_up(&rdev->irq.vblank_queue);
c913e23a 475 }
dcfdd408 476 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 477 queue_hotplug = true;
478 DRM_DEBUG("HPD1\n");
dcfdd408
AD		 479 }
480 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 481 queue_hotplug = true;
482 DRM_DEBUG("HPD2\n");
dcfdd408 483 }
7ed220d7
MD		 484 status = rs600_irq_ack(rdev, &r500_disp_int);
485 }
d4877cf2
AD		 486 if (queue_hotplug)
487 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 488 if (rdev->msi_enabled) {
489 switch (rdev->family) {
490 case CHIP_RS600:
491 case CHIP_RS690:
492 case CHIP_RS740:
493 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
494 WREG32(RADEON_BUS_CNTL, msi_rearm);
495 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
496 break;
497 default:
498 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
499 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
500 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
501 break;
502 }
503 }
7ed220d7
MD		 504 return IRQ_HANDLED;
505}
506
507u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
508{
509 if (crtc == 0)
c010f800 510 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 511 else
c010f800 512 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 513}
514
771fe6b9
JG		 515int rs600_mc_wait_for_idle(struct radeon_device *rdev)
516{
517 unsigned i;
771fe6b9
JG		 518
519 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 520 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 521 return 0;
c010f800 522 udelay(1);
771fe6b9
JG		 523 }
524 return -1;
525}
526
771fe6b9
JG		 527void rs600_gpu_init(struct radeon_device *rdev)
528{
771fe6b9 529 r420_pipes_init(rdev);
c010f800
JG		 530 /* Wait for mc idle */
531 if (rs600_mc_wait_for_idle(rdev))
532 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 533}
534
d594e46a 535void rs600_mc_init(struct radeon_device *rdev)
771fe6b9 536{
d594e46a
JG		 537 u64 base;
538
51e5fcd3
JG		 539 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
540 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
771fe6b9
JG		 541 rdev->mc.vram_is_ddr = true;
542 rdev->mc.vram_width = 128;
722f2943
AD		 543 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
544 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
51e5fcd3 545 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 546 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
547 base = RREG32_MC(R_000004_MC_FB_LOCATION);
548 base = G_000004_MC_FB_START(base) << 16;
f47299c5 549 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
d594e46a
JG		 550 radeon_vram_location(rdev, &rdev->mc, base);
551 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 552 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 553}
554
c93bb85b
JG		 555void rs600_bandwidth_update(struct radeon_device *rdev)
556{
f46c0120
AD		 557 struct drm_display_mode *mode0 = NULL;
558 struct drm_display_mode *mode1 = NULL;
559 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
560 /* FIXME: implement full support */
561
562 radeon_update_display_priority(rdev);
563
564 if (rdev->mode_info.crtcs[0]->base.enabled)
565 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
566 if (rdev->mode_info.crtcs[1]->base.enabled)
567 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
568
569 rs690_line_buffer_adjust(rdev, mode0, mode1);
570
571 if (rdev->disp_priority == 2) {
572 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
573 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
574 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
575 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
576 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
577 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
578 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
579 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
580 }
c93bb85b
JG		 581}
582
771fe6b9
JG		 583uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
584{
c010f800
JG		 585 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
586 S_000070_MC_IND_CITF_ARB0(1));
587 return RREG32(R_000074_MC_IND_DATA);
771fe6b9
JG		 588}
589
590void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
591{
c010f800
JG		 592 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
593 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
594 WREG32(R_000074_MC_IND_DATA, v);
595}
596
597void rs600_debugfs(struct radeon_device *rdev)
598{
599 if (r100_debugfs_rbbm_init(rdev))
600 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 601}
3f7dc91a 602
3bc68535 603void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 604{
605 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
606 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 607}
608
c010f800
JG		 609static void rs600_mc_program(struct radeon_device *rdev)
610{
611 struct rv515_mc_save save;
612
613 /* Stops all mc clients */
614 rv515_mc_stop(rdev, &save);
615
616 /* Wait for mc idle */
617 if (rs600_mc_wait_for_idle(rdev))
618 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
619
620 /* FIXME: What does AGP means for such chipset ? */
621 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
622 WREG32_MC(R_000006_AGP_BASE, 0);
623 WREG32_MC(R_000007_AGP_BASE_2, 0);
624 /* Program MC */
625 WREG32_MC(R_000004_MC_FB_LOCATION,
626 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
627 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
628 WREG32(R_000134_HDP_FB_LOCATION,
629 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
630
631 rv515_mc_resume(rdev, &save);
632}
633
634static int rs600_startup(struct radeon_device *rdev)
635{
636 int r;
637
638 rs600_mc_program(rdev);
639 /* Resume clock */
640 rv515_clock_startup(rdev);
641 /* Initialize GPU configuration (# pipes, ...) */
642 rs600_gpu_init(rdev);
643 /* Initialize GART (initialize after TTM so we can allocate
644 * memory through TTM but finalize after TTM) */
645 r = rs600_gart_enable(rdev);
646 if (r)
647 return r;
648 /* Enable IRQ */
c010f800 649 rs600_irq_set(rdev);
cafe6609 650 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 651 /* 1M ring buffer */
652 r = r100_cp_init(rdev, 1024 * 1024);
653 if (r) {
654 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
655 return r;
656 }
657 r = r100_wb_init(rdev);
658 if (r)
659 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
660 r = r100_ib_init(rdev);
661 if (r) {
662 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
663 return r;
664 }
665 return 0;
666}
667
668int rs600_resume(struct radeon_device *rdev)
669{
670 /* Make sur GART are not working */
671 rs600_gart_disable(rdev);
672 /* Resume clock before doing reset */
673 rv515_clock_startup(rdev);
674 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 675 if (radeon_asic_reset(rdev)) {
c010f800
JG		 676 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
677 RREG32(R_000E40_RBBM_STATUS),
678 RREG32(R_0007C0_CP_STAT));
679 }
680 /* post */
681 atom_asic_init(rdev->mode_info.atom_context);
682 /* Resume clock after posting */
683 rv515_clock_startup(rdev);
550e2d92
DA		 684 /* Initialize surface registers */
685 radeon_surface_init(rdev);
c010f800
JG		 686 return rs600_startup(rdev);
687}
688
689int rs600_suspend(struct radeon_device *rdev)
690{
691 r100_cp_disable(rdev);
692 r100_wb_disable(rdev);
ac447df4 693 rs600_irq_disable(rdev);
c010f800
JG		 694 rs600_gart_disable(rdev);
695 return 0;
696}
697
698void rs600_fini(struct radeon_device *rdev)
699{
29fb52ca 700 radeon_pm_fini(rdev);
c010f800
JG		 701 r100_cp_fini(rdev);
702 r100_wb_fini(rdev);
703 r100_ib_fini(rdev);
704 radeon_gem_fini(rdev);
705 rs600_gart_fini(rdev);
706 radeon_irq_kms_fini(rdev);
707 radeon_fence_driver_fini(rdev);
4c788679 708 radeon_bo_fini(rdev);
c010f800
JG		 709 radeon_atombios_fini(rdev);
710 kfree(rdev->bios);
711 rdev->bios = NULL;
712}
713
3bc68535
JG		 714int rs600_init(struct radeon_device *rdev)
715{
c010f800
JG		 716 int r;
717
c010f800
JG		 718 /* Disable VGA */
719 rv515_vga_render_disable(rdev);
720 /* Initialize scratch registers */
721 radeon_scratch_init(rdev);
722 /* Initialize surface registers */
723 radeon_surface_init(rdev);
724 /* BIOS */
725 if (!radeon_get_bios(rdev)) {
726 if (ASIC_IS_AVIVO(rdev))
727 return -EINVAL;
728 }
729 if (rdev->is_atom_bios) {
730 r = radeon_atombios_init(rdev);
731 if (r)
732 return r;
733 } else {
734 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
735 return -EINVAL;
736 }
737 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 738 if (radeon_asic_reset(rdev)) {
c010f800
JG		 739 dev_warn(rdev->dev,
740 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
741 RREG32(R_000E40_RBBM_STATUS),
742 RREG32(R_0007C0_CP_STAT));
743 }
744 /* check if cards are posted or not */
72542d77
DA		 745 if (radeon_boot_test_post_card(rdev) == false)
746 return -EINVAL;
747
c010f800
JG		 748 /* Initialize clocks */
749 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 750 /* Initialize power management */
751 radeon_pm_init(rdev);
d594e46a
JG		 752 /* initialize memory controller */
753 rs600_mc_init(rdev);
c010f800
JG		 754 rs600_debugfs(rdev);
755 /* Fence driver */
756 r = radeon_fence_driver_init(rdev);
757 if (r)
758 return r;
759 r = radeon_irq_kms_init(rdev);
760 if (r)
761 return r;
762 /* Memory manager */
4c788679 763 r = radeon_bo_init(rdev);
c010f800
JG		 764 if (r)
765 return r;
766 r = rs600_gart_init(rdev);
767 if (r)
768 return r;
769 rs600_set_safe_registers(rdev);
770 rdev->accel_working = true;
771 r = rs600_startup(rdev);
772 if (r) {
773 /* Somethings want wront with the accel init stop accel */
774 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800
JG		 775 r100_cp_fini(rdev);
776 r100_wb_fini(rdev);
777 r100_ib_fini(rdev);
778 rs600_gart_fini(rdev);
779 radeon_irq_kms_fini(rdev);
780 rdev->accel_working = false;
781 }
3f7dc91a
DA		 782 return 0;
783}
Linux kernel - Deliverables
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