Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
c010f800 JG |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * | |
30 | * This file gather function specific to RS600 which is the IGP of | |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 | |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are | |
33 | * the avivo one, bios is an atombios, 3D block are the one of the | |
34 | * R4XX family. The GART is different from the RS400 one and is very | |
35 | * close to the one of the R600 family (R600 likely being an evolution | |
36 | * of the RS600 GART block). | |
37 | */ | |
771fe6b9 | 38 | #include "drmP.h" |
771fe6b9 | 39 | #include "radeon.h" |
e6990375 | 40 | #include "radeon_asic.h" |
c010f800 JG |
41 | #include "atom.h" |
42 | #include "rs600d.h" | |
771fe6b9 | 43 | |
3f7dc91a DA |
44 | #include "rs600_reg_safe.h" |
45 | ||
771fe6b9 JG |
46 | void rs600_gpu_init(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); | |
771fe6b9 | 48 | |
dcfdd408 AD |
49 | /* hpd for digital panel detect/disconnect */ |
50 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
51 | { | |
52 | u32 tmp; | |
53 | bool connected = false; | |
54 | ||
55 | switch (hpd) { | |
56 | case RADEON_HPD_1: | |
57 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); | |
58 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) | |
59 | connected = true; | |
60 | break; | |
61 | case RADEON_HPD_2: | |
62 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); | |
63 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) | |
64 | connected = true; | |
65 | break; | |
66 | default: | |
67 | break; | |
68 | } | |
69 | return connected; | |
70 | } | |
71 | ||
72 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
73 | enum radeon_hpd_id hpd) | |
74 | { | |
75 | u32 tmp; | |
76 | bool connected = rs600_hpd_sense(rdev, hpd); | |
77 | ||
78 | switch (hpd) { | |
79 | case RADEON_HPD_1: | |
80 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
81 | if (connected) | |
82 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); | |
83 | else | |
84 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); | |
85 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
86 | break; | |
87 | case RADEON_HPD_2: | |
88 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
89 | if (connected) | |
90 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); | |
91 | else | |
92 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); | |
93 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
94 | break; | |
95 | default: | |
96 | break; | |
97 | } | |
98 | } | |
99 | ||
100 | void rs600_hpd_init(struct radeon_device *rdev) | |
101 | { | |
102 | struct drm_device *dev = rdev->ddev; | |
103 | struct drm_connector *connector; | |
104 | ||
105 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
106 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
107 | switch (radeon_connector->hpd.hpd) { | |
108 | case RADEON_HPD_1: | |
109 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, | |
110 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); | |
111 | rdev->irq.hpd[0] = true; | |
112 | break; | |
113 | case RADEON_HPD_2: | |
114 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, | |
115 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); | |
116 | rdev->irq.hpd[1] = true; | |
117 | break; | |
118 | default: | |
119 | break; | |
120 | } | |
121 | } | |
003e69f9 JG |
122 | if (rdev->irq.installed) |
123 | rs600_irq_set(rdev); | |
dcfdd408 AD |
124 | } |
125 | ||
126 | void rs600_hpd_fini(struct radeon_device *rdev) | |
127 | { | |
128 | struct drm_device *dev = rdev->ddev; | |
129 | struct drm_connector *connector; | |
130 | ||
131 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
132 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
133 | switch (radeon_connector->hpd.hpd) { | |
134 | case RADEON_HPD_1: | |
135 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, | |
136 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); | |
137 | rdev->irq.hpd[0] = false; | |
138 | break; | |
139 | case RADEON_HPD_2: | |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, | |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); | |
142 | rdev->irq.hpd[1] = false; | |
143 | break; | |
144 | default: | |
145 | break; | |
146 | } | |
147 | } | |
148 | } | |
149 | ||
771fe6b9 JG |
150 | /* |
151 | * GART. | |
152 | */ | |
153 | void rs600_gart_tlb_flush(struct radeon_device *rdev) | |
154 | { | |
155 | uint32_t tmp; | |
156 | ||
c010f800 JG |
157 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
158 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
159 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 160 | |
c010f800 JG |
161 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
162 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); | |
163 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
771fe6b9 | 164 | |
c010f800 JG |
165 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
166 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; | |
167 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); | |
168 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); | |
771fe6b9 JG |
169 | } |
170 | ||
4aac0473 | 171 | int rs600_gart_init(struct radeon_device *rdev) |
771fe6b9 | 172 | { |
771fe6b9 JG |
173 | int r; |
174 | ||
4aac0473 JG |
175 | if (rdev->gart.table.vram.robj) { |
176 | WARN(1, "RS600 GART already initialized.\n"); | |
177 | return 0; | |
178 | } | |
771fe6b9 JG |
179 | /* Initialize common gart structure */ |
180 | r = radeon_gart_init(rdev); | |
181 | if (r) { | |
182 | return r; | |
183 | } | |
184 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; | |
4aac0473 JG |
185 | return radeon_gart_table_vram_alloc(rdev); |
186 | } | |
187 | ||
188 | int rs600_gart_enable(struct radeon_device *rdev) | |
189 | { | |
c010f800 | 190 | u32 tmp; |
4aac0473 JG |
191 | int r, i; |
192 | ||
193 | if (rdev->gart.table.vram.robj == NULL) { | |
194 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
195 | return -EINVAL; | |
771fe6b9 | 196 | } |
4aac0473 JG |
197 | r = radeon_gart_table_vram_pin(rdev); |
198 | if (r) | |
199 | return r; | |
82568565 | 200 | radeon_gart_restore(rdev); |
c010f800 JG |
201 | /* Enable bus master */ |
202 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; | |
203 | WREG32(R_00004C_BUS_CNTL, tmp); | |
771fe6b9 | 204 | /* FIXME: setup default page */ |
c010f800 | 205 | WREG32_MC(R_000100_MC_PT0_CNTL, |
4f15d24a AD |
206 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
207 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); | |
208 | ||
771fe6b9 | 209 | for (i = 0; i < 19; i++) { |
c010f800 | 210 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
4f15d24a AD |
211 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
212 | S_00016C_SYSTEM_ACCESS_MODE_MASK( | |
213 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | | |
214 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( | |
215 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | | |
216 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | | |
217 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | | |
218 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); | |
771fe6b9 | 219 | } |
771fe6b9 | 220 | /* enable first context */ |
c010f800 | 221 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
4f15d24a AD |
222 | S_000102_ENABLE_PAGE_TABLE(1) | |
223 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); | |
224 | ||
771fe6b9 | 225 | /* disable all other contexts */ |
4f15d24a | 226 | for (i = 1; i < 8; i++) |
c010f800 | 227 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
771fe6b9 JG |
228 | |
229 | /* setup the page table */ | |
c010f800 | 230 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
4f15d24a AD |
231 | rdev->gart.table_addr); |
232 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); | |
233 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); | |
c010f800 | 234 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
771fe6b9 | 235 | |
4f15d24a AD |
236 | /* System context maps to VRAM space */ |
237 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); | |
238 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); | |
239 | ||
771fe6b9 | 240 | /* enable page tables */ |
c010f800 JG |
241 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
242 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); | |
243 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
244 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); | |
771fe6b9 JG |
245 | rs600_gart_tlb_flush(rdev); |
246 | rdev->gart.ready = true; | |
247 | return 0; | |
248 | } | |
249 | ||
250 | void rs600_gart_disable(struct radeon_device *rdev) | |
251 | { | |
4c788679 JG |
252 | u32 tmp; |
253 | int r; | |
771fe6b9 JG |
254 | |
255 | /* FIXME: disable out of gart access */ | |
c010f800 JG |
256 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
257 | tmp = RREG32_MC(R_000009_MC_CNTL1); | |
258 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); | |
4aac0473 | 259 | if (rdev->gart.table.vram.robj) { |
4c788679 JG |
260 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
261 | if (r == 0) { | |
262 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
263 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
264 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
265 | } | |
4aac0473 JG |
266 | } |
267 | } | |
268 | ||
269 | void rs600_gart_fini(struct radeon_device *rdev) | |
270 | { | |
f9274562 | 271 | radeon_gart_fini(rdev); |
4aac0473 JG |
272 | rs600_gart_disable(rdev); |
273 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
274 | } |
275 | ||
276 | #define R600_PTE_VALID (1 << 0) | |
277 | #define R600_PTE_SYSTEM (1 << 1) | |
278 | #define R600_PTE_SNOOPED (1 << 2) | |
279 | #define R600_PTE_READABLE (1 << 5) | |
280 | #define R600_PTE_WRITEABLE (1 << 6) | |
281 | ||
282 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
283 | { | |
284 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | |
285 | ||
286 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
287 | return -EINVAL; | |
288 | } | |
289 | addr = addr & 0xFFFFFFFFFFFFF000ULL; | |
290 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
291 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
292 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); | |
293 | return 0; | |
294 | } | |
295 | ||
7ed220d7 MD |
296 | int rs600_irq_set(struct radeon_device *rdev) |
297 | { | |
298 | uint32_t tmp = 0; | |
299 | uint32_t mode_int = 0; | |
dcfdd408 AD |
300 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
301 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | |
302 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & | |
303 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | |
7ed220d7 | 304 | |
003e69f9 JG |
305 | if (!rdev->irq.installed) { |
306 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
307 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
308 | return -EINVAL; | |
309 | } | |
7ed220d7 | 310 | if (rdev->irq.sw_int) { |
c010f800 | 311 | tmp |= S_000040_SW_INT_EN(1); |
7ed220d7 MD |
312 | } |
313 | if (rdev->irq.crtc_vblank_int[0]) { | |
c010f800 | 314 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
7ed220d7 MD |
315 | } |
316 | if (rdev->irq.crtc_vblank_int[1]) { | |
c010f800 | 317 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
7ed220d7 | 318 | } |
dcfdd408 AD |
319 | if (rdev->irq.hpd[0]) { |
320 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | |
321 | } | |
322 | if (rdev->irq.hpd[1]) { | |
323 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | |
324 | } | |
c010f800 JG |
325 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
326 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); | |
dcfdd408 AD |
327 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
328 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
7ed220d7 MD |
329 | return 0; |
330 | } | |
331 | ||
332 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) | |
333 | { | |
01ceae8e JG |
334 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
335 | uint32_t irq_mask = ~C_000044_SW_INT; | |
dcfdd408 | 336 | u32 tmp; |
c010f800 | 337 | |
01ceae8e | 338 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
c010f800 JG |
339 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
340 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { | |
341 | WREG32(R_006534_D1MODE_VBLANK_STATUS, | |
342 | S_006534_D1MODE_VBLANK_ACK(1)); | |
7ed220d7 | 343 | } |
c010f800 JG |
344 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
345 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, | |
346 | S_006D34_D2MODE_VBLANK_ACK(1)); | |
7ed220d7 | 347 | } |
dcfdd408 AD |
348 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
349 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
350 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); | |
351 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
352 | } | |
353 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { | |
354 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
355 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); | |
356 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
357 | } | |
7ed220d7 MD |
358 | } else { |
359 | *r500_disp_int = 0; | |
360 | } | |
361 | ||
362 | if (irqs) { | |
01ceae8e | 363 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
7ed220d7 MD |
364 | } |
365 | return irqs & irq_mask; | |
366 | } | |
367 | ||
ac447df4 JG |
368 | void rs600_irq_disable(struct radeon_device *rdev) |
369 | { | |
370 | u32 tmp; | |
371 | ||
372 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
373 | WREG32(R_006540_DxMODE_INT_MASK, 0); | |
374 | /* Wait and acknowledge irq */ | |
375 | mdelay(1); | |
376 | rs600_irq_ack(rdev, &tmp); | |
377 | } | |
378 | ||
7ed220d7 MD |
379 | int rs600_irq_process(struct radeon_device *rdev) |
380 | { | |
3e5cb98d | 381 | uint32_t status, msi_rearm; |
7ed220d7 | 382 | uint32_t r500_disp_int; |
d4877cf2 | 383 | bool queue_hotplug = false; |
7ed220d7 MD |
384 | |
385 | status = rs600_irq_ack(rdev, &r500_disp_int); | |
386 | if (!status && !r500_disp_int) { | |
387 | return IRQ_NONE; | |
388 | } | |
389 | while (status || r500_disp_int) { | |
390 | /* SW interrupt */ | |
43b19f16 | 391 | if (G_000044_SW_INT(status)) |
7ed220d7 | 392 | radeon_fence_process(rdev); |
7ed220d7 | 393 | /* Vertical blank interrupts */ |
c913e23a | 394 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { |
7ed220d7 | 395 | drm_handle_vblank(rdev->ddev, 0); |
839461d3 | 396 | rdev->pm.vblank_sync = true; |
73a6d3fc | 397 | wake_up(&rdev->irq.vblank_queue); |
c913e23a RM |
398 | } |
399 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { | |
7ed220d7 | 400 | drm_handle_vblank(rdev->ddev, 1); |
839461d3 | 401 | rdev->pm.vblank_sync = true; |
73a6d3fc | 402 | wake_up(&rdev->irq.vblank_queue); |
c913e23a | 403 | } |
dcfdd408 | 404 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { |
d4877cf2 AD |
405 | queue_hotplug = true; |
406 | DRM_DEBUG("HPD1\n"); | |
dcfdd408 AD |
407 | } |
408 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) { | |
d4877cf2 AD |
409 | queue_hotplug = true; |
410 | DRM_DEBUG("HPD2\n"); | |
dcfdd408 | 411 | } |
7ed220d7 MD |
412 | status = rs600_irq_ack(rdev, &r500_disp_int); |
413 | } | |
d4877cf2 AD |
414 | if (queue_hotplug) |
415 | queue_work(rdev->wq, &rdev->hotplug_work); | |
3e5cb98d AD |
416 | if (rdev->msi_enabled) { |
417 | switch (rdev->family) { | |
418 | case CHIP_RS600: | |
419 | case CHIP_RS690: | |
420 | case CHIP_RS740: | |
421 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; | |
422 | WREG32(RADEON_BUS_CNTL, msi_rearm); | |
423 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); | |
424 | break; | |
425 | default: | |
426 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; | |
427 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); | |
428 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); | |
429 | break; | |
430 | } | |
431 | } | |
7ed220d7 MD |
432 | return IRQ_HANDLED; |
433 | } | |
434 | ||
435 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
436 | { | |
437 | if (crtc == 0) | |
c010f800 | 438 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
7ed220d7 | 439 | else |
c010f800 | 440 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
7ed220d7 MD |
441 | } |
442 | ||
771fe6b9 JG |
443 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
444 | { | |
445 | unsigned i; | |
771fe6b9 JG |
446 | |
447 | for (i = 0; i < rdev->usec_timeout; i++) { | |
c010f800 | 448 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
771fe6b9 | 449 | return 0; |
c010f800 | 450 | udelay(1); |
771fe6b9 JG |
451 | } |
452 | return -1; | |
453 | } | |
454 | ||
771fe6b9 JG |
455 | void rs600_gpu_init(struct radeon_device *rdev) |
456 | { | |
771fe6b9 | 457 | r100_hdp_reset(rdev); |
771fe6b9 | 458 | r420_pipes_init(rdev); |
c010f800 JG |
459 | /* Wait for mc idle */ |
460 | if (rs600_mc_wait_for_idle(rdev)) | |
461 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
771fe6b9 JG |
462 | } |
463 | ||
d594e46a | 464 | void rs600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 465 | { |
d594e46a JG |
466 | u64 base; |
467 | ||
51e5fcd3 JG |
468 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
469 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
771fe6b9 JG |
470 | rdev->mc.vram_is_ddr = true; |
471 | rdev->mc.vram_width = 128; | |
722f2943 AD |
472 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
473 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
51e5fcd3 | 474 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a JG |
475 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
476 | base = RREG32_MC(R_000004_MC_FB_LOCATION); | |
477 | base = G_000004_MC_FB_START(base) << 16; | |
f47299c5 | 478 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
d594e46a JG |
479 | radeon_vram_location(rdev, &rdev->mc, base); |
480 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 481 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
482 | } |
483 | ||
c93bb85b JG |
484 | void rs600_bandwidth_update(struct radeon_device *rdev) |
485 | { | |
f46c0120 AD |
486 | struct drm_display_mode *mode0 = NULL; |
487 | struct drm_display_mode *mode1 = NULL; | |
488 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; | |
489 | /* FIXME: implement full support */ | |
490 | ||
491 | radeon_update_display_priority(rdev); | |
492 | ||
493 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
494 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
495 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
496 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
497 | ||
498 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
499 | ||
500 | if (rdev->disp_priority == 2) { | |
501 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); | |
502 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); | |
503 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); | |
504 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | |
505 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
506 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | |
507 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | |
508 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | |
509 | } | |
c93bb85b JG |
510 | } |
511 | ||
771fe6b9 JG |
512 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
513 | { | |
c010f800 JG |
514 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
515 | S_000070_MC_IND_CITF_ARB0(1)); | |
516 | return RREG32(R_000074_MC_IND_DATA); | |
771fe6b9 JG |
517 | } |
518 | ||
519 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
520 | { | |
c010f800 JG |
521 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
522 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); | |
523 | WREG32(R_000074_MC_IND_DATA, v); | |
524 | } | |
525 | ||
526 | void rs600_debugfs(struct radeon_device *rdev) | |
527 | { | |
528 | if (r100_debugfs_rbbm_init(rdev)) | |
529 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
771fe6b9 | 530 | } |
3f7dc91a | 531 | |
3bc68535 | 532 | void rs600_set_safe_registers(struct radeon_device *rdev) |
3f7dc91a DA |
533 | { |
534 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; | |
535 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); | |
3bc68535 JG |
536 | } |
537 | ||
c010f800 JG |
538 | static void rs600_mc_program(struct radeon_device *rdev) |
539 | { | |
540 | struct rv515_mc_save save; | |
541 | ||
542 | /* Stops all mc clients */ | |
543 | rv515_mc_stop(rdev, &save); | |
544 | ||
545 | /* Wait for mc idle */ | |
546 | if (rs600_mc_wait_for_idle(rdev)) | |
547 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
548 | ||
549 | /* FIXME: What does AGP means for such chipset ? */ | |
550 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); | |
551 | WREG32_MC(R_000006_AGP_BASE, 0); | |
552 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
553 | /* Program MC */ | |
554 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
555 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
556 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
557 | WREG32(R_000134_HDP_FB_LOCATION, | |
558 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
559 | ||
560 | rv515_mc_resume(rdev, &save); | |
561 | } | |
562 | ||
563 | static int rs600_startup(struct radeon_device *rdev) | |
564 | { | |
565 | int r; | |
566 | ||
567 | rs600_mc_program(rdev); | |
568 | /* Resume clock */ | |
569 | rv515_clock_startup(rdev); | |
570 | /* Initialize GPU configuration (# pipes, ...) */ | |
571 | rs600_gpu_init(rdev); | |
572 | /* Initialize GART (initialize after TTM so we can allocate | |
573 | * memory through TTM but finalize after TTM) */ | |
574 | r = rs600_gart_enable(rdev); | |
575 | if (r) | |
576 | return r; | |
577 | /* Enable IRQ */ | |
c010f800 | 578 | rs600_irq_set(rdev); |
cafe6609 | 579 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
c010f800 JG |
580 | /* 1M ring buffer */ |
581 | r = r100_cp_init(rdev, 1024 * 1024); | |
582 | if (r) { | |
583 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
584 | return r; | |
585 | } | |
586 | r = r100_wb_init(rdev); | |
587 | if (r) | |
588 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
589 | r = r100_ib_init(rdev); | |
590 | if (r) { | |
591 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
592 | return r; | |
593 | } | |
594 | return 0; | |
595 | } | |
596 | ||
597 | int rs600_resume(struct radeon_device *rdev) | |
598 | { | |
599 | /* Make sur GART are not working */ | |
600 | rs600_gart_disable(rdev); | |
601 | /* Resume clock before doing reset */ | |
602 | rv515_clock_startup(rdev); | |
603 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 604 | if (radeon_asic_reset(rdev)) { |
c010f800 JG |
605 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
606 | RREG32(R_000E40_RBBM_STATUS), | |
607 | RREG32(R_0007C0_CP_STAT)); | |
608 | } | |
609 | /* post */ | |
610 | atom_asic_init(rdev->mode_info.atom_context); | |
611 | /* Resume clock after posting */ | |
612 | rv515_clock_startup(rdev); | |
550e2d92 DA |
613 | /* Initialize surface registers */ |
614 | radeon_surface_init(rdev); | |
c010f800 JG |
615 | return rs600_startup(rdev); |
616 | } | |
617 | ||
618 | int rs600_suspend(struct radeon_device *rdev) | |
619 | { | |
620 | r100_cp_disable(rdev); | |
621 | r100_wb_disable(rdev); | |
ac447df4 | 622 | rs600_irq_disable(rdev); |
c010f800 JG |
623 | rs600_gart_disable(rdev); |
624 | return 0; | |
625 | } | |
626 | ||
627 | void rs600_fini(struct radeon_device *rdev) | |
628 | { | |
29fb52ca | 629 | radeon_pm_fini(rdev); |
c010f800 JG |
630 | r100_cp_fini(rdev); |
631 | r100_wb_fini(rdev); | |
632 | r100_ib_fini(rdev); | |
633 | radeon_gem_fini(rdev); | |
634 | rs600_gart_fini(rdev); | |
635 | radeon_irq_kms_fini(rdev); | |
636 | radeon_fence_driver_fini(rdev); | |
4c788679 | 637 | radeon_bo_fini(rdev); |
c010f800 JG |
638 | radeon_atombios_fini(rdev); |
639 | kfree(rdev->bios); | |
640 | rdev->bios = NULL; | |
641 | } | |
642 | ||
3bc68535 JG |
643 | int rs600_init(struct radeon_device *rdev) |
644 | { | |
c010f800 JG |
645 | int r; |
646 | ||
c010f800 JG |
647 | /* Disable VGA */ |
648 | rv515_vga_render_disable(rdev); | |
649 | /* Initialize scratch registers */ | |
650 | radeon_scratch_init(rdev); | |
651 | /* Initialize surface registers */ | |
652 | radeon_surface_init(rdev); | |
653 | /* BIOS */ | |
654 | if (!radeon_get_bios(rdev)) { | |
655 | if (ASIC_IS_AVIVO(rdev)) | |
656 | return -EINVAL; | |
657 | } | |
658 | if (rdev->is_atom_bios) { | |
659 | r = radeon_atombios_init(rdev); | |
660 | if (r) | |
661 | return r; | |
662 | } else { | |
663 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); | |
664 | return -EINVAL; | |
665 | } | |
666 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 667 | if (radeon_asic_reset(rdev)) { |
c010f800 JG |
668 | dev_warn(rdev->dev, |
669 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
670 | RREG32(R_000E40_RBBM_STATUS), | |
671 | RREG32(R_0007C0_CP_STAT)); | |
672 | } | |
673 | /* check if cards are posted or not */ | |
72542d77 DA |
674 | if (radeon_boot_test_post_card(rdev) == false) |
675 | return -EINVAL; | |
676 | ||
c010f800 JG |
677 | /* Initialize clocks */ |
678 | radeon_get_clock_info(rdev->ddev); | |
7433874e RM |
679 | /* Initialize power management */ |
680 | radeon_pm_init(rdev); | |
d594e46a JG |
681 | /* initialize memory controller */ |
682 | rs600_mc_init(rdev); | |
c010f800 JG |
683 | rs600_debugfs(rdev); |
684 | /* Fence driver */ | |
685 | r = radeon_fence_driver_init(rdev); | |
686 | if (r) | |
687 | return r; | |
688 | r = radeon_irq_kms_init(rdev); | |
689 | if (r) | |
690 | return r; | |
691 | /* Memory manager */ | |
4c788679 | 692 | r = radeon_bo_init(rdev); |
c010f800 JG |
693 | if (r) |
694 | return r; | |
695 | r = rs600_gart_init(rdev); | |
696 | if (r) | |
697 | return r; | |
698 | rs600_set_safe_registers(rdev); | |
699 | rdev->accel_working = true; | |
700 | r = rs600_startup(rdev); | |
701 | if (r) { | |
702 | /* Somethings want wront with the accel init stop accel */ | |
703 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
c010f800 JG |
704 | r100_cp_fini(rdev); |
705 | r100_wb_fini(rdev); | |
706 | r100_ib_fini(rdev); | |
707 | rs600_gart_fini(rdev); | |
708 | radeon_irq_kms_fini(rdev); | |
709 | rdev->accel_working = false; | |
710 | } | |
3f7dc91a DA |
711 | return 0; |
712 | } |