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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 | 29 | #include "radeon.h" |
e6990375 | 30 | #include "radeon_asic.h" |
c93bb85b | 31 | #include "atom.h" |
3bc68535 | 32 | #include "rs690d.h" |
771fe6b9 | 33 | |
89e5181f | 34 | int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 JG |
35 | { |
36 | unsigned i; | |
37 | uint32_t tmp; | |
38 | ||
39 | for (i = 0; i < rdev->usec_timeout; i++) { | |
40 | /* read MC_STATUS */ | |
3bc68535 JG |
41 | tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); |
42 | if (G_000090_MC_SYSTEM_IDLE(tmp)) | |
771fe6b9 | 43 | return 0; |
3bc68535 | 44 | udelay(1); |
771fe6b9 JG |
45 | } |
46 | return -1; | |
47 | } | |
48 | ||
3bc68535 | 49 | static void rs690_gpu_init(struct radeon_device *rdev) |
771fe6b9 | 50 | { |
771fe6b9 JG |
51 | /* FIXME: is this correct ? */ |
52 | r420_pipes_init(rdev); | |
53 | if (rs690_mc_wait_for_idle(rdev)) { | |
54 | printk(KERN_WARNING "Failed to wait MC idle while " | |
55 | "programming pipes. Bad things might happen.\n"); | |
56 | } | |
57 | } | |
58 | ||
a084e6ee AD |
59 | union igp_info { |
60 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
61 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; | |
62 | }; | |
63 | ||
c93bb85b JG |
64 | void rs690_pm_info(struct radeon_device *rdev) |
65 | { | |
66 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
a084e6ee | 67 | union igp_info *info; |
c93bb85b JG |
68 | uint16_t data_offset; |
69 | uint8_t frev, crev; | |
70 | fixed20_12 tmp; | |
71 | ||
a084e6ee AD |
72 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
73 | &frev, &crev, &data_offset)) { | |
74 | info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); | |
75 | ||
76 | /* Get various system informations from bios */ | |
77 | switch (crev) { | |
78 | case 1: | |
68adac5e | 79 | tmp.full = dfixed_const(100); |
265aa6c8 | 80 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); |
68adac5e | 81 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
265aa6c8 | 82 | if (le16_to_cpu(info->info.usK8MemoryClock)) |
f892034a AD |
83 | rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); |
84 | else if (rdev->clock.default_mclk) { | |
85 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); | |
86 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); | |
87 | } else | |
88 | rdev->pm.igp_system_mclk.full = dfixed_const(400); | |
68adac5e BS |
89 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); |
90 | rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); | |
a084e6ee AD |
91 | break; |
92 | case 2: | |
68adac5e | 93 | tmp.full = dfixed_const(100); |
265aa6c8 | 94 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); |
68adac5e | 95 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
265aa6c8 AD |
96 | if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) |
97 | rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); | |
f892034a AD |
98 | else if (rdev->clock.default_mclk) |
99 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); | |
100 | else | |
101 | rdev->pm.igp_system_mclk.full = dfixed_const(66700); | |
68adac5e | 102 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
265aa6c8 | 103 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); |
68adac5e BS |
104 | rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
105 | rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); | |
a084e6ee AD |
106 | break; |
107 | default: | |
a084e6ee | 108 | /* We assume the slower possible clock ie worst case */ |
f892034a AD |
109 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
110 | rdev->pm.igp_system_mclk.full = dfixed_const(200); | |
111 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); | |
68adac5e | 112 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
a084e6ee AD |
113 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
114 | break; | |
115 | } | |
116 | } else { | |
c93bb85b | 117 | /* We assume the slower possible clock ie worst case */ |
f892034a AD |
118 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
119 | rdev->pm.igp_system_mclk.full = dfixed_const(200); | |
120 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); | |
68adac5e | 121 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
c93bb85b | 122 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
c93bb85b JG |
123 | } |
124 | /* Compute various bandwidth */ | |
125 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ | |
68adac5e BS |
126 | tmp.full = dfixed_const(4); |
127 | rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); | |
c93bb85b JG |
128 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
129 | * = ht_clk * ht_width / 5 | |
130 | */ | |
68adac5e BS |
131 | tmp.full = dfixed_const(5); |
132 | rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, | |
c93bb85b | 133 | rdev->pm.igp_ht_link_width); |
68adac5e | 134 | rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); |
c93bb85b JG |
135 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
136 | /* HT link is a limiting factor */ | |
137 | rdev->pm.max_bandwidth.full = tmp.full; | |
138 | } | |
139 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 | |
140 | * = (sideport_clk * 14) / 10 | |
141 | */ | |
68adac5e BS |
142 | tmp.full = dfixed_const(14); |
143 | rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); | |
144 | tmp.full = dfixed_const(10); | |
145 | rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); | |
c93bb85b JG |
146 | } |
147 | ||
1109ca09 | 148 | static void rs690_mc_init(struct radeon_device *rdev) |
771fe6b9 | 149 | { |
d594e46a | 150 | u64 base; |
a0a53aa8 SL |
151 | uint32_t h_addr, l_addr; |
152 | unsigned long long k8_addr; | |
771fe6b9 JG |
153 | |
154 | rs400_gart_adjust_size(rdev); | |
771fe6b9 | 155 | rdev->mc.vram_is_ddr = true; |
722f2943 | 156 | rdev->mc.vram_width = 128; |
7a50f01a DA |
157 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
158 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
01d73a69 JC |
159 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
160 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
51e5fcd3 | 161 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a JG |
162 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
163 | base = G_000100_MC_FB_START(base) << 16; | |
06b6476d | 164 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
a0a53aa8 SL |
165 | |
166 | /* Use K8 direct mapping for fast fb access. */ | |
167 | rdev->fastfb_working = false; | |
168 | h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL)); | |
169 | l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION); | |
170 | k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; | |
171 | #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) | |
172 | if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) | |
173 | #endif | |
174 | { | |
175 | /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport | |
176 | * memory is present. | |
177 | */ | |
178 | if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { | |
179 | DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", | |
180 | (unsigned long long)rdev->mc.aper_base, k8_addr); | |
181 | rdev->mc.aper_base = (resource_size_t)k8_addr; | |
182 | rdev->fastfb_working = true; | |
183 | } | |
184 | } | |
185 | ||
4c70b2ea | 186 | rs690_pm_info(rdev); |
d594e46a | 187 | radeon_vram_location(rdev, &rdev->mc, base); |
8d369bb1 | 188 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
d594e46a | 189 | radeon_gtt_location(rdev, &rdev->mc); |
f47299c5 | 190 | radeon_update_bandwidth_info(rdev); |
22dd5013 AD |
191 | } |
192 | ||
c93bb85b JG |
193 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
194 | struct drm_display_mode *mode1, | |
195 | struct drm_display_mode *mode2) | |
196 | { | |
197 | u32 tmp; | |
198 | ||
199 | /* | |
200 | * Line Buffer Setup | |
201 | * There is a single line buffer shared by both display controllers. | |
3bc68535 | 202 | * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
c93bb85b JG |
203 | * the display controllers. The paritioning can either be done |
204 | * manually or via one of four preset allocations specified in bits 1:0: | |
205 | * 0 - line buffer is divided in half and shared between crtc | |
206 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 | |
207 | * 2 - D1 gets the whole buffer | |
208 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 | |
3bc68535 | 209 | * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual |
c93bb85b JG |
210 | * allocation mode. In manual allocation mode, D1 always starts at 0, |
211 | * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. | |
212 | */ | |
3bc68535 JG |
213 | tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; |
214 | tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; | |
c93bb85b JG |
215 | /* auto */ |
216 | if (mode1 && mode2) { | |
217 | if (mode1->hdisplay > mode2->hdisplay) { | |
218 | if (mode1->hdisplay > 2560) | |
3bc68535 | 219 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
c93bb85b | 220 | else |
3bc68535 | 221 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
c93bb85b JG |
222 | } else if (mode2->hdisplay > mode1->hdisplay) { |
223 | if (mode2->hdisplay > 2560) | |
3bc68535 | 224 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
c93bb85b | 225 | else |
3bc68535 | 226 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
c93bb85b | 227 | } else |
3bc68535 | 228 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
c93bb85b | 229 | } else if (mode1) { |
3bc68535 | 230 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; |
c93bb85b | 231 | } else if (mode2) { |
3bc68535 | 232 | tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
c93bb85b | 233 | } |
3bc68535 | 234 | WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); |
771fe6b9 JG |
235 | } |
236 | ||
c93bb85b JG |
237 | struct rs690_watermark { |
238 | u32 lb_request_fifo_depth; | |
239 | fixed20_12 num_line_pair; | |
240 | fixed20_12 estimated_width; | |
241 | fixed20_12 worst_case_latency; | |
242 | fixed20_12 consumption_rate; | |
243 | fixed20_12 active_time; | |
244 | fixed20_12 dbpp; | |
245 | fixed20_12 priority_mark_max; | |
246 | fixed20_12 priority_mark; | |
247 | fixed20_12 sclk; | |
248 | }; | |
249 | ||
1109ca09 | 250 | static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, |
3a4d8f7b AD |
251 | struct radeon_crtc *crtc, |
252 | struct rs690_watermark *wm, | |
253 | bool low) | |
c93bb85b JG |
254 | { |
255 | struct drm_display_mode *mode = &crtc->base.mode; | |
256 | fixed20_12 a, b, c; | |
257 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; | |
258 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; | |
3a4d8f7b AD |
259 | fixed20_12 sclk, core_bandwidth, max_bandwidth; |
260 | u32 selected_sclk; | |
c93bb85b JG |
261 | |
262 | if (!crtc->base.enabled) { | |
263 | /* FIXME: wouldn't it better to set priority mark to maximum */ | |
264 | wm->lb_request_fifo_depth = 4; | |
265 | return; | |
266 | } | |
267 | ||
3a4d8f7b AD |
268 | if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) && |
269 | (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) | |
270 | selected_sclk = radeon_dpm_get_sclk(rdev, low); | |
271 | else | |
272 | selected_sclk = rdev->pm.current_sclk; | |
273 | ||
274 | /* sclk in Mhz */ | |
275 | a.full = dfixed_const(100); | |
276 | sclk.full = dfixed_const(selected_sclk); | |
277 | sclk.full = dfixed_div(sclk, a); | |
278 | ||
279 | /* core_bandwidth = sclk(Mhz) * 16 */ | |
280 | a.full = dfixed_const(16); | |
281 | core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); | |
282 | ||
68adac5e BS |
283 | if (crtc->vsc.full > dfixed_const(2)) |
284 | wm->num_line_pair.full = dfixed_const(2); | |
c93bb85b | 285 | else |
68adac5e BS |
286 | wm->num_line_pair.full = dfixed_const(1); |
287 | ||
288 | b.full = dfixed_const(mode->crtc_hdisplay); | |
289 | c.full = dfixed_const(256); | |
290 | a.full = dfixed_div(b, c); | |
291 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); | |
292 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); | |
293 | if (a.full < dfixed_const(4)) { | |
c93bb85b JG |
294 | wm->lb_request_fifo_depth = 4; |
295 | } else { | |
68adac5e | 296 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
c93bb85b JG |
297 | } |
298 | ||
299 | /* Determine consumption rate | |
300 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) | |
301 | * vtaps = number of vertical taps, | |
302 | * vsc = vertical scaling ratio, defined as source/destination | |
303 | * hsc = horizontal scaling ration, defined as source/destination | |
304 | */ | |
68adac5e BS |
305 | a.full = dfixed_const(mode->clock); |
306 | b.full = dfixed_const(1000); | |
307 | a.full = dfixed_div(a, b); | |
308 | pclk.full = dfixed_div(b, a); | |
c93bb85b | 309 | if (crtc->rmx_type != RMX_OFF) { |
68adac5e | 310 | b.full = dfixed_const(2); |
c93bb85b JG |
311 | if (crtc->vsc.full > b.full) |
312 | b.full = crtc->vsc.full; | |
68adac5e BS |
313 | b.full = dfixed_mul(b, crtc->hsc); |
314 | c.full = dfixed_const(2); | |
315 | b.full = dfixed_div(b, c); | |
316 | consumption_time.full = dfixed_div(pclk, b); | |
c93bb85b JG |
317 | } else { |
318 | consumption_time.full = pclk.full; | |
319 | } | |
68adac5e BS |
320 | a.full = dfixed_const(1); |
321 | wm->consumption_rate.full = dfixed_div(a, consumption_time); | |
c93bb85b JG |
322 | |
323 | ||
324 | /* Determine line time | |
325 | * LineTime = total time for one line of displayhtotal | |
326 | * LineTime = total number of horizontal pixels | |
327 | * pclk = pixel clock period(ns) | |
328 | */ | |
68adac5e BS |
329 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
330 | line_time.full = dfixed_mul(a, pclk); | |
c93bb85b JG |
331 | |
332 | /* Determine active time | |
333 | * ActiveTime = time of active region of display within one line, | |
334 | * hactive = total number of horizontal active pixels | |
335 | * htotal = total number of horizontal pixels | |
336 | */ | |
68adac5e BS |
337 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
338 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
339 | wm->active_time.full = dfixed_mul(line_time, b); | |
340 | wm->active_time.full = dfixed_div(wm->active_time, a); | |
c93bb85b JG |
341 | |
342 | /* Maximun bandwidth is the minimun bandwidth of all component */ | |
3a4d8f7b | 343 | max_bandwidth = core_bandwidth; |
0888e883 | 344 | if (rdev->mc.igp_sideport_enabled) { |
3a4d8f7b | 345 | if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
c93bb85b | 346 | rdev->pm.sideport_bandwidth.full) |
3a4d8f7b | 347 | max_bandwidth = rdev->pm.sideport_bandwidth; |
68adac5e BS |
348 | read_delay_latency.full = dfixed_const(370 * 800 * 1000); |
349 | read_delay_latency.full = dfixed_div(read_delay_latency, | |
c93bb85b JG |
350 | rdev->pm.igp_sideport_mclk); |
351 | } else { | |
3a4d8f7b | 352 | if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
c93bb85b | 353 | rdev->pm.k8_bandwidth.full) |
3a4d8f7b AD |
354 | max_bandwidth = rdev->pm.k8_bandwidth; |
355 | if (max_bandwidth.full > rdev->pm.ht_bandwidth.full && | |
c93bb85b | 356 | rdev->pm.ht_bandwidth.full) |
3a4d8f7b | 357 | max_bandwidth = rdev->pm.ht_bandwidth; |
68adac5e | 358 | read_delay_latency.full = dfixed_const(5000); |
c93bb85b JG |
359 | } |
360 | ||
361 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ | |
68adac5e | 362 | a.full = dfixed_const(16); |
3a4d8f7b | 363 | sclk.full = dfixed_mul(max_bandwidth, a); |
68adac5e | 364 | a.full = dfixed_const(1000); |
3a4d8f7b | 365 | sclk.full = dfixed_div(a, sclk); |
c93bb85b JG |
366 | /* Determine chunk time |
367 | * ChunkTime = the time it takes the DCP to send one chunk of data | |
368 | * to the LB which consists of pipeline delay and inter chunk gap | |
369 | * sclk = system clock(ns) | |
370 | */ | |
68adac5e | 371 | a.full = dfixed_const(256 * 13); |
3a4d8f7b | 372 | chunk_time.full = dfixed_mul(sclk, a); |
68adac5e BS |
373 | a.full = dfixed_const(10); |
374 | chunk_time.full = dfixed_div(chunk_time, a); | |
c93bb85b JG |
375 | |
376 | /* Determine the worst case latency | |
377 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) | |
378 | * WorstCaseLatency = worst case time from urgent to when the MC starts | |
379 | * to return data | |
380 | * READ_DELAY_IDLE_MAX = constant of 1us | |
381 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB | |
382 | * which consists of pipeline delay and inter chunk gap | |
383 | */ | |
68adac5e BS |
384 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
385 | a.full = dfixed_const(3); | |
386 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
c93bb85b JG |
387 | wm->worst_case_latency.full += read_delay_latency.full; |
388 | } else { | |
68adac5e BS |
389 | a.full = dfixed_const(2); |
390 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); | |
c93bb85b JG |
391 | wm->worst_case_latency.full += read_delay_latency.full; |
392 | } | |
393 | ||
394 | /* Determine the tolerable latency | |
395 | * TolerableLatency = Any given request has only 1 line time | |
396 | * for the data to be returned | |
397 | * LBRequestFifoDepth = Number of chunk requests the LB can | |
398 | * put into the request FIFO for a display | |
399 | * LineTime = total time for one line of display | |
400 | * ChunkTime = the time it takes the DCP to send one chunk | |
401 | * of data to the LB which consists of | |
402 | * pipeline delay and inter chunk gap | |
403 | */ | |
68adac5e | 404 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
c93bb85b JG |
405 | tolerable_latency.full = line_time.full; |
406 | } else { | |
68adac5e | 407 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
c93bb85b | 408 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
68adac5e | 409 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
c93bb85b JG |
410 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
411 | } | |
412 | /* We assume worst case 32bits (4 bytes) */ | |
68adac5e | 413 | wm->dbpp.full = dfixed_const(4 * 8); |
c93bb85b JG |
414 | |
415 | /* Determine the maximum priority mark | |
416 | * width = viewport width in pixels | |
417 | */ | |
68adac5e BS |
418 | a.full = dfixed_const(16); |
419 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); | |
420 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); | |
421 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); | |
c93bb85b JG |
422 | |
423 | /* Determine estimated width */ | |
424 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; | |
68adac5e BS |
425 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
426 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { | |
427 | wm->priority_mark.full = dfixed_const(10); | |
c93bb85b | 428 | } else { |
68adac5e BS |
429 | a.full = dfixed_const(16); |
430 | wm->priority_mark.full = dfixed_div(estimated_width, a); | |
431 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); | |
c93bb85b JG |
432 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
433 | } | |
434 | } | |
435 | ||
3a4d8f7b AD |
436 | static void rs690_compute_mode_priority(struct radeon_device *rdev, |
437 | struct rs690_watermark *wm0, | |
438 | struct rs690_watermark *wm1, | |
439 | struct drm_display_mode *mode0, | |
440 | struct drm_display_mode *mode1, | |
441 | u32 *d1mode_priority_a_cnt, | |
442 | u32 *d2mode_priority_a_cnt) | |
c93bb85b | 443 | { |
c93bb85b JG |
444 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
445 | fixed20_12 a, b; | |
446 | ||
3a4d8f7b AD |
447 | *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); |
448 | *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); | |
c93bb85b JG |
449 | |
450 | if (mode0 && mode1) { | |
3a4d8f7b AD |
451 | if (dfixed_trunc(wm0->dbpp) > 64) |
452 | a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); | |
c93bb85b | 453 | else |
3a4d8f7b AD |
454 | a.full = wm0->num_line_pair.full; |
455 | if (dfixed_trunc(wm1->dbpp) > 64) | |
456 | b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); | |
c93bb85b | 457 | else |
3a4d8f7b | 458 | b.full = wm1->num_line_pair.full; |
c93bb85b | 459 | a.full += b.full; |
3a4d8f7b AD |
460 | fill_rate.full = dfixed_div(wm0->sclk, a); |
461 | if (wm0->consumption_rate.full > fill_rate.full) { | |
462 | b.full = wm0->consumption_rate.full - fill_rate.full; | |
463 | b.full = dfixed_mul(b, wm0->active_time); | |
464 | a.full = dfixed_mul(wm0->worst_case_latency, | |
465 | wm0->consumption_rate); | |
c93bb85b | 466 | a.full = a.full + b.full; |
68adac5e BS |
467 | b.full = dfixed_const(16 * 1000); |
468 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b | 469 | } else { |
3a4d8f7b AD |
470 | a.full = dfixed_mul(wm0->worst_case_latency, |
471 | wm0->consumption_rate); | |
68adac5e BS |
472 | b.full = dfixed_const(16 * 1000); |
473 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b | 474 | } |
3a4d8f7b AD |
475 | if (wm1->consumption_rate.full > fill_rate.full) { |
476 | b.full = wm1->consumption_rate.full - fill_rate.full; | |
477 | b.full = dfixed_mul(b, wm1->active_time); | |
478 | a.full = dfixed_mul(wm1->worst_case_latency, | |
479 | wm1->consumption_rate); | |
c93bb85b | 480 | a.full = a.full + b.full; |
68adac5e BS |
481 | b.full = dfixed_const(16 * 1000); |
482 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b | 483 | } else { |
3a4d8f7b AD |
484 | a.full = dfixed_mul(wm1->worst_case_latency, |
485 | wm1->consumption_rate); | |
68adac5e BS |
486 | b.full = dfixed_const(16 * 1000); |
487 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b | 488 | } |
3a4d8f7b AD |
489 | if (wm0->priority_mark.full > priority_mark02.full) |
490 | priority_mark02.full = wm0->priority_mark.full; | |
68adac5e | 491 | if (dfixed_trunc(priority_mark02) < 0) |
c93bb85b | 492 | priority_mark02.full = 0; |
3a4d8f7b AD |
493 | if (wm0->priority_mark_max.full > priority_mark02.full) |
494 | priority_mark02.full = wm0->priority_mark_max.full; | |
495 | if (wm1->priority_mark.full > priority_mark12.full) | |
496 | priority_mark12.full = wm1->priority_mark.full; | |
68adac5e | 497 | if (dfixed_trunc(priority_mark12) < 0) |
c93bb85b | 498 | priority_mark12.full = 0; |
3a4d8f7b AD |
499 | if (wm1->priority_mark_max.full > priority_mark12.full) |
500 | priority_mark12.full = wm1->priority_mark_max.full; | |
501 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | |
502 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
f46c0120 | 503 | if (rdev->disp_priority == 2) { |
3a4d8f7b AD |
504 | *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
505 | *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | |
f46c0120 | 506 | } |
c93bb85b | 507 | } else if (mode0) { |
3a4d8f7b AD |
508 | if (dfixed_trunc(wm0->dbpp) > 64) |
509 | a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); | |
c93bb85b | 510 | else |
3a4d8f7b AD |
511 | a.full = wm0->num_line_pair.full; |
512 | fill_rate.full = dfixed_div(wm0->sclk, a); | |
513 | if (wm0->consumption_rate.full > fill_rate.full) { | |
514 | b.full = wm0->consumption_rate.full - fill_rate.full; | |
515 | b.full = dfixed_mul(b, wm0->active_time); | |
516 | a.full = dfixed_mul(wm0->worst_case_latency, | |
517 | wm0->consumption_rate); | |
c93bb85b | 518 | a.full = a.full + b.full; |
68adac5e BS |
519 | b.full = dfixed_const(16 * 1000); |
520 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b | 521 | } else { |
3a4d8f7b AD |
522 | a.full = dfixed_mul(wm0->worst_case_latency, |
523 | wm0->consumption_rate); | |
68adac5e BS |
524 | b.full = dfixed_const(16 * 1000); |
525 | priority_mark02.full = dfixed_div(a, b); | |
c93bb85b | 526 | } |
3a4d8f7b AD |
527 | if (wm0->priority_mark.full > priority_mark02.full) |
528 | priority_mark02.full = wm0->priority_mark.full; | |
68adac5e | 529 | if (dfixed_trunc(priority_mark02) < 0) |
c93bb85b | 530 | priority_mark02.full = 0; |
3a4d8f7b AD |
531 | if (wm0->priority_mark_max.full > priority_mark02.full) |
532 | priority_mark02.full = wm0->priority_mark_max.full; | |
533 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | |
f46c0120 | 534 | if (rdev->disp_priority == 2) |
3a4d8f7b | 535 | *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
e06b14ee | 536 | } else if (mode1) { |
3a4d8f7b AD |
537 | if (dfixed_trunc(wm1->dbpp) > 64) |
538 | a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); | |
c93bb85b | 539 | else |
3a4d8f7b AD |
540 | a.full = wm1->num_line_pair.full; |
541 | fill_rate.full = dfixed_div(wm1->sclk, a); | |
542 | if (wm1->consumption_rate.full > fill_rate.full) { | |
543 | b.full = wm1->consumption_rate.full - fill_rate.full; | |
544 | b.full = dfixed_mul(b, wm1->active_time); | |
545 | a.full = dfixed_mul(wm1->worst_case_latency, | |
546 | wm1->consumption_rate); | |
c93bb85b | 547 | a.full = a.full + b.full; |
68adac5e BS |
548 | b.full = dfixed_const(16 * 1000); |
549 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b | 550 | } else { |
3a4d8f7b AD |
551 | a.full = dfixed_mul(wm1->worst_case_latency, |
552 | wm1->consumption_rate); | |
68adac5e BS |
553 | b.full = dfixed_const(16 * 1000); |
554 | priority_mark12.full = dfixed_div(a, b); | |
c93bb85b | 555 | } |
3a4d8f7b AD |
556 | if (wm1->priority_mark.full > priority_mark12.full) |
557 | priority_mark12.full = wm1->priority_mark.full; | |
68adac5e | 558 | if (dfixed_trunc(priority_mark12) < 0) |
c93bb85b | 559 | priority_mark12.full = 0; |
3a4d8f7b AD |
560 | if (wm1->priority_mark_max.full > priority_mark12.full) |
561 | priority_mark12.full = wm1->priority_mark_max.full; | |
562 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | |
f46c0120 | 563 | if (rdev->disp_priority == 2) |
3a4d8f7b | 564 | *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
c93bb85b | 565 | } |
3a4d8f7b AD |
566 | } |
567 | ||
568 | void rs690_bandwidth_update(struct radeon_device *rdev) | |
569 | { | |
570 | struct drm_display_mode *mode0 = NULL; | |
571 | struct drm_display_mode *mode1 = NULL; | |
572 | struct rs690_watermark wm0_high, wm0_low; | |
573 | struct rs690_watermark wm1_high, wm1_low; | |
574 | u32 tmp; | |
575 | u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; | |
576 | u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; | |
577 | ||
578 | radeon_update_display_priority(rdev); | |
579 | ||
580 | if (rdev->mode_info.crtcs[0]->base.enabled) | |
581 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; | |
582 | if (rdev->mode_info.crtcs[1]->base.enabled) | |
583 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; | |
584 | /* | |
585 | * Set display0/1 priority up in the memory controller for | |
586 | * modes if the user specifies HIGH for displaypriority | |
587 | * option. | |
588 | */ | |
589 | if ((rdev->disp_priority == 2) && | |
590 | ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { | |
591 | tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); | |
592 | tmp &= C_000104_MC_DISP0R_INIT_LAT; | |
593 | tmp &= C_000104_MC_DISP1R_INIT_LAT; | |
594 | if (mode0) | |
595 | tmp |= S_000104_MC_DISP0R_INIT_LAT(1); | |
596 | if (mode1) | |
597 | tmp |= S_000104_MC_DISP1R_INIT_LAT(1); | |
598 | WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); | |
599 | } | |
600 | rs690_line_buffer_adjust(rdev, mode0, mode1); | |
601 | ||
602 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) | |
603 | WREG32(R_006C9C_DCP_CONTROL, 0); | |
604 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) | |
605 | WREG32(R_006C9C_DCP_CONTROL, 2); | |
606 | ||
607 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); | |
608 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); | |
609 | ||
610 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); | |
611 | rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); | |
612 | ||
613 | tmp = (wm0_high.lb_request_fifo_depth - 1); | |
614 | tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16; | |
615 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); | |
616 | ||
617 | rs690_compute_mode_priority(rdev, | |
618 | &wm0_high, &wm1_high, | |
619 | mode0, mode1, | |
620 | &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); | |
621 | rs690_compute_mode_priority(rdev, | |
622 | &wm0_low, &wm1_low, | |
623 | mode0, mode1, | |
624 | &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); | |
e06b14ee AD |
625 | |
626 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | |
3a4d8f7b | 627 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); |
e06b14ee | 628 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
3a4d8f7b | 629 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); |
c93bb85b | 630 | } |
771fe6b9 | 631 | |
771fe6b9 JG |
632 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
633 | { | |
0a5b7b0b | 634 | unsigned long flags; |
771fe6b9 JG |
635 | uint32_t r; |
636 | ||
0a5b7b0b | 637 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
3bc68535 JG |
638 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); |
639 | r = RREG32(R_00007C_MC_DATA); | |
640 | WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); | |
0a5b7b0b | 641 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
771fe6b9 JG |
642 | return r; |
643 | } | |
644 | ||
645 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
646 | { | |
0a5b7b0b AD |
647 | unsigned long flags; |
648 | ||
649 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); | |
3bc68535 JG |
650 | WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | |
651 | S_000078_MC_IND_WR_EN(1)); | |
652 | WREG32(R_00007C_MC_DATA, v); | |
653 | WREG32(R_000078_MC_INDEX, 0x7F); | |
0a5b7b0b | 654 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
3bc68535 JG |
655 | } |
656 | ||
1109ca09 | 657 | static void rs690_mc_program(struct radeon_device *rdev) |
3bc68535 JG |
658 | { |
659 | struct rv515_mc_save save; | |
660 | ||
661 | /* Stops all mc clients */ | |
662 | rv515_mc_stop(rdev, &save); | |
663 | ||
664 | /* Wait for mc idle */ | |
665 | if (rs690_mc_wait_for_idle(rdev)) | |
666 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
667 | /* Program MC, should be a 32bits limited address space */ | |
668 | WREG32_MC(R_000100_MCCFG_FB_LOCATION, | |
669 | S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | | |
670 | S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
671 | WREG32(R_000134_HDP_FB_LOCATION, | |
672 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
673 | ||
674 | rv515_mc_resume(rdev, &save); | |
675 | } | |
676 | ||
677 | static int rs690_startup(struct radeon_device *rdev) | |
678 | { | |
679 | int r; | |
680 | ||
681 | rs690_mc_program(rdev); | |
682 | /* Resume clock */ | |
683 | rv515_clock_startup(rdev); | |
684 | /* Initialize GPU configuration (# pipes, ...) */ | |
685 | rs690_gpu_init(rdev); | |
686 | /* Initialize GART (initialize after TTM so we can allocate | |
687 | * memory through TTM but finalize after TTM) */ | |
688 | r = rs400_gart_enable(rdev); | |
689 | if (r) | |
690 | return r; | |
724c80e1 AD |
691 | |
692 | /* allocate wb buffer */ | |
693 | r = radeon_wb_init(rdev); | |
694 | if (r) | |
695 | return r; | |
696 | ||
30eb77f4 JG |
697 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
698 | if (r) { | |
699 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
700 | return r; | |
701 | } | |
702 | ||
3bc68535 | 703 | /* Enable IRQ */ |
e49f3959 AH |
704 | if (!rdev->irq.installed) { |
705 | r = radeon_irq_kms_init(rdev); | |
706 | if (r) | |
707 | return r; | |
708 | } | |
709 | ||
ac447df4 | 710 | rs600_irq_set(rdev); |
cafe6609 | 711 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
3bc68535 JG |
712 | /* 1M ring buffer */ |
713 | r = r100_cp_init(rdev, 1024 * 1024); | |
714 | if (r) { | |
ec4f2ac4 | 715 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
3bc68535 JG |
716 | return r; |
717 | } | |
b15ba512 | 718 | |
2898c348 CK |
719 | r = radeon_ib_pool_init(rdev); |
720 | if (r) { | |
721 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 722 | return r; |
2898c348 | 723 | } |
b15ba512 | 724 | |
d4e30ef0 AD |
725 | r = r600_audio_init(rdev); |
726 | if (r) { | |
727 | dev_err(rdev->dev, "failed initializing audio\n"); | |
728 | return r; | |
729 | } | |
730 | ||
3bc68535 JG |
731 | return 0; |
732 | } | |
733 | ||
734 | int rs690_resume(struct radeon_device *rdev) | |
735 | { | |
6b7746e8 JG |
736 | int r; |
737 | ||
3bc68535 JG |
738 | /* Make sur GART are not working */ |
739 | rs400_gart_disable(rdev); | |
740 | /* Resume clock before doing reset */ | |
741 | rv515_clock_startup(rdev); | |
742 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 743 | if (radeon_asic_reset(rdev)) { |
3bc68535 JG |
744 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
745 | RREG32(R_000E40_RBBM_STATUS), | |
746 | RREG32(R_0007C0_CP_STAT)); | |
747 | } | |
748 | /* post */ | |
749 | atom_asic_init(rdev->mode_info.atom_context); | |
750 | /* Resume clock after posting */ | |
751 | rv515_clock_startup(rdev); | |
550e2d92 DA |
752 | /* Initialize surface registers */ |
753 | radeon_surface_init(rdev); | |
b15ba512 JG |
754 | |
755 | rdev->accel_working = true; | |
6b7746e8 JG |
756 | r = rs690_startup(rdev); |
757 | if (r) { | |
758 | rdev->accel_working = false; | |
759 | } | |
760 | return r; | |
3bc68535 JG |
761 | } |
762 | ||
763 | int rs690_suspend(struct radeon_device *rdev) | |
764 | { | |
fe50ac78 | 765 | r600_audio_fini(rdev); |
3bc68535 | 766 | r100_cp_disable(rdev); |
724c80e1 | 767 | radeon_wb_disable(rdev); |
ac447df4 | 768 | rs600_irq_disable(rdev); |
3bc68535 JG |
769 | rs400_gart_disable(rdev); |
770 | return 0; | |
771 | } | |
772 | ||
773 | void rs690_fini(struct radeon_device *rdev) | |
774 | { | |
fe50ac78 | 775 | r600_audio_fini(rdev); |
3bc68535 | 776 | r100_cp_fini(rdev); |
724c80e1 | 777 | radeon_wb_fini(rdev); |
2898c348 | 778 | radeon_ib_pool_fini(rdev); |
3bc68535 JG |
779 | radeon_gem_fini(rdev); |
780 | rs400_gart_fini(rdev); | |
781 | radeon_irq_kms_fini(rdev); | |
782 | radeon_fence_driver_fini(rdev); | |
4c788679 | 783 | radeon_bo_fini(rdev); |
3bc68535 JG |
784 | radeon_atombios_fini(rdev); |
785 | kfree(rdev->bios); | |
786 | rdev->bios = NULL; | |
787 | } | |
788 | ||
789 | int rs690_init(struct radeon_device *rdev) | |
790 | { | |
791 | int r; | |
792 | ||
3bc68535 JG |
793 | /* Disable VGA */ |
794 | rv515_vga_render_disable(rdev); | |
795 | /* Initialize scratch registers */ | |
796 | radeon_scratch_init(rdev); | |
797 | /* Initialize surface registers */ | |
798 | radeon_surface_init(rdev); | |
4c712e6c DA |
799 | /* restore some register to sane defaults */ |
800 | r100_restore_sanity(rdev); | |
3bc68535 JG |
801 | /* TODO: disable VGA need to use VGA request */ |
802 | /* BIOS*/ | |
803 | if (!radeon_get_bios(rdev)) { | |
804 | if (ASIC_IS_AVIVO(rdev)) | |
805 | return -EINVAL; | |
806 | } | |
807 | if (rdev->is_atom_bios) { | |
808 | r = radeon_atombios_init(rdev); | |
809 | if (r) | |
810 | return r; | |
811 | } else { | |
812 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
813 | return -EINVAL; | |
814 | } | |
815 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 816 | if (radeon_asic_reset(rdev)) { |
3bc68535 JG |
817 | dev_warn(rdev->dev, |
818 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
819 | RREG32(R_000E40_RBBM_STATUS), | |
820 | RREG32(R_0007C0_CP_STAT)); | |
821 | } | |
822 | /* check if cards are posted or not */ | |
72542d77 DA |
823 | if (radeon_boot_test_post_card(rdev) == false) |
824 | return -EINVAL; | |
825 | ||
3bc68535 JG |
826 | /* Initialize clocks */ |
827 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
828 | /* initialize memory controller */ |
829 | rs690_mc_init(rdev); | |
3bc68535 JG |
830 | rv515_debugfs(rdev); |
831 | /* Fence driver */ | |
30eb77f4 | 832 | r = radeon_fence_driver_init(rdev); |
3bc68535 JG |
833 | if (r) |
834 | return r; | |
835 | /* Memory manager */ | |
4c788679 | 836 | r = radeon_bo_init(rdev); |
3bc68535 JG |
837 | if (r) |
838 | return r; | |
839 | r = rs400_gart_init(rdev); | |
840 | if (r) | |
841 | return r; | |
842 | rs600_set_safe_registers(rdev); | |
b15ba512 | 843 | |
3bc68535 JG |
844 | rdev->accel_working = true; |
845 | r = rs690_startup(rdev); | |
846 | if (r) { | |
847 | /* Somethings want wront with the accel init stop accel */ | |
848 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
3bc68535 | 849 | r100_cp_fini(rdev); |
724c80e1 | 850 | radeon_wb_fini(rdev); |
2898c348 | 851 | radeon_ib_pool_fini(rdev); |
3bc68535 JG |
852 | rs400_gart_fini(rdev); |
853 | radeon_irq_kms_fini(rdev); | |
854 | rdev->accel_working = false; | |
855 | } | |
856 | return 0; | |
771fe6b9 | 857 | } |